u-boot.git/include/pch.h, branch v2017.01 Unnamed repository; edit this file 'description' to name the repository. dm: pch: Add get_io_base op 2016-02-05T04:47:21+00:00 Bin Meng bmeng.cn@gmail.com 2016-02-01T09:40:45+00:00 79d4eb627cffbc3ab7cefdd623fa39fefaaedbe7 On some newer chipset (eg: BayTrail), there is an IO base address register on the PCH device which configures the base address of a memory-mapped I/O controller. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> 
On some newer chipset (eg: BayTrail), there is an IO base address
register on the PCH device which configures the base address of a
memory-mapped I/O controller.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
dm: pch: Add get_gpio_base op 2016-02-05T04:47:21+00:00 Bin Meng bmeng.cn@gmail.com 2016-02-01T09:40:43+00:00 384980c687ca38c028bdf40f59a38b3f52105884 x86 GPIO registers are accessed via I/O port whose base address is configured in a PCI configuration register on the PCH device. Add an op get_gpio_base to get the GPIO base address from PCH. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> 
x86 GPIO registers are accessed via I/O port whose base address is
configured in a PCI configuration register on the PCH device. Add
an op get_gpio_base to get the GPIO base address from PCH.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
dm: pch: Rename get_sbase op to get_spi_base 2016-02-05T04:47:21+00:00 Bin Meng bmeng.cn@gmail.com 2016-02-01T09:40:42+00:00 3e389d8ba666c5c2ad42021c2087630c1e412954 Spell out 'sbase' to 'spi_base' so that it looks clearer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> 
Spell out 'sbase' to 'spi_base' so that it looks clearer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
dm: pch: Remove pch_get_version op 2016-02-05T04:47:21+00:00 Bin Meng bmeng.cn@gmail.com 2016-02-01T09:40:41+00:00 d02be99e6774b99c27b7d4304865c7f45e1ac4b4 pch_get_version op was only used by the ich spi controller driver, and does not really provide a good identification of pch controller so far, since we see plenty of Intel PCH chipsets and one differs from another a lot, which is not simply either a PCHV_7 or PCHV_9. Now that ich spi controller driver was updated to not get such info from pch, the pch_get_version op is useless now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> 
pch_get_version op was only used by the ich spi controller driver,
and does not really provide a good identification of pch controller
so far, since we see plenty of Intel PCH chipsets and one differs
from another a lot, which is not simply either a PCHV_7 or PCHV_9.
Now that ich spi controller driver was updated to not get such info
from pch, the pch_get_version op is useless now.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
dm: x86: Add a driver for Intel PCH7 2016-01-24T04:07:17+00:00 Simon Glass sjg@chromium.org 2016-01-19T03:19:18+00:00 1ff4f321b69950acca1b06daed89d872a52a337c At some point we may need to distinguish between different types of PCHs, but for existing supported platforms we only need to worry about version 7 and version 9 bridges. Add a driver for the PCH7. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
At some point we may need to distinguish between different types of PCHs,
but for existing supported platforms we only need to worry about version 7
and version 9 bridges. Add a driver for the PCH7.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
dm: Expand the uclass for Platform Controller Hubs (PCH) 2016-01-24T04:07:17+00:00 Simon Glass sjg@chromium.org 2016-01-19T03:19:17+00:00 ca831f4933dc68d9ed1b6399cbda90068c520005 A Platform Controller Hub is an Intel concept - it is like the peripherals on an SoC and is often in a separate chip from the CPU. The chip is typically found on the first PCI bus and integrates multiple devices. We have a very simple uclass to support PCHs. Add a few operations, such as setting up the devices on the PCH and finding the SPI controller base address. Also move it into drivers/pch/ since we will be adding a few PCH drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
A Platform Controller Hub is an Intel concept - it is like the peripherals
on an SoC and is often in a separate chip from the CPU. The chip is typically
found on the first PCI bus and integrates multiple devices.

We have a very simple uclass to support PCHs. Add a few operations, such as
setting up the devices on the PCH and finding the SPI controller base
address. Also move it into drivers/pch/ since we will be adding a few PCH
drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>