u-boot.git/include/pci.h, branch v2014.01

pci.h: allow inclusion in assembly source

2013-11-09T16:21:01+00:00

This patch simply #ifdef's out the C-specific parts of pci.h when it is
included by an assembly file. This will allow the macros it contains to
be used from assembly source as will be done in a followup commit adding
support for more modern MIPS Malta boards.

Signed-off-by: Paul Burton

PCIe:change the method to get the address of a requested capability in configuration space.

2013-10-16T23:15:17+00:00

Previously, the address of a requested capability is define like that
	"#define PCI_DCR	0x78"
But, the addresses of capabilities is different with regard to PCIe revs.
So this method is not flexible.

Now a function to get the address of a requested capability is added and used.
It can get the address dynamically by capability ID.
The step of this function:
	1. Read Status register in PCIe configuration space to confirm that
	   Capabilities List is valid.
	2. Find the address of Capabilities Pointer Register.
	3. Find the address of requested capability from the first capability.

Signed-off-by: Zhao Qiang

powerpc/pcie: add PCIe version 3.x support

2013-08-09T19:41:41+00:00

T4240 PCIe IP is version 3.0 and has some update comparing previous
QorIQ products.

1.  Move Freescale specific register define
to
arch/powerpc/include/asm/fsl_pci.h
and update the register offset define for T4240.

2. add the status/control register define
use status/control register to judge the link status

3. The original code uses 'Programming Interface' field to judge if PCIE is
EP or RC mode, however, T4240 does not support this functionality.
According to PCIE specification, 'Header Type' offset 0x0e is used to
indicate header type, so for PCIE controller, the patch changes code to
use 'Header Type' field to identify if the PCIE is RC or EP mode.

This patch fixes  the PCIe card link up issue on T4240QDS.

Signed-off-by: Roy Zang 
Signed-off-by: Minghuan Lian 
Signed-off-by: York Sun

Add GPL-2.0+ SPDX-License-Identifier to source files

2013-07-24T13:44:38+00:00

Signed-off-by: Wolfgang Denk 
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini

pci: Convert extern inline functions to static inline

2013-06-26T14:16:40+00:00

I am not sure of the meaning of extern inline, but this gives errors
when building with function instrumenting enabled. Change these functions
to static inline.

Signed-off-by: Simon Glass

pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option

2013-06-07T18:17:01+00:00

The pci_indirect.c file is always compiled when
CONFIG_PCI is defined although the indirect PCI
bridge support is not needed by every board.

Introduce a new CONFIG_PCI_INDIRECT_BRIDGE
config option and only compile indirect PCI
bridge support if this options is enabled.

Also add the new option into the configuration
files of the boards which needs that.

Compile tested for powerpc, x86, arm and nds32.
MAKEALL results:

powerpc:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 641
  Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB )
  ----------------------------------------------------------
  Note: the warnings for ELPPC and MPC8323ERDB are present even
  without the actual patch.

x86:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 1
  ----------------------------------------------------------

arm:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 311
  ----------------------------------------------------------

nds32:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 3
  ----------------------------------------------------------

Cc: Tom Rini 
Cc: Daniel Schwierzeck 
Signed-off-by: Gabor Juhos

x86: gpio: Add GPIO driver for Intel ICH6 and later.

2012-12-06T22:30:38+00:00

Implement  functions for Intel ICH6 and later.
Only GPIOs 0-31 are handled by this code.

Signed-off-by: Bill Richardson 

Signed-off-by: Simon Glass

pci: declare pciauto functions in header

2012-03-30T20:46:00+00:00

The FSL PCI driver uses local prototypes for
pciauto_[pre|post]scan_setup_bridge(), this does not seem right,
so move them to the  file.

Fixed a small extern declaration too, this is harmless but distracts
the view since all other prototypes are explicitly external.

Signed-off-by: Linus Walleij

pci: move pciauto_config_init() to pci.h

2012-03-04T20:13:33+00:00

Fixing build regressions for the Integrator I get find that a few
boards try to work around the missing declaration of
pciauto_config_init() by declaring it in the local scope. This
does not make sense when the sibling functions are in 
so move the function to the header, ridding the build error
in the Integrator and getting rid of the local declarations
here and there.

Reported-by:  Wolfgang Denk 
Signed-off-by: Linus Walleij

powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs

2011-03-29T12:41:37+00:00

The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require
that we initialize the SERDES registers if the lanes are configured for
PCIe.  Additionally these devices PCIe controller do not support ASPM
and we have to explicitly disable it.

Signed-off-by: Prabhakar Kushwaha 
Signed-off-by: Kumar Gala