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<title>u-boot.git/include/pci.h, branch v2015.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>powerpc: mpc824x: remove MPC824X cpu support</title>
<updated>2015-01-05T17:08:55+00:00</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2014-12-15T14:26:31+00:00</published>
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<id>d622ac39274a949b6445f1bfd92dc1644014388b</id>
<content type='text'>
All the MPC824X boards are still non-generic boards:
A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Josef Wagner &lt;Wagner@Microsys.de&gt;
Cc: Torsten Demke &lt;torsten.demke@fci.com&gt;
Cc: Jim Thompson &lt;jim@musenki.com&gt;
Cc: Greg Allen &lt;gallen@arlut.utexas.edu&gt;
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<pre>
All the MPC824X boards are still non-generic boards:
A3000, CPC45, CU824, eXalion, MVBLUE, MUSENKI, Sandpoint824x, utx8245

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Josef Wagner &lt;Wagner@Microsys.de&gt;
Cc: Torsten Demke &lt;torsten.demke@fci.com&gt;
Cc: Jim Thompson &lt;jim@musenki.com&gt;
Cc: Greg Allen &lt;gallen@arlut.utexas.edu&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: Add functions to read and write a BAR address</title>
<updated>2014-11-25T13:34:00+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2014-11-15T01:18:30+00:00</published>
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<id>e8a552eb625f0b2d7a778d151af25a17c6d33b7b</id>
<content type='text'>
Some PCI functions cannot be auto-configured. Add a function to set up a
fixed BAR which can be used in these situations. Also add a function to read
the current address of a BAR.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
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<pre>
Some PCI functions cannot be auto-configured. Add a function to set up a
fixed BAR which can be used in these situations. Also add a function to read
the current address of a BAR.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: Honour pci_skip_dev()</title>
<updated>2014-11-23T11:49:01+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-11-13T01:26:49+00:00</published>
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<content type='text'>
When enumerating devices, honour the pci_skip_dev() function. This can
be used by PCI controller drivers to restrict which devices will be
probed.

This is required by the NVIDIA Tegra PCIe controller driver, which will
fail with a data abort exception if an access is attempted to a device
number larger than 0 outside of bus 0. pci_skip_dev() is therefore
implemented to prevent any such accesses.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
When enumerating devices, honour the pci_skip_dev() function. This can
be used by PCI controller drivers to restrict which devices will be
probed.

This is required by the NVIDIA Tegra PCIe controller driver, which will
fail with a data abort exception if an access is attempted to a device
number larger than 0 outside of bus 0. pci_skip_dev() is therefore
implemented to prevent any such accesses.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: add support for board_pci_fixup_dev function</title>
<updated>2014-09-09T14:15:02+00:00</updated>
<author>
<name>Tim Harvey</name>
<email>tharvey@gateworks.com</email>
</author>
<published>2014-08-08T05:49:56+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0991866cf7a10d4868aa2a10940b4def0f68cc50'/>
<id>0991866cf7a10d4868aa2a10940b4def0f68cc50</id>
<content type='text'>
Some board-level drivers may wish to have per-device fixup functions
for PCI devices.

Signed-off-by: Tim Harvey &lt;tharvey@gateworks.com&gt;
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<pre>
Some board-level drivers may wish to have per-device fixup functions
for PCI devices.

Signed-off-by: Tim Harvey &lt;tharvey@gateworks.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci.h: allow inclusion in assembly source</title>
<updated>2013-11-09T16:21:01+00:00</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2013-11-08T11:18:47+00:00</published>
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<content type='text'>
This patch simply #ifdef's out the C-specific parts of pci.h when it is
included by an assembly file. This will allow the macros it contains to
be used from assembly source as will be done in a followup commit adding
support for more modern MIPS Malta boards.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
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<pre>
This patch simply #ifdef's out the C-specific parts of pci.h when it is
included by an assembly file. This will allow the macros it contains to
be used from assembly source as will be done in a followup commit adding
support for more modern MIPS Malta boards.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>PCIe:change the method to get the address of a requested capability in configuration space.</title>
<updated>2013-10-16T23:15:17+00:00</updated>
<author>
<name>Zhao Qiang</name>
<email>B45475@freescale.com</email>
</author>
<published>2013-10-12T05:46:33+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=287df01e6aef0464c5e5bcbd7e87aa4ff1f24f5a'/>
<id>287df01e6aef0464c5e5bcbd7e87aa4ff1f24f5a</id>
<content type='text'>
Previously, the address of a requested capability is define like that
	"#define PCI_DCR	0x78"
But, the addresses of capabilities is different with regard to PCIe revs.
So this method is not flexible.

Now a function to get the address of a requested capability is added and used.
It can get the address dynamically by capability ID.
The step of this function:
	1. Read Status register in PCIe configuration space to confirm that
	   Capabilities List is valid.
	2. Find the address of Capabilities Pointer Register.
	3. Find the address of requested capability from the first capability.

Signed-off-by: Zhao Qiang &lt;B45475@freescale.com&gt;
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<pre>
Previously, the address of a requested capability is define like that
	"#define PCI_DCR	0x78"
But, the addresses of capabilities is different with regard to PCIe revs.
So this method is not flexible.

Now a function to get the address of a requested capability is added and used.
It can get the address dynamically by capability ID.
The step of this function:
	1. Read Status register in PCIe configuration space to confirm that
	   Capabilities List is valid.
	2. Find the address of Capabilities Pointer Register.
	3. Find the address of requested capability from the first capability.

Signed-off-by: Zhao Qiang &lt;B45475@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/pcie: add PCIe version 3.x support</title>
<updated>2013-08-09T19:41:41+00:00</updated>
<author>
<name>Zang Roy-R61911</name>
<email>tie-fei.zang@freescale.com</email>
</author>
<published>2013-07-03T23:25:03+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7b4e58440f7813a952133e77f2d9c4a475730e40'/>
<id>7b4e58440f7813a952133e77f2d9c4a475730e40</id>
<content type='text'>
T4240 PCIe IP is version 3.0 and has some update comparing previous
QorIQ products.

1.  Move Freescale specific register define
to
arch/powerpc/include/asm/fsl_pci.h
and update the register offset define for T4240.

2. add the status/control register define
use status/control register to judge the link status

3. The original code uses 'Programming Interface' field to judge if PCIE is
EP or RC mode, however, T4240 does not support this functionality.
According to PCIE specification, 'Header Type' offset 0x0e is used to
indicate header type, so for PCIE controller, the patch changes code to
use 'Header Type' field to identify if the PCIE is RC or EP mode.

This patch fixes  the PCIe card link up issue on T4240QDS.

Signed-off-by: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
Signed-off-by: Minghuan Lian &lt;Minghuan.Lian@freescale.com&gt;
Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</content>
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<pre>
T4240 PCIe IP is version 3.0 and has some update comparing previous
QorIQ products.

1.  Move Freescale specific register define
to
arch/powerpc/include/asm/fsl_pci.h
and update the register offset define for T4240.

2. add the status/control register define
use status/control register to judge the link status

3. The original code uses 'Programming Interface' field to judge if PCIE is
EP or RC mode, however, T4240 does not support this functionality.
According to PCIE specification, 'Header Type' offset 0x0e is used to
indicate header type, so for PCIE controller, the patch changes code to
use 'Header Type' field to identify if the PCIE is RC or EP mode.

This patch fixes  the PCIe card link up issue on T4240QDS.

Signed-off-by: Roy Zang &lt;tie-fei.zang@freescale.com&gt;
Signed-off-by: Minghuan Lian &lt;Minghuan.Lian@freescale.com&gt;
Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Add GPL-2.0+ SPDX-License-Identifier to source files</title>
<updated>2013-07-24T13:44:38+00:00</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2013-07-08T07:37:19+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1a4596601fd395f3afb8f82f3f840c5e00bdd57a'/>
<id>1a4596601fd395f3afb8f82f3f840c5e00bdd57a</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
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<pre>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: Convert extern inline functions to static inline</title>
<updated>2013-06-26T14:16:40+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2013-06-11T18:14:33+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=bc3442aaed26f16a0b9d1caa55cbe3bd94d16a86'/>
<id>bc3442aaed26f16a0b9d1caa55cbe3bd94d16a86</id>
<content type='text'>
I am not sure of the meaning of extern inline, but this gives errors
when building with function instrumenting enabled. Change these functions
to static inline.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
I am not sure of the meaning of extern inline, but this gives errors
when building with function instrumenting enabled. Change these functions
to static inline.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option</title>
<updated>2013-06-07T18:17:01+00:00</updated>
<author>
<name>Gabor Juhos</name>
<email>juhosg@openwrt.org</email>
</author>
<published>2013-05-30T07:06:12+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=842033e6964e9e5d34aca893c1845416dd8ac2cc'/>
<id>842033e6964e9e5d34aca893c1845416dd8ac2cc</id>
<content type='text'>
The pci_indirect.c file is always compiled when
CONFIG_PCI is defined although the indirect PCI
bridge support is not needed by every board.

Introduce a new CONFIG_PCI_INDIRECT_BRIDGE
config option and only compile indirect PCI
bridge support if this options is enabled.

Also add the new option into the configuration
files of the boards which needs that.

Compile tested for powerpc, x86, arm and nds32.
MAKEALL results:

powerpc:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 641
  Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB )
  ----------------------------------------------------------
  Note: the warnings for ELPPC and MPC8323ERDB are present even
  without the actual patch.

x86:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 1
  ----------------------------------------------------------

arm:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 311
  ----------------------------------------------------------

nds32:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 3
  ----------------------------------------------------------

Cc: Tom Rini &lt;trini@ti.com&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@googlemail.com&gt;
Signed-off-by: Gabor Juhos &lt;juhosg@openwrt.org&gt;
</content>
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<pre>
The pci_indirect.c file is always compiled when
CONFIG_PCI is defined although the indirect PCI
bridge support is not needed by every board.

Introduce a new CONFIG_PCI_INDIRECT_BRIDGE
config option and only compile indirect PCI
bridge support if this options is enabled.

Also add the new option into the configuration
files of the boards which needs that.

Compile tested for powerpc, x86, arm and nds32.
MAKEALL results:

powerpc:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 641
  Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB )
  ----------------------------------------------------------
  Note: the warnings for ELPPC and MPC8323ERDB are present even
  without the actual patch.

x86:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 1
  ----------------------------------------------------------

arm:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 311
  ----------------------------------------------------------

nds32:
  --------------------- SUMMARY ----------------------------
  Boards compiled: 3
  ----------------------------------------------------------

Cc: Tom Rini &lt;trini@ti.com&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@googlemail.com&gt;
Signed-off-by: Gabor Juhos &lt;juhosg@openwrt.org&gt;
</pre>
</div>
</content>
</entry>
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