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<title>u-boot.git/include/pci.h, branch v2020.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/include/pci.h?h=v2020.10</id>
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<updated>2020-08-25T06:01:16Z</updated>
<entry>
<title>pci: pci-uclass: Add VF BAR map support for Enhanced Allocation</title>
<updated>2020-08-25T06:01:16Z</updated>
<author>
<name>Suneel Garapati</name>
<email>sgarapati@marvell.com</email>
</author>
<published>2019-10-19T23:34:16Z</published>
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<id>urn:sha1:51eeae91c5e7b8f7c1bdf46aa6d6bb1675fd2ebc</id>
<content type='text'>
Makes dm_pci_map_bar API available to map BAR for Virtual function
PCI devices which support Enhanced Allocation.

Signed-off-by: Suneel Garapati &lt;sgarapati@marvell.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>pci: pci-uclass: Add support for Single-Root I/O Virtualization</title>
<updated>2020-08-25T06:01:16Z</updated>
<author>
<name>Suneel Garapati</name>
<email>sgarapati@marvell.com</email>
</author>
<published>2019-10-19T23:07:20Z</published>
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<id>urn:sha1:b8852dcfcb0facb37839a8cf9b01cb549153fba8</id>
<content type='text'>
SR-IOV - Single Root I/O Virtualization
PF - Physical Function VF - Virtual Function

If SR-IOV capability is present, use it to initialize Virtual Function
PCI device instances. pci_sriov_init function will read SR-IOV
registers to create VF devices under the PF PCI device and also bind
driver if available. This function needs to be invoked from Physical
function device driver which expects VF device support, creating
minimal impact on existing framework.

Signed-off-by: Suneel Garapati &lt;sgarapati@marvell.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>pci: pci-uclass: Dynamically allocate the PCI regions</title>
<updated>2020-08-25T03:41:09Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2020-07-23T14:34:10Z</published>
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<id>urn:sha1:e002474158d1054a7a2ff9a66149384c639ff242</id>
<content type='text'>
Instead of using a fixed length pre-allocated array of regions, this
patch moves to dynamically allocating the regions based on the number
of available regions plus the necessary regions for DRAM banks.

Since MAX_PCI_REGIONS is not needed any more, its removed completely
with this patch.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Thierry Reding &lt;treding@nvidia.com&gt;
Cc: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
</content>
</entry>
<entry>
<title>drivers: pci: add api to get dma regions</title>
<updated>2020-08-14T13:43:21Z</updated>
<author>
<name>Rayagonda Kokatanur</name>
<email>rayagonda.kokatanur@broadcom.com</email>
</author>
<published>2020-05-12T07:59:49Z</published>
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<id>urn:sha1:143eb5b1caf1d2f3f37dd9f2c26936df5949d367</id>
<content type='text'>
Add api to get dma regions.

Signed-off-by: Rayagonda Kokatanur &lt;rayagonda.kokatanur@broadcom.com&gt;
</content>
</entry>
<entry>
<title>pci: Add some PCI Express capability register offset definitions</title>
<updated>2020-07-10T09:49:28Z</updated>
<author>
<name>Sylwester Nawrocki</name>
<email>s.nawrocki@samsung.com</email>
</author>
<published>2020-05-25T11:39:57Z</published>
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<id>urn:sha1:db75485f5c1e09e8571bdf15a6e15a8b62696d76</id>
<content type='text'>
Add PCI Express capability definitions required by the Broadcom
STB PCIe controller driver.

Signed-off-by: Sylwester Nawrocki &lt;s.nawrocki@samsung.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Nicolas Saenz Julienne &lt;nsaenzjulienne@suse.de&gt;
Signed-off-by: Matthias Brugger &lt;mbrugger@suse.com&gt;
</content>
</entry>
<entry>
<title>pci: Move some PCIe register offset definitions to a common header</title>
<updated>2020-07-09T13:46:12Z</updated>
<author>
<name>Sylwester Nawrocki</name>
<email>s.nawrocki@samsung.com</email>
</author>
<published>2020-05-25T11:39:53Z</published>
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<id>urn:sha1:b6687e19f9d3fdd33e76991df3dfcba60961ce35</id>
<content type='text'>
Some PCI Express register offsets are currently defined in multiple
drivers, move them to a common header to avoid re-definitions and
as a pre-requisite for adding new PCIe driver.
While at it replace some spaces with tabs.

Signed-off-by: Sylwester Nawrocki &lt;s.nawrocki@samsung.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Nicolas Saenz Julienne &lt;nsaenzjulienne@suse.de&gt;
Signed-off-by: Matthias Brugger &lt;mbrugger@suse.com&gt;
</content>
</entry>
<entry>
<title>pci: Fix typo in definition for PCI_DEV</title>
<updated>2020-05-15T17:53:50Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-10T16:26:54Z</published>
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<id>urn:sha1:5f20c283f9c232b226758f23b55c761790457b34</id>
<content type='text'>
Fix a typo in the comment.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>pci: Add a macro to convert BDF from linux to U-Boot</title>
<updated>2020-04-24T20:40:09Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-04-08T14:32:59Z</published>
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<id>urn:sha1:f05970380e4c72a198cce29affc622a8e543b4de</id>
<content type='text'>
U-Boot's BDF format has its bits in the same position as the device tree
PCI definition.

Some x86 devices use linux format in their register format and it is
useful to be able to convert to U-Boot format. Add a macro for this.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>pci: definition of pci_addr_t and pci_size_t</title>
<updated>2020-02-13T15:10:50Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>xypron.glpk@gmx.de</email>
</author>
<published>2020-02-05T20:59:12Z</published>
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<id>urn:sha1:58fc2b54f5b9102d593f3b98c370b6cbaeb97ac2</id>
<content type='text'>
Currently the size of pci_addr_t and pci_size_t depends on
CONFIG_SYS_PCI_64BIT. For qemu_arm64_defconfig with 4 GiB RAM this leads
to an error

    pci_hose_phys_to_bus: invalid physical address

which is due to the truncation of the bus address in _dm_pci_phys_to_bus.

Defining CONFIG_SYS_PCI_64BIT is not a solution as this results in an error

   PCI: Failed autoconfig bar 10

So let's use unsigned long for pci_addr_t and pci_size_t if
CONFIG_SYS_PCI_64BIT is not defined.

Considering that 32bit U-Boot is used to launch some 64bit x86 systems we
cannot do without CONFIG_SYS_PCI_64BIT requiring u64 as type.

Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: pci: Update a few more interfaces for const udevice *</title>
<updated>2020-02-06T02:33:45Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-01-27T15:49:38Z</published>
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<id>urn:sha1:194fca91306f1a35da404a9c56d767be257c8b0f</id>
<content type='text'>
Tidy up a few places where const * should be used.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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