u-boot.git/include/pci_ids.h, branch v2017.09 Unnamed repository; edit this file 'description' to name the repository. nvme: Detect devices that are class Storage Express 2017-08-13T19:17:32+00:00 Jon Nettleton jon@solid-run.com 2017-08-03T09:31:00+00:00 0deb91318b15f0d12839b23433e2720722504d25 This adds support to detect the catchall PCI class for NVMe devices. It allows the drivers to work with most NVMe devices that don't need specific detection due to quirks etc. Tested against a Samsung 960 EVO drive. Signed-off-by: Jon Nettleton <jon@solid-run.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> 
This adds support to detect the catchall PCI class for NVMe devices.
It allows the drivers to work with most NVMe devices that don't need
specific detection due to quirks etc.

Tested against a Samsung 960 EVO drive.

Signed-off-by: Jon Nettleton <jon@solid-run.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
x86: baytrail: Add 2nd eMMC controller to the PCI probe list 2016-10-11T03:55:33+00:00 Stefan Roese sr@denx.de 2016-09-26T08:18:07+00:00 5572367cc595d567361fc29298c099922ed65812 With this addition, the eMMC device available on the congatec and DFI BayTrail SoM is detected correctly. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
With this addition, the eMMC device available on the congatec and DFI
BayTrail SoM is detected correctly.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: pci: Add PCI IDs for Wildcat Point 2015-10-21T13:46:27+00:00 George McCollister george.mccollister@gmail.com 2015-10-12T21:18:40+00:00 b6fa966dc057be0575b086105b270fce08c61af1 Add Wildcat Point AHCI and LPC PCI IDs which are present on Broadwell U based (and possibly other) boards. Signed-off-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
Add Wildcat Point AHCI and LPC PCI IDs which are present on Broadwell U
based (and possibly other) boards.

Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: baytrail: Add all IDE/SATA PCI device IDs 2015-08-14T09:24:20+00:00 Bin Meng bmeng.cn@gmail.com 2015-08-06T09:36:01+00:00 44a8b96f6488bc0392f99e6caa424539813dee20 The BayTrail SoC has 4 different PCI devices IDs regarding to IDE and AHCI. Add these IDs in pci_ids.h and also add the other SATA ID in the Bayley Bay and MinnowMax board configuration header. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> 
The BayTrail SoC has 4 different PCI devices IDs regarding to IDE
and AHCI. Add these IDs in pci_ids.h and also add the other SATA
ID in the Bayley Bay and MinnowMax board configuration header.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
x86: qemu: Add ATA/SATA support 2015-06-04T08:39:39+00:00 Bin Meng bmeng.cn@gmail.com 2015-05-16T01:33:19+00:00 2aa3a7fb1c24afd4c0e12360acccf3234d8fe019 Enable legacy IDE support on the pc target and AHCI support on the q35 target. Default configuration is to support the pc target. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> 
Enable legacy IDE support on the pc target and AHCI support on the
q35 target. Default configuration is to support the pc target.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
x86: pci: Add PCI IDs for lynxpoint 2015-04-17T01:27:40+00:00 Simon Glass sjg@chromium.org 2015-03-02T19:40:51+00:00 713704f5e425c44b945eeacecc21086644213dce Add some new device IDs used by this haswell-based chipset. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
Add some new device IDs used by this haswell-based chipset.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: pci: Add pci ids for Quark SoC 2015-02-06T19:07:45+00:00 Bin Meng bmeng.cn@gmail.com 2015-02-04T08:26:11+00:00 38fc1cdae0fb7a429222b7b85f8cdaefbd078e21 Add pci ids for Intel Quark SoC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> 
Add pci ids for Intel Quark SoC.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
x86: pci: Add PCI IDs for Minnowboard Max 2015-02-06T05:16:42+00:00 Simon Glass sjg@chromium.org 2015-01-28T05:13:28+00:00 34236238359253ef5342843a3cca09dcca939262 This board includes a few IDs we have not seen before. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
This board includes a few IDs we have not seen before.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: Add Intel Topcliff PCH device IDs 2014-12-14T05:32:05+00:00 Bin Meng bmeng.cn@gmail.com 2014-12-12T13:05:26+00:00 936248d92f3afb6ec2447f3eccbf9b425dc14b66 Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> 
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
pci: Update pci_ids.h to include some missing IDs 2014-11-25T13:33:59+00:00 Simon Glass sjg@chromium.org 2014-11-15T01:18:21+00:00 e3bf4c759be1bf037818100e15af425d16822c29 This was taken from Linux 3.18 with some additional IDs from Chrome OS Coreboot commit 688ef385. Signed-off-by: Simon Glass <sjg@chromium.org> 
This was taken from Linux 3.18 with some additional IDs from Chrome OS
Coreboot commit 688ef385.

Signed-off-by: Simon Glass <sjg@chromium.org>