u-boot.git/include/phy.h, branch v2014.01-rc1 Unnamed repository; edit this file 'description' to name the repository. net: add extended function to phy API 2013-11-22T22:50:52+00:00 Stefano Babic sbabic@denx.de 2013-09-02T13:42:30+00:00 b71841b978fc33f961383b255693a70a1dd64031 Some phys (Micrel) has extended registers that must be accessed in a special way. Add pointers to the phy driver structure to allow to use these functions with mdio command. Signed-off-by: Stefano Babic <sbabic@denx.de> 
Some phys (Micrel) has extended registers that must be
accessed in a special way. Add pointers to the phy driver
structure to allow to use these functions with mdio command.

Signed-off-by: Stefano Babic <sbabic@denx.de>
Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24T13:44:38+00:00 Wolfgang Denk wd@denx.de 2013-07-08T07:37:19+00:00 1a4596601fd395f3afb8f82f3f840c5e00bdd57a Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> 
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
phy: export genphy_parse_link() 2013-06-25T00:07:32+00:00 Yegor Yefremov yegorslists@googlemail.com 2012-11-28T10:15:17+00:00 e2043f5c272d14a0e0acd81382f17cfc883136d6 Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> 
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Merge branch 'u-boot/master' into 'u-boot-arm/master' 2013-05-30T12:45:06+00:00 Albert ARIBAUD albert.u.boot@aribaud.net 2013-05-30T12:45:06+00:00 a19b0dd62d7b8efc658fa1aa685ff5665878f3ee Conflicts: common/cmd_fpga.c drivers/usb/host/ohci-at91.c 
Conflicts:
	common/cmd_fpga.c
	drivers/usb/host/ohci-at91.c
net/phy: add VSC8574 support 2013-05-14T21:13:25+00:00 Shaohui Xie Shaohui.Xie@freescale.com 2013-03-25T07:39:31+00:00 7794b1a7e6bb7fd678f00b17feb15e5d392fb5b0 The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes interfaces for quad-port dual media capability. This driver supports SGMII and QSGMII MAC mode. For now SGMII mode is tested. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> 
The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes
interfaces for quad-port dual media capability. This driver supports SGMII
and QSGMII MAC mode. For now SGMII mode is tested.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
phy: add support for ET1011C phys 2013-05-10T12:25:54+00:00 Matt Porter mporter@ti.com 2013-03-20T05:38:13+00:00 f485c8a35b38356a473208bec5ed786792c1eafe Adds an ET1011C PHY driver which is derived from the Linux kernel PHY driver (drivers/net/phy/et1011c.c) from the v3.9-rc2 tag. Note that an errata workaround config option is implemented to allow for TX_CLK to be enabled even when gigabit mode is negotiated. This workaround is used on the PG1.0 TI814X EVM. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com> 
Adds an ET1011C PHY driver which is derived from the
Linux kernel PHY driver (drivers/net/phy/et1011c.c)
from the v3.9-rc2 tag. Note that an errata workaround
config option is implemented to allow for TX_CLK to be
enabled even when gigabit mode is negotiated. This
workaround is used on the PG1.0 TI814X EVM.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
phy: add phy_find_by_mask/phy_connect_dev 2013-01-28T05:57:50+00:00 Troy Kisky troy.kisky@boundarydevices.com 2012-10-22T16:40:43+00:00 1adb406b014176f0c1a925e4d3e9aae556dfe571 It is useful to be able to try a range of possible phy addresses to connect. Also, an ethernet device is not required to use phy_find_by_mask leading to better separation of mii vs ethernet, as suggested by Andy Fleming. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> 
It is useful to be able to try a range of
possible phy addresses to connect.

Also, an ethernet device is not required
to use phy_find_by_mask leading to better
separation of mii vs ethernet, as suggested
by Andy Fleming.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
net: phy: add support for Micrel's KSZ9021 2012-02-27T20:19:25+00:00 Troy Kisky troy.kisky@boundarydevices.com 2012-02-07T14:08:48+00:00 8682aba7da2af2842296710acca7c03fcebafd5c Add the gigabit phy KSZ9021. Also, add function ksz9021_phy_extended_write /_read for access to the phys extended registers. The environment variable "disable_giga" can be used to disable 1000baseTx. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> 
Add the gigabit phy KSZ9021.
Also, add function ksz9021_phy_extended_write
/_read for access to the phys extended registers.
The environment variable "disable_giga"
can be used to disable 1000baseTx.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
phy: add phy_smsc_init() declaration 2012-01-05T15:12:26+00:00 Vladimir Zapolskiy vz@mleia.com 2011-12-29T15:18:37+00:00 b6abf55578d36d0304d8af9a13a58ca13b9066b7 This trivial change removes a compilation warning: ----8<---- phy.c: In function 'phy_init': phy.c:448:2: warning: implicit declaration of function 'phy_smsc_init' ----8<---- Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> 
This trivial change removes a compilation warning:
  ----8<----
  phy.c: In function 'phy_init':
  phy.c:448:2: warning: implicit declaration of function 'phy_smsc_init'
  ----8<----

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9) 2011-10-20T21:01:37+00:00 Timur Tabi timur@freescale.com 2011-10-18T23:44:34+00:00 a836626cc4ddae53bfa46195a39194f21ad157af The work-around for P4080 erratum SERDES9 says that the SERDES receiver lanes should be reset after the XAUI starts tranmitting alignment signals. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
The work-around for P4080 erratum SERDES9 says that the SERDES receiver
lanes should be reset after the XAUI starts tranmitting alignment signals.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>