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<title>u-boot.git/include/ppc440.h, branch v1.3.3</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>lwmon5: watchdog POST fix</title>
<updated>2008-04-25T09:35:32+00:00</updated>
<author>
<name>Yuri Tikhonov</name>
<email>yur@emcraft.com</email>
</author>
<published>2008-04-24T08:30:53+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=eb0615bf600d2caf5aa2958f47f5ba364c52d5e7'/>
<id>eb0615bf600d2caf5aa2958f47f5ba364c52d5e7</id>
<content type='text'>
Use the GPT0_MASKx registers as the temporary storage for watch-dog
timer POST test instead of GPT0_COMPx. The latter
(GPT0_COMP1..GPT0_COMP5) are used for the log-buffer header.

Signed-off-by: Sergei Poselenov &lt;sposelenov@emcraft.com&gt;
Signed-off-by: Yuri Tikhonov &lt;yur@emcraft.com&gt;
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<pre>
Use the GPT0_MASKx registers as the temporary storage for watch-dog
timer POST test instead of GPT0_COMPx. The latter
(GPT0_COMP1..GPT0_COMP5) are used for the log-buffer header.

Signed-off-by: Sergei Poselenov &lt;sposelenov@emcraft.com&gt;
Signed-off-by: Yuri Tikhonov &lt;yur@emcraft.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>ppc4xx: Fix power mgt definitions for PPC440</title>
<updated>2008-04-11T14:27:58+00:00</updated>
<author>
<name>Eugene O'Brien</name>
<email>eugene.obrien@advantechamt.com</email>
</author>
<published>2008-04-11T14:00:35+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5b2052e5f5fcce5dbd4d2750a29c0e45bce806e7'/>
<id>5b2052e5f5fcce5dbd4d2750a29c0e45bce806e7</id>
<content type='text'>
Corrected DCR addresses of PPC440EP power management registers.

Signed-off-by: Eugene O'Brien &lt;eugene.obrien@advantechamt.com&gt;
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<pre>
Corrected DCR addresses of PPC440EP power management registers.

Signed-off-by: Eugene O'Brien &lt;eugene.obrien@advantechamt.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ppc4xx: Add AMCC Glacier 406GT eval board support</title>
<updated>2008-03-27T08:54:41+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2008-03-19T15:20:49+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4c9e855734c523900322a7c3cdd9099b4f51b51d'/>
<id>4c9e855734c523900322a7c3cdd9099b4f51b51d</id>
<content type='text'>
This patch adds support for the AMCC Glacier 460GT eval board.
The main difference to the Canyonlands board are listed here:

- 4 ethernet ports instead of 2
- no SATA port
- no USB port

Currently EMAC2+3 are not working. This will be fixed in a later
release.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
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<pre>
This patch adds support for the AMCC Glacier 460GT eval board.
The main difference to the Canyonlands board are listed here:

- 4 ethernet ports instead of 2
- no SATA port
- no USB port

Currently EMAC2+3 are not working. This will be fixed in a later
release.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>The patch introduces the alternative configuration of the log buffer for the lwmon5 board: the storage for the log-buffer itself is OCM(on-chip memory), the log-buffer header is moved to six GPT registers (PPC440EPX_GPT0_COMP1, ..., PPC440EPX_GPT0_COMP5).</title>
<updated>2008-03-18T21:24:48+00:00</updated>
<author>
<name>Yuri Tikhonov</name>
<email>yur@pollux.denx.de</email>
</author>
<published>2008-02-06T17:48:36+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3d61018643a2cd38c145aa6dde53f3f5f1a0e9cf'/>
<id>3d61018643a2cd38c145aa6dde53f3f5f1a0e9cf</id>
<content type='text'>
 To enable this, alternative, configuration the U-Boot board configuration
file for lwmon5 includes the definitions of alternative addresses for header
(CONFIG_ALT_LH_ADDR) and buffer (CONFIG_ALT_LB_ADDR).

 The Linux shall be configured with the CONFIG_ALT_LB_LOCATION option set,
and has the BOARD_ALT_LH_ADDR and BOARD_ALT_LB_ADDR constants defined in the
lwmon5 board-specific header (arch/ppc/platforms/4xx/lwmon5.h).

Signed-off-by: Yuri Tikhonov &lt;yur@emcraft.com&gt;
</content>
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<pre>
 To enable this, alternative, configuration the U-Boot board configuration
file for lwmon5 includes the definitions of alternative addresses for header
(CONFIG_ALT_LH_ADDR) and buffer (CONFIG_ALT_LB_ADDR).

 The Linux shall be configured with the CONFIG_ALT_LB_LOCATION option set,
and has the BOARD_ALT_LH_ADDR and BOARD_ALT_LB_ADDR constants defined in the
lwmon5 board-specific header (arch/ppc/platforms/4xx/lwmon5.h).

Signed-off-by: Yuri Tikhonov &lt;yur@emcraft.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>The patch adds new POST tests for the Lwmon5 board. These are:</title>
<updated>2008-03-18T21:24:47+00:00</updated>
<author>
<name>Yuri Tikhonov</name>
<email>yur@pollux.denx.de</email>
</author>
<published>2008-02-04T13:10:42+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8f15d4addd49c956412e1e3bfc764a0c8b1f3184'/>
<id>8f15d4addd49c956412e1e3bfc764a0c8b1f3184</id>
<content type='text'>
* External Watchdog test;
* dsPIC tests;
* FPGA test;
* GDC test;
* Sysmon tests.

Signed-off-by: Dmitry Rakhchev &lt;rda@emcraft.com&gt;
Signed-off-by: Yuri Tikhonov &lt;yur@emcraft.com&gt;
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<pre>
* External Watchdog test;
* dsPIC tests;
* FPGA test;
* GDC test;
* Sysmon tests.

Signed-off-by: Dmitry Rakhchev &lt;rda@emcraft.com&gt;
Signed-off-by: Yuri Tikhonov &lt;yur@emcraft.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ppc4xx: Add USB OHCI support to AMCC Canyonlands 460EX eval board</title>
<updated>2008-03-15T06:28:05+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2008-03-05T11:31:53+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=41712b4e8c95dff23354bcd620e1f9477160c190'/>
<id>41712b4e8c95dff23354bcd620e1f9477160c190</id>
<content type='text'>
This patch adds USB OHCI support to the Canyonlands board port. It also
enables EXT2 support.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
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<pre>
This patch adds USB OHCI support to the Canyonlands board port. It also
enables EXT2 support.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ppc4xx: Add basic support for AMCC 460EX/460GT (5/5)</title>
<updated>2008-03-15T06:28:04+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2008-03-11T14:11:43+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=43c60992cdf72496e7eaaa3fbd37ebbe75835f69'/>
<id>43c60992cdf72496e7eaaa3fbd37ebbe75835f69</id>
<content type='text'>
This patch adds basic support for the AMCC 460EX/460GT PPC's.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
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<pre>
This patch adds basic support for the AMCC 460EX/460GT PPC's.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'lwmon5-no-ocm'</title>
<updated>2008-01-09T09:43:47+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2008-01-09T09:43:47+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1466ef8db57a2b52efd8c900dd37e7b3840dc263'/>
<id>1466ef8db57a2b52efd8c900dd37e7b3840dc263</id>
<content type='text'>
</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>ppc4xx: Change LWMON5 to not use OCM for init-ram and POST anymore</title>
<updated>2008-01-09T09:28:20+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2008-01-09T09:28:20+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8f24e0637ae113500d8bd60d80d57afcc0aa8bde'/>
<id>8f24e0637ae113500d8bd60d80d57afcc0aa8bde</id>
<content type='text'>
This patch configures the LWMON5 port to use d-cache as init-ram and
the unused GPT0_COMP6 as POST WORD storage.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
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<pre>
This patch configures the LWMON5 port to use d-cache as init-ram and
the unused GPT0_COMP6 as POST WORD storage.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ppc4xx: Update Katmai/44x_spd_ddr2.c code for optimal DDR2 setup</title>
<updated>2008-01-05T08:12:41+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2008-01-05T08:12:41+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=845c6c95dbfe6c915ce68a0a115852fa17932fb4'/>
<id>845c6c95dbfe6c915ce68a0a115852fa17932fb4</id>
<content type='text'>
On Katmai the complete auto-calibration somehow doesn't seem to
produce the best results, meaning optimal values for RQFD/RFFD.
This was discovered by GDA using a high bandwidth scope,
analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
so now on Katmai "only" RFFD is auto-calibrated.

This patch also adds RDCC calibration as mentioned on page 7 of
the AMCC PowerPC440SP/SPe DDR2 application note:
"DDR1/DDR2 Initialization Sequence and Dynamic Tuning"

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
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<pre>
On Katmai the complete auto-calibration somehow doesn't seem to
produce the best results, meaning optimal values for RQFD/RFFD.
This was discovered by GDA using a high bandwidth scope,
analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
so now on Katmai "only" RFFD is auto-calibrated.

This patch also adds RDCC calibration as mentioned on page 7 of
the AMCC PowerPC440SP/SPe DDR2 application note:
"DDR1/DDR2 Initialization Sequence and Dynamic Tuning"

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
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