u-boot.git/include/ppc440.h, branch v2008.10 Unnamed repository; edit this file 'description' to name the repository. ppc4xx: Update Kilauea to use PPC4xx DDR autocalibration routines 2008-09-05T10:04:16+00:00 Adam Graham agraham@amcc.com 2008-09-03T19:26:59+00:00 f6b6c45840f9b4671d2d97243a12a1f3ffb64765 Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de> 
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe, 2008-08-21T08:31:16+00:00 Prodyut Hazarika phazarika@amcc.com 2008-08-20T16:38:51+00:00 079589bcfb24ba11068460276a3cc9549ab5346f PPC405EX and PPC460EX/GT/SX - Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX processors - Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared across processors (405 and 440/460) - Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX processors - Add register bit definitions for Memory Queue Configuration registers Signed-off-by: Prodyut Hazarika <phazarika@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de> 
	PPC405EX and PPC460EX/GT/SX

- Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX
  processors
- Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared
  across processors (405 and 440/460)
- Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX
  processors
- Add register bit definitions for Memory Queue Configuration registers

Signed-off-by: Prodyut Hazarika <phazarika@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
ppc4xx: Continue cleanup of ppc440.h 2008-07-11T11:18:14+00:00 Stefan Roese sr@denx.de 2008-06-30T12:11:07+00:00 26173fc6f60521c2a8072f652f863617fc11ba9a This patch continues the ppc440.h cleanup by removing some of the unused defines. Signed-off-by: Stefan Roese <sr@denx.de> 
This patch continues the ppc440.h cleanup by removing some of the unused
defines.

Signed-off-by: Stefan Roese <sr@denx.de>
ppc4xx: Consolidate PPC4xx UIC defines 2008-07-11T11:18:14+00:00 Stefan Roese sr@denx.de 2008-06-26T11:40:57+00:00 d1631fe1a05b063ccaf62ea892a8887b829847d1 This 2nd patch now removes all UIC mask bit definition. They should be generated from the vectors by using the UIC_MASK() macro from now on. This way only the vectors need to get defined for new PPC's. Also only the really used interrupt vectors are now defined. This makes definitions for new PPC versions easier and less error prone. Another part of this patch is that the 4xx emac driver got a little cleanup, since now the usage of the interrupts is clearer. Signed-off-by: Stefan Roese <sr@denx.de> 
This 2nd patch now removes all UIC mask bit definition. They should be
generated from the vectors by using the UIC_MASK() macro from now on.
This way only the vectors need to get defined for new PPC's.

Also only the really used interrupt vectors are now defined. This makes
definitions for new PPC versions easier and less error prone.

Another part of this patch is that the 4xx emac driver got a little
cleanup, since now the usage of the interrupts is clearer.

Signed-off-by: Stefan Roese <sr@denx.de>
ppc4xx: Consolidate PPC4xx EBC defines 2008-07-11T11:18:13+00:00 Stefan Roese sr@denx.de 2008-06-24T15:18:50+00:00 7ee2619c20ccecd57966d74d844e6329e141261c This patch removes all EBC related defines from the PPC4xx headers ppc405.h and ppc440.h and introduces a new header include/asm-ppc/ppc4xx-ebc.h with all those defines. Signed-off-by: Stefan Roese <sr@denx.de> 
This patch removes all EBC related defines from the PPC4xx headers
ppc405.h and ppc440.h and introduces a new header

include/asm-ppc/ppc4xx-ebc.h

with all those defines.

Signed-off-by: Stefan Roese <sr@denx.de>
ppc4xx: Add initial 460SX reference board (redwood) config file and defines. 2008-07-11T11:18:12+00:00 Feng Kan fkan@amcc.com 2008-07-09T05:48:07+00:00 96e5fc0e6a1861d0fea4efa3cd376df95a5b1b89 Signed-off-by: Feng Kan <fkan@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de> 
Signed-off-by: Feng Kan <fkan@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
ppc4xx: Fix 460EX errata with CPU lockup upon high AHB traffic 2008-06-30T13:20:41+00:00 Stefan Roese sr@denx.de 2008-06-28T12:56:17+00:00 745d8a0d3cea82e6d1753e14afb4588c34761b15 This patch implements a fix provided by AMCC so that the lockup upon simultanious traffic on AHB USB OTG, USB 2.0 and SATA doesn't occur anymore: Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA. This errata is not officially available yet. I'll update the comment to add the errata number later. Signed-off-by: Stefan Roese <sr@denx.de> 
This patch implements a fix provided by AMCC so that the lockup upon
simultanious traffic on AHB USB OTG, USB 2.0 and SATA doesn't occur
anymore:

Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and clear SDR0_AHB_CFG[A2P_PROT2]
(bit 25) for a new 460EX errata regarding concurrent use of AHB USB OTG,
USB 2.0 host and SATA.

This errata is not officially available yet. I'll update the comment
to add the errata number later.

Signed-off-by: Stefan Roese <sr@denx.de>
ppc4xx: Consolidate PPC4xx SDRAM/DDR/DDR2 defines, part1 2008-06-03T18:21:53+00:00 Stefan Roese sr@denx.de 2008-06-02T12:57:41+00:00 36ea16f6a066ccb046e91ebce4f326b69f4c0569 This patch removes all SDRAM related defines from the PPC4xx headers ppc405.h and ppc440.h. This is needed since now some 405 PPC's use the same SDRAM controller as 440 systems do (like 405EX and 440SP). It also introduces new defines for the equipped SDRAM controller based on which PPC variant is used. There new defines are: used on 405GR/CR/EP and some Xilinx Virtex boards. used on 440GP/GX/EP/GR. used on 440EPx/GRx. used on 405EX/r/440SP/SPe/460EX/GT. Signed-off-by: Stefan Roese <sr@denx.de> 
This patch removes all SDRAM related defines from the PPC4xx headers
ppc405.h and ppc440.h. This is needed since now some 405 PPC's use
the same SDRAM controller as 440 systems do (like 405EX and 440SP).

It also introduces new defines for the equipped SDRAM controller based on
which PPC variant is used. There new defines are:

used on 405GR/CR/EP and some Xilinx Virtex boards.

used on 440GP/GX/EP/GR.

used on 440EPx/GRx.

used on 405EX/r/440SP/SPe/460EX/GT.

Signed-off-by: Stefan Roese <sr@denx.de>
Big white-space cleanup. 2008-05-20T22:14:08+00:00 Wolfgang Denk wd@denx.de 2008-05-20T14:00:29+00:00 53677ef18e25c97ac613349087c5cb33ae5a2741 This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de> 
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).

Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.

Signed-off-by: Wolfgang Denk <wd@denx.de>
lwmon5: watchdog POST fix 2008-04-25T09:35:32+00:00 Yuri Tikhonov yur@emcraft.com 2008-04-24T08:30:53+00:00 eb0615bf600d2caf5aa2958f47f5ba364c52d5e7 Use the GPT0_MASKx registers as the temporary storage for watch-dog timer POST test instead of GPT0_COMPx. The latter (GPT0_COMP1..GPT0_COMP5) are used for the log-buffer header. Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> Signed-off-by: Yuri Tikhonov <yur@emcraft.com> 
Use the GPT0_MASKx registers as the temporary storage for watch-dog
timer POST test instead of GPT0_COMPx. The latter
(GPT0_COMP1..GPT0_COMP5) are used for the log-buffer header.

Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>