u-boot.git/include/sdhci.h, branch master

mmc: sdhci: Add SDHCI_SPEC_400, _410, and _420 version defines

2025-12-11T12:53:51+00:00

Add SDHCI_SPEC_400, SDHCI_SPEC_410, and SDHCI_SPEC_420 macros to sdhci.h
to support newer SDHCI specification versions. These defines are required
for compatibility with controllers implementing SDHCI 4.0 and above.

Reference:
https://lore.kernel.org/all/1535617305-16952-2-git-send-email-zhang.chunyan@linaro.org/

Signed-off-by: Tanmay Kathpalia 
Reviewed-by: Balsundar Ponnusamy 
Reviewed-by: Peng Fan 
Signed-off-by: Peng Fan

sdhci: Reorder interrupt flags in SDHCI_INT_DATA_MASK definition

2025-10-30T02:11:18+00:00

Reorder the SDHCI_INT_SPACE_AVAIL and SDHCI_INT_DATA_AVAIL flags in the
SDHCI_INT_DATA_MASK definition to match the bit order as defined in the
SDHCI specification and maintain consistency with the register layout.

The functional behavior remains unchanged as this only affects the
order of OR operations in the mask definition.

Signed-off-by: Tanmay Kathpalia 
Reviewed-by: Peng Fan 
Signed-off-by: Peng Fan

mmc: am654_sdhci: Add am654_sdhci_set_control_reg

2025-04-24T16:44:52+00:00

This patch adds am654_sdhci_set_control_reg to am654_sdhci.

This is required to fix UHS_MODE_SELECT for TI K3 boards.

If any of HIGH_SPEED_ENA, V1P8_SIGNAL_ENA, UHS_MODE_SELECT
are set, then data will be launched on the pos-edge of the
clock.

Since K3 SoCs did not meet timing requirements for High Speed
SDR mode at rising clock edge, none of these three should be
set, therefore limit UHS_MODE_SELECT to only be set for modes
above MMC_HS_52.

This fixes MMC write issue on am64x evm at mode High Speed
SDR.

Signed-off-by: Judith Mendez 
Reviewed-by: Bryan Brattlof

mmc: sdhci: Correct ADMA_DESC_LEN to 12

2024-05-02T16:34:34+00:00

Commit 37cb626da25d0d ("mmc: sdhci: Add Support for ADMA2") introduced
ADMA_DESC_LEN == 16 (64 bit case), but it was never used before commit
74755c1fed1b0 ("mmc: sdhci: introduce adma_write_desc() hook to struct sdhci_ops").

"sizeof(struct sdhci_adma_desc)" (== 12 for 64bit case) was used instead.

Confusion probably originates from Linux commit 685e444bbaa0
("mmc: sdhci: Add ADMA2 64-bit addressing support for V4 mode"), but
the latter "V4 mode" was never ported to U-Boot.

Fixes: 74755c1fed1b0 ("mmc: sdhci: introduce adma_write_desc() hook to struct sdhci_ops")
Signed-off-by: Alexander Sverdlin 
Tested-by: Jonathan Humphreys 
Tested-by: Judith Mendez

mmc: Support 32-bit only ADMA on 64-bit platforms

2024-04-26T06:31:11+00:00

Some arm64 platforms may include SDIO host controllers that
only support 32-bit ADMA. While the Linux kernel detects which
size is supported and adjusts the descriptor size used dynamically,
the previous u-boot implementation statically selected between the
two depending on whether DMA_ADDR_T_64BIT was defined. Because the
static selection is already in place and effective for most platforms,
this patch logically separates "64 bit addresses are used for DMA on
this platform" and "64 bit addresses are used by the SDIO host
controller for ADMA" in order to support the small number of platforms
where these statements are not equivalent.

Using 32 bits is opt-in and existing 64 bit platforms should be
unaffected by this change.

Co-developed-by: Nathan Barrett-Morrison 
Signed-off-by: Nathan Barrett-Morrison 
Co-developed-by: Ian Roberts 
Signed-off-by: Ian Roberts 
Signed-off-by: Greg Malysa 
Reviewed-by: Jaehoon Chung

mmc: sdhci: Fix potential ADMA descriptor table overflow

2024-04-26T06:31:00+00:00

Change ADMA_TABLE_NO_ENTRIES to round the division up to fully
contain CONFIG_SYS_MMC_MAX_BLK_COUNT, fixing potential buffer overflow
of the ADMA descriptor table.

sdhci_prepare_adma_table() expecitily states it does _not_ check for
overflow as the descriptor table size is dependent on
CONFIG_SYS_MMC_MAX_BLK_COUNT. However, the ADMA_TABLE_NO_ENTRIES
calculation does not round up the divison, so with the current u-boot
 defaults:
max_mmc_transfer = (CONFIG_SYS_MMC_MAX_BLK_COUNT * MMC_MAX_BLOCK_LEN) =
65535 * 512 = 33553920 bytes.
ADMA_TABLE_NO_ENTRIES = max_mmc_transfer / ADMA_MAX_LEN =
33553920 / 65532, which does not divide cleanly.
actual_max_transfer = ADMA_TABLE_NO_ENTRIES * ADMA_MAX_LEN = 512 *
65532 = 33552384, which is smaller than max_mmc_transfer.
This can cause sdhci_prepare_adma_table() to write one extra
descriptor, overflowing the table when a transaction larger than
actual_max_transfer is issued.

Co-developed-by: Nathan Barrett-Morrison 
Signed-off-by: Nathan Barrett-Morrison 
Signed-off-by: Greg Malysa 
Signed-off-by: Ian Roberts 
Reviewed-by: Jaehoon Chung

mmc: sdhci: introduce adma_write_desc() hook to struct sdhci_ops

2024-04-26T06:30:48+00:00

Add this hook so that it can be overridden with driver specific
implementations. We also let the original sdhci_adma_write_desc()
accept &desc so that the function can set its new value. Then export
the function so that it could be reused by driver's specific
implementations.

The above is a port of Linux kernel commit 54552e4948cbf

In addition, allow drivers to allocate their own ADMA descriptor
tables if additional space is required.

Finally, fix the assignment of adma_addr to fix compiler warning
on 64-bit platforms that still use 32-bit DMA addressing.

Co-developed-by: Nathan Barrett-Morrison 
Signed-off-by: Nathan Barrett-Morrison 
Co-developed-by: Greg Malysa 
Signed-off-by: Greg Malysa 
Signed-off-by: Ian Roberts

mmc: sdhci: Rework SDHCI_QUIRK_BROKEN_R1B

2023-11-01T01:01:10+00:00

As noted in commit 3a6383207be ("mmc: sdhci: add the quirk for broken
r1b response"), some MMC controllers don't always set the transfer
complete bit with R1b responses.

According to the SD Host Controller Simplified Specification v4.20,

> In the case of a command pairing with response-with-busy[, Transfer
> Complete] is set when busy is de-asserted. Refer to DAT Line Active
> and Command Inhibit (DAT) in the Present State register.

By polling the DAT Line Active bit in the present state register, we can
detect when we are no longer busy, without waiting for a long timeout.
This results in much faster reads/writes on buggy controllers.

Signed-off-by: Sean Anderson 
Tested-by: Henrik Grimler

mmc: sdhci: Enable HS400 support if available in caps

2023-01-31T13:02:27+00:00

HS400 is indicated in bit63 of capability register in few IP's.
Add a quirk to check this and add HS400 to host capabilities.

Signed-off-by: Ashok Reddy Soma

mmc: sdhci: Check and call config_dll callback functions

2023-01-31T13:02:27+00:00

Check if the low level driver supports config_dll callback function and
call it if it does. Call with dll disable before calling set_clock and
with dll enable after it.

Signed-off-by: Ashok Reddy Soma