<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/include/spi.h, branch v2026.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>spi: Introduce setup_for_spinand()</title>
<updated>2025-04-17T01:57:19+00:00</updated>
<author>
<name>Christian Marangi</name>
<email>ansuelsmth@gmail.com</email>
</author>
<published>2025-04-07T20:01:54+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ef45b9c395f92d9239d6c363b1f5a89f6a53f2e6'/>
<id>ef45b9c395f92d9239d6c363b1f5a89f6a53f2e6</id>
<content type='text'>
A common device attached to SPI are SPI NAND and some device might
require to have info on the attached NAND to know the flash page size
and spare size.

To support this, introduce setup_for_spinand() that pass the attached
spinand info from manufacturer.

Signed-off-by: Christian Marangi &lt;ansuelsmth@gmail.com&gt;
[trini: Switch to forward declaration of struct spinand_info]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
A common device attached to SPI are SPI NAND and some device might
require to have info on the attached NAND to know the flash page size
and spare size.

To support this, introduce setup_for_spinand() that pass the attached
spinand info from manufacturer.

Signed-off-by: Christian Marangi &lt;ansuelsmth@gmail.com&gt;
[trini: Switch to forward declaration of struct spinand_info]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mtd: spi-nor: Fix integer overflow in stacked memories support</title>
<updated>2024-11-11T02:21:07+00:00</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2024-11-02T23:57:31+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=24b28ffc40d464696b909ca5a4e860e09343397b'/>
<id>24b28ffc40d464696b909ca5a4e860e09343397b</id>
<content type='text'>
The 5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
adds new SPI bus flags, but also introduces a completely new set of
SPI bus flags in another location. The existing flags field is type
u8, while the new separate flags are BIT(8) and higher. Use of those
new flags triggers integer overflow.

Drop the newly introduced flags which were never used anywhere in the
code. Move the one remaining flag which was used in the correct place
and change it from BIT(8) to BIT(6) so it fits the u8 flags.

Fixes: 5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
Addresses-Coverity-ID: 510804 Extra high-order bits
Reported-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
Reviewed-by: Venkatesh Yadav Abbarapu &lt;venkatesh.abbarapu@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The 5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
adds new SPI bus flags, but also introduces a completely new set of
SPI bus flags in another location. The existing flags field is type
u8, while the new separate flags are BIT(8) and higher. Use of those
new flags triggers integer overflow.

Drop the newly introduced flags which were never used anywhere in the
code. Move the one remaining flag which was used in the correct place
and change it from BIT(8) to BIT(6) so it fits the u8 flags.

Fixes: 5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
Addresses-Coverity-ID: 510804 Extra high-order bits
Reported-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
Reviewed-by: Venkatesh Yadav Abbarapu &lt;venkatesh.abbarapu@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: zynqmp_gqspi: Add parallel memories support in GQSPI driver</title>
<updated>2024-10-09T15:01:54+00:00</updated>
<author>
<name>Venkatesh Yadav Abbarapu</name>
<email>venkatesh.abbarapu@amd.com</email>
</author>
<published>2024-09-26T04:55:06+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=217b0a28b6db3d664300f82df8e4cf342de3b8a0'/>
<id>217b0a28b6db3d664300f82df8e4cf342de3b8a0</id>
<content type='text'>
Add support for parallel memories in zynqmp_gqspi.c driver. In case of
parallel memories STRIPE bit is set and sent to the qspi ip, which will
send data bits to both the flashes in parallel. However for few commands
we should not use stripe, instead send same data to both the flashes.
Those commands are exclueded by using zynqmp_qspi_update_stripe().

Also update copyright info for this file.

Signed-off-by: Ashok Reddy Soma &lt;ashok.reddy.soma@amd.com&gt;
Signed-off-by: Venkatesh Yadav Abbarapu &lt;venkatesh.abbarapu@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add support for parallel memories in zynqmp_gqspi.c driver. In case of
parallel memories STRIPE bit is set and sent to the qspi ip, which will
send data bits to both the flashes in parallel. However for few commands
we should not use stripe, instead send same data to both the flashes.
Those commands are exclueded by using zynqmp_qspi_update_stripe().

Also update copyright info for this file.

Signed-off-by: Ashok Reddy Soma &lt;ashok.reddy.soma@amd.com&gt;
Signed-off-by: Venkatesh Yadav Abbarapu &lt;venkatesh.abbarapu@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: spi-uclass: Read chipselect and restrict capabilities</title>
<updated>2024-10-09T15:01:54+00:00</updated>
<author>
<name>Venkatesh Yadav Abbarapu</name>
<email>venkatesh.abbarapu@amd.com</email>
</author>
<published>2024-09-26T04:55:05+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=34da258bb0465de4bf44dc8949a9536cc06bf725'/>
<id>34da258bb0465de4bf44dc8949a9536cc06bf725</id>
<content type='text'>
Read chipselect properties from DT which are populated using 'reg'
property and save it in plat-&gt;cs[] array for later use.

Also read multi chipselect capability which is used for
parallel-memories and return errors if they are passed on using DT but
driver is not capable of handling it.

Signed-off-by: Ashok Reddy Soma &lt;ashok.reddy.soma@amd.com&gt;
Signed-off-by: Venkatesh Yadav Abbarapu &lt;venkatesh.abbarapu@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Read chipselect properties from DT which are populated using 'reg'
property and save it in plat-&gt;cs[] array for later use.

Also read multi chipselect capability which is used for
parallel-memories and return errors if they are passed on using DT but
driver is not capable of handling it.

Signed-off-by: Ashok Reddy Soma &lt;ashok.reddy.soma@amd.com&gt;
Signed-off-by: Venkatesh Yadav Abbarapu &lt;venkatesh.abbarapu@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mtd: spi-nor: Add parallel and stacked memories support</title>
<updated>2024-10-09T15:01:54+00:00</updated>
<author>
<name>Venkatesh Yadav Abbarapu</name>
<email>venkatesh.abbarapu@amd.com</email>
</author>
<published>2024-09-26T04:55:02+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5d40b3d384dc536ec26ce9b76b20b0b84749d2d1'/>
<id>5d40b3d384dc536ec26ce9b76b20b0b84749d2d1</id>
<content type='text'>
In parallel mode, the current implementation assumes that a maximum of
two flashes are connected. The QSPI controller splits the data evenly
between both the flashes so, both the flashes that are connected in
parallel mode should be identical.
During each operation SPI-NOR sets 0th bit for CS0 &amp; 1st bit for CS1 in
nor-&gt;flags.

In stacked mode the current implementation assumes that a maximum of two
flashes are connected and both the flashes are of same make but can
differ in sizes. So, except the sizes all other flash parameters of both
the flashes are identical

Spi-nor will pass on the appropriate flash select flag to low level
driver, and it will select pass all the data to that particular flash.

Write operation in parallel mode are performed in page size * 2 chunks as
each write operation results in writing both the flashes. For doubling
the address space each operation is performed at addr/2 flash offset,
where addr is the address specified by the user.

Similarly for read and erase operations it will read from both flashes,
so size and offset are divided by 2 and send to flash.

Adding the config option SPI_ADVANCE for non SPL code.

Signed-off-by: Ashok Reddy Soma &lt;ashok.reddy.soma@amd.com&gt;
Signed-off-by: Venkatesh Yadav Abbarapu &lt;venkatesh.abbarapu@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In parallel mode, the current implementation assumes that a maximum of
two flashes are connected. The QSPI controller splits the data evenly
between both the flashes so, both the flashes that are connected in
parallel mode should be identical.
During each operation SPI-NOR sets 0th bit for CS0 &amp; 1st bit for CS1 in
nor-&gt;flags.

In stacked mode the current implementation assumes that a maximum of two
flashes are connected and both the flashes are of same make but can
differ in sizes. So, except the sizes all other flash parameters of both
the flashes are identical

Spi-nor will pass on the appropriate flash select flag to low level
driver, and it will select pass all the data to that particular flash.

Write operation in parallel mode are performed in page size * 2 chunks as
each write operation results in writing both the flashes. For doubling
the address space each operation is performed at addr/2 flash offset,
where addr is the address specified by the user.

Similarly for read and erase operations it will read from both flashes,
so size and offset are divided by 2 and send to flash.

Adding the config option SPI_ADVANCE for non SPL code.

Signed-off-by: Ashok Reddy Soma &lt;ashok.reddy.soma@amd.com&gt;
Signed-off-by: Venkatesh Yadav Abbarapu &lt;venkatesh.abbarapu@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>env_spi: support overriding spi dev from board code</title>
<updated>2024-08-05T14:10:36+00:00</updated>
<author>
<name>Venkatesh Yadav Abbarapu</name>
<email>venkatesh.abbarapu@amd.com</email>
</author>
<published>2024-06-14T12:48:10+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7d84ad1da0e32f4525cee9b35bc5a4f3b5585ed8'/>
<id>7d84ad1da0e32f4525cee9b35bc5a4f3b5585ed8</id>
<content type='text'>
This enables boards to choose where to/from the environment
should be saved/loaded. They can then for example support using
the same device (dynamically) from which the bootloader was
launched to load and save env data and do not have to
define CONFIG_ENV_SPI_BUS statically.

In my use case, the environment needs to be on the same device I
booted from. It can be the QSPI or OSPI device.
I therefore would override spi_get_env_dev in the board code,
read the bootmode registers to determine where we booted from
and return the corresponding device index.

Signed-off-by: Venkatesh Yadav Abbarapu &lt;venkatesh.abbarapu@amd.com&gt;
Link: https://lore.kernel.org/r/20240614124811.22945-2-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt; # Move spi_get_env_dev to sf.c
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This enables boards to choose where to/from the environment
should be saved/loaded. They can then for example support using
the same device (dynamically) from which the bootloader was
launched to load and save env data and do not have to
define CONFIG_ENV_SPI_BUS statically.

In my use case, the environment needs to be on the same device I
booted from. It can be the QSPI or OSPI device.
I therefore would override spi_get_env_dev in the board code,
read the bootmode registers to determine where we booted from
and return the corresponding device index.

Signed-off-by: Venkatesh Yadav Abbarapu &lt;venkatesh.abbarapu@amd.com&gt;
Link: https://lore.kernel.org/r/20240614124811.22945-2-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt; # Move spi_get_env_dev to sf.c
</pre>
</div>
</content>
</entry>
<entry>
<title>include: Drop &lt;common.h&gt; from include lists</title>
<updated>2023-11-07T19:50:52+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-11-01T16:28:20+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7f38e9c9a49418fffa233c1a42959ff928415ec4'/>
<id>7f38e9c9a49418fffa233c1a42959ff928415ec4</id>
<content type='text'>
At this point, we don't need to have &lt;common.h&gt; be included because of
properties in the header itself, it only includes other common header
files. We've also audited the code enough at this point that we can drop
&lt;common.h&gt; from being included in headers and rely on code to have the
correct inclusions themselves, or at least &lt;common.h&gt;.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
At this point, we don't need to have &lt;common.h&gt; be included because of
properties in the header itself, it only includes other common header
files. We've also audited the code enough at this point that we can drop
&lt;common.h&gt; from being included in headers and rely on code to have the
correct inclusions themselves, or at least &lt;common.h&gt;.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: Implement spi_set_speed</title>
<updated>2022-10-16T10:23:22+00:00</updated>
<author>
<name>Paul Barker</name>
<email>paul.barker@sancloud.com</email>
</author>
<published>2022-10-05T12:18:34+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c98f6fed93ca49a956d628200b2dfa1454ce6fbb'/>
<id>c98f6fed93ca49a956d628200b2dfa1454ce6fbb</id>
<content type='text'>
This function is already defined in spi.h but no implementation of it
currently exists in the tree. The implementation is based on the static
function spi_set_speed_mode(). The function prototype is modified so
that an success or error condition can be returned to the caller.

Signed-off-by: Paul Barker &lt;paul.barker@sancloud.com&gt;
Reviewed-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This function is already defined in spi.h but no implementation of it
currently exists in the tree. The implementation is based on the static
function spi_set_speed_mode(). The function prototype is modified so
that an success or error condition can be returned to the caller.

Signed-off-by: Paul Barker &lt;paul.barker@sancloud.com&gt;
Reviewed-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: spi-uclass: Add new spi_get_bus_and_cs() implementation</title>
<updated>2022-05-23T13:33:10+00:00</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@foss.st.com</email>
</author>
<published>2022-03-30T07:33:13+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=61708bb0a24caad99b0e79de52077dafb59688d6'/>
<id>61708bb0a24caad99b0e79de52077dafb59688d6</id>
<content type='text'>
Move legacy spi_get_bus_and_cs() code to _spi_get_bus_and_cs().

Add new spi_get_bus_and_cs() implementation which rely on DT
for speed and mode and don't need any drv_name nor dev_name
parameters. This will prepare the ground for next patch.

Update all callers to use _spi_get_bus_and_cs() to keep the
same behavior.

Signed-off-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;

Cc: Marek Behun &lt;marek.behun@nic.cz&gt;
Cc: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Cc: Vignesh R &lt;vigneshr@ti.com&gt;
Cc: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Cc: Ramon Fried &lt;rfried.dev@gmail.com&gt;
Cc: Lukasz Majewski &lt;lukma@denx.de&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: "Pali Rohár" &lt;pali@kernel.org&gt;
Cc: Konstantin Porotchkin &lt;kostap@marvell.com&gt;
Cc: Igal Liberman &lt;igall@marvell.com&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Pratyush Yadav &lt;p.yadav@ti.com&gt;
Cc: Sean Anderson &lt;seanga2@gmail.com&gt;
Cc: Anji J &lt;anji.jagarlmudi@nxp.com&gt;
Cc: Biwen Li &lt;biwen.li@nxp.com&gt;
Cc: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
Cc: Chaitanya Sakinam &lt;chaitanya.sakinam@nxp.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Move legacy spi_get_bus_and_cs() code to _spi_get_bus_and_cs().

Add new spi_get_bus_and_cs() implementation which rely on DT
for speed and mode and don't need any drv_name nor dev_name
parameters. This will prepare the ground for next patch.

Update all callers to use _spi_get_bus_and_cs() to keep the
same behavior.

Signed-off-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;

Cc: Marek Behun &lt;marek.behun@nic.cz&gt;
Cc: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Cc: Vignesh R &lt;vigneshr@ti.com&gt;
Cc: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
Cc: Ramon Fried &lt;rfried.dev@gmail.com&gt;
Cc: Lukasz Majewski &lt;lukma@denx.de&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Cc: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: "Pali Rohár" &lt;pali@kernel.org&gt;
Cc: Konstantin Porotchkin &lt;kostap@marvell.com&gt;
Cc: Igal Liberman &lt;igall@marvell.com&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Pratyush Yadav &lt;p.yadav@ti.com&gt;
Cc: Sean Anderson &lt;seanga2@gmail.com&gt;
Cc: Anji J &lt;anji.jagarlmudi@nxp.com&gt;
Cc: Biwen Li &lt;biwen.li@nxp.com&gt;
Cc: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
Cc: Chaitanya Sakinam &lt;chaitanya.sakinam@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>doc: replace @return by Return:</title>
<updated>2022-01-19T17:11:34+00:00</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>heinrich.schuchardt@canonical.com</email>
</author>
<published>2022-01-19T17:05:50+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=185f812c419f1b4f0d10d9787d59cf9f11a2a600'/>
<id>185f812c419f1b4f0d10d9787d59cf9f11a2a600</id>
<content type='text'>
Sphinx expects Return: and not @return to indicate a return value.

find . -name '*.c' -exec \
sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \;

find . -name '*.h' -exec \
sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \;

Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Sphinx expects Return: and not @return to indicate a return value.

find . -name '*.c' -exec \
sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \;

find . -name '*.h' -exec \
sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \;

Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
