u-boot.git/include/xilinx.h, branch master

arm64: versal2: Add PL bit stream load support

2025-04-16T11:44:44+00:00

Add support for loading the secure & non-secure pdi images and PL
bitstream on the Versal Gen2 platform. The FPGA driver is enabled
to load the bitstream in PDI format on the AMD Versal Gen2 device.
PDI is the new programmable device image format for Versal Gen2,
and the bitstream for the Versal Gen2 platform is generated exclusively
in this format.

With the enhanced SMC format in TF-A ensuring transparent payload
forwarding for Versal Gen2, the u-boot driver must now handle the
word swapping of PDI address that was previously done in TF-A for
this API. The source code for the Versal2 loadpdi command and the
CONFIG_CMD_VERSAL2 configuration has been removed. It now utilizes
the fpga load    command to load secure &
non-secure pdi images.

Signed-off-by: Prasad Kummari 
Link: https://lore.kernel.org/r/20250327105200.1262615-3-prasad.kummari@amd.com
Signed-off-by: Michal Simek

arm64: versal-net: Add PL bit stream load support

2025-04-16T11:44:44+00:00

Add support for loading the secure & non-secure pdi images and
PL bitstream on the Versal NET platform. The FPGA driver is enabled
to load the bitstream in PDI format on the AMD Versal NET device.
PDI is the new programmable device image format for Versal NET,
and the bitstream for the Versal NET platform is generated exclusively
in this format.

The source code for the versalnet loadpdi command and the
CONFIG_CMD_VERSAL_NET configuration has been removed. It now utilizes
the fpga load    command to load secure &
non-secure pdi images.

Signed-off-by: Prasad Kummari 
Link: https://lore.kernel.org/r/20250327105200.1262615-2-prasad.kummari@amd.com
Signed-off-by: Michal Simek

fpga: zynqmp: support loading encrypted bitfiles

2022-07-26T07:34:21+00:00

Add supporting new compatible string "u-boot,zynqmp-fpga-enc" to
handle loading encrypted bitfiles.

This feature requires encrypted FSBL, as according to UG1085:
"The CSU automatically locks out the AES key, stored in either BBRAM
 or eFUSEs, as a key source to the AES engine if the FSBL is not
 encrypted. This prevents using the BBRAM or eFUSE as the key source
 to the AES engine during run-time applications."

Signed-off-by: Adrian Fiergolski 
Co-developed-by: Oleksandr Suvorov 
Signed-off-by: Oleksandr Suvorov 
Tested-by: Adrian Fiergolski 
Link: https://lore.kernel.org/r/20220722141614.297383-14-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek

fpga: zynqmp: support loading authenticated images

2022-07-26T07:34:21+00:00

Add supporting new compatible string "u-boot,zynqmp-fpga-ddrauth" to
handle loading authenticated images (DDR).

Based on solution by Jorge Ramirez-Ortiz 

Signed-off-by: Oleksandr Suvorov 
Tested-by: Ricardo Salveti 
Link: https://lore.kernel.org/r/20220722141614.297383-13-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek

fpga: xilinx: pass compatible flags to load() callback

2022-07-26T07:34:21+00:00

These flags may be used to check whether an FPGA driver is able to
load a particular FPGA bitstream image.

Signed-off-by: Oleksandr Suvorov 
Tested-by: Ricardo Salveti 
Tested-by: Adrian Fiergolski 
Link: https://lore.kernel.org/r/20220722141614.297383-10-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek

fpga: xilinx: pass compatible flags to xilinx_load()

2022-07-26T07:34:21+00:00

This flag is used to check whether a Xilinx FPGA driver is able to
load a particular FPGA bitstream image.

Signed-off-by: Oleksandr Suvorov 
Tested-by: Ricardo Salveti 
Tested-by: Adrian Fiergolski 
Link: https://lore.kernel.org/r/20220722141614.297383-6-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek

fpga: zynqmp: add str2flags call

2022-07-26T07:34:21+00:00

Add a call to convert FPGA "compatible" string to a binary flag.

Signed-off-by: Oleksandr Suvorov 
Tested-by: Ricardo Salveti 
Tested-by: Adrian Fiergolski 
Link: https://lore.kernel.org/r/20220722141614.297383-5-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek

fpga: xilinx: add bitstream flags to driver desc

2022-07-26T07:34:21+00:00

Store a set of supported bitstream types in xilinx_desc structure.
It will be used to determine whether an FPGA image is able to be
loaded with a given driver.

Signed-off-by: Oleksandr Suvorov 
Tested-by: Ricardo Salveti 
Tested-by: Adrian Fiergolski 
Link: https://lore.kernel.org/r/20220722141614.297383-4-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek

fpga: xilinx: add missed identifier names

2022-07-26T07:34:21+00:00

Function definition arguments should also have identifier names.
Add missed ones to struct xilinx_fpga_op callbacks, unifying code.

Signed-off-by: Oleksandr Suvorov 
Tested-by: Ricardo Salveti 
Tested-by: Adrian Fiergolski 
Link: https://lore.kernel.org/r/20220722141614.297383-3-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek

arm64: versal: fpga: Add PL bit stream load support

2019-10-08T07:11:14+00:00

This patch adds PL bitstream load support for Versal platform. The PL
bitstream is loaded by making an SMC to ATF which in turn communicates
with platform firmware which configures and loads PL bitstream on to PL.

Signed-off-by: Siva Durga Prasad Paladugu 
Signed-off-by: Michal Simek