u-boot.git/include/xilinx.h, branch v2014.01 Unnamed repository; edit this file 'description' to name the repository. Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24T13:44:38+00:00 Wolfgang Denk wd@denx.de 2013-07-08T07:37:19+00:00 1a4596601fd395f3afb8f82f3f840c5e00bdd57a Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> 
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
fpga: Remove all CONFIG_SYS_* fpga related options 2013-05-06T08:41:30+00:00 Michal Simek michal.simek@xilinx.com 2013-05-01T16:05:56+00:00 b03b25caea1ff3a501161f5bc1ad5e5b5b124e0c All these macros are completely unused by any code. CONFIG_FPGA is not a bitfield anymore. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com> 
All these macros are completely unused by any code.
CONFIG_FPGA is not a bitfield anymore.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
fpga: Check device name against bitstream name 2013-05-06T08:41:25+00:00 Michal Simek michal.simek@xilinx.com 2013-04-26T13:04:48+00:00 6631db4773cd735688bf3332173a49271df23385 Ensure that wrong bitstream won't be loaded to current device. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com> 
Ensure that wrong bitstream won't be loaded
to current device.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
fpga: zynq: Add support for loading bitstream 2013-05-06T08:41:24+00:00 Michal Simek michal.simek@xilinx.com 2013-04-22T13:43:02+00:00 d5dae85f23c7c902731512e451afde9a6e4a250a Devcfg device requires to load bitstream in binary format. But u-boot also has an option for loading bitstream in bit format. Let's handle both cases by zynqpl driver. Also add suport for loading partial bitstreams. The first driver version was done by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com> 
Devcfg device requires to load bitstream in binary format.
But u-boot also has an option for loading bitstream in bit
format. Let's handle both cases by zynqpl driver.
Also add suport for loading partial bitstreams.

The first driver version was done by:
Joe Hershberger <joe.hershberger@ni.com>

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
fpga: constify to fix build warning 2011-08-01T13:19:40+00:00 Wolfgang Denk wd@denx.de 2011-07-30T13:33:49+00:00 e6a857da746d5d7d450e59c0f86664c6b279b1c2 Fix compiler warning: cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data' from incompatible pointer type Adding the needed 'const' here entails a whole bunch of additonal changes all over the FPGA code. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andre Schwarz <andre.schwarz@matrix-vision.de> Cc: Murray Jensen <Murray.Jensen@csiro.au> Acked-by: Andre Schwarz<andre.schwarz@matrix-vision.de> 
Fix compiler warning:

cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data'
from incompatible pointer type

Adding the needed 'const' here entails a whole bunch of additonal
changes all over the FPGA code.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andre Schwarz <andre.schwarz@matrix-vision.de>
Cc: Murray Jensen <Murray.Jensen@csiro.au>
Acked-by: Andre Schwarz<andre.schwarz@matrix-vision.de>
add block write function to spartan3 slave serial load 2010-03-24T16:08:43+00:00 Wolfgang Wegner w.wegner@astro-kom.de 2009-10-30T15:55:02+00:00 89083346d0627a5e6e271e61bd34ab5121f9462b Using seperate function calls for each bit-bang of slave serial load can be painfully slow. This patch adds the possibility to supply a block write function that loads the complete block of data in one call (like it can already be done with Altera FPGAs). On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load time from around 15 seconds to around 3 seconds Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de> 
Using seperate function calls for each bit-bang of slave serial
load can be painfully slow. This patch adds the possibility to
supply a block write function that loads the complete block of
data in one call (like it can already be done with Altera FPGAs).
On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load
time from around 15 seconds to around 3 seconds

Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
fpga: Remove relocation fixups 2009-10-03T08:17:56+00:00 Peter Tyser ptyser@xes-inc.com 2009-09-21T16:20:32+00:00 6385b28116f775da4771b768ba9bf93c3aaaf26e PPC boards are the only users of the current FPGA code which is littered with manual relocation fixups. Now that proper relocation is supported for PPC boards, remove FPGA manual relocation. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> 
PPC boards are the only users of the current FPGA code which is littered
with manual relocation fixups.  Now that proper relocation is supported
for PPC boards, remove FPGA manual relocation.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
rename CFG_ macros to CONFIG_SYS 2008-10-18T19:54:03+00:00 Jean-Christophe PLAGNIOL-VILLARD plagnioj@jcrosoft.com 2008-10-16T13:01:15+00:00 6d0f6bcf337c5261c08fabe12982178c2c489d76 Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Big white-space cleanup. 2008-05-20T22:14:08+00:00 Wolfgang Denk wd@denx.de 2008-05-20T14:00:29+00:00 53677ef18e25c97ac613349087c5cb33ae5a2741 This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de> 
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).

Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Improve configuration of FPGA subsystem 2008-01-09T12:34:20+00:00 Matthias Fuchs matthias.fuchs@esd-electronics.com 2007-12-27T16:12:34+00:00 0133502e39ff89b67c26cb4015e0e7e8d9571184 This patch removes the FPGA subsystem configuration through the CONFIG_FPGA bitmask configuration option. See README for the new options: CONFIG_FPGA, CONFIG_FPGA_<vendor>, CONFIG_FPGA_<family> Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> 
This patch removes the FPGA subsystem configuration through
the CONFIG_FPGA bitmask configuration option.

See README for the new options:

	CONFIG_FPGA,
	CONFIG_FPGA_<vendor>,
	CONFIG_FPGA_<family>

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>