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<title>u-boot.git/include/zynqpl.h, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>ARM: zynq: Add support for 7z010_lr and 7z020_lr</title>
<updated>2024-08-05T14:13:26+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@amd.com</email>
</author>
<published>2024-07-30T13:50:17+00:00</published>
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<id>5389564b521490f8e97299c2f82e26cbf75fc796</id>
<content type='text'>
Add support for *_lr SOCs. Without this change chips are not going to be
properly identified and bitstream programming won't work.

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/14d8905a89d1b31fbb2318512cf57eb0256c11be.1722347416.git.michal.simek@amd.com
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<pre>
Add support for *_lr SOCs. Without this change chips are not going to be
properly identified and bitstream programming won't work.

Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/14d8905a89d1b31fbb2318512cf57eb0256c11be.1722347416.git.michal.simek@amd.com
</pre>
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</entry>
<entry>
<title>fpga: zynqpl: Correct PL bitstream loading sequence for zynqaes</title>
<updated>2020-06-24T11:07:57+00:00</updated>
<author>
<name>Siva Durga Prasad Paladugu</name>
<email>siva.durga.paladugu@xilinx.com</email>
</author>
<published>2015-12-09T13:16:43+00:00</published>
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<id>3427f4d2045729c8995b19407daf91ea9a50e4f8</id>
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Correct the PL bitstream loading sequence for zynqaes command by
clearing the loaded PL bitstream before loading the new encrypted
bitstream using the zynq aes command. This was done by setting
the PROG_B same as in case of fpgaload commands.
This patch fixes the issue of loading the encrypted PL bitstream
onto the PL in which a bitstream has already been loaded
successfully.

Signed-off-by: Siva Durga Prasad Paladugu &lt;siva.durga.paladugu@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
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<pre>
Correct the PL bitstream loading sequence for zynqaes command by
clearing the loaded PL bitstream before loading the new encrypted
bitstream using the zynq aes command. This was done by setting
the PROG_B same as in case of fpgaload commands.
This patch fixes the issue of loading the encrypted PL bitstream
onto the PL in which a bitstream has already been loaded
successfully.

Signed-off-by: Siva Durga Prasad Paladugu &lt;siva.durga.paladugu@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>xilinx: zynq: Add support to secure images</title>
<updated>2018-07-19T08:49:54+00:00</updated>
<author>
<name>Siva Durga Prasad Paladugu</name>
<email>siva.durga.paladugu@xilinx.com</email>
</author>
<published>2018-06-26T09:32:19+00:00</published>
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<id>37e3a36a54755d15e36b52ee47caaf1cdfdc37aa</id>
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This patch basically adds two new commands for loadig secure
images.
1. zynq rsa adds support to load secure image which can be both
   authenticated or encrypted or both authenticated and encrypted
   image in xilinx bootimage(BOOT.bin) format.
2. zynq aes command adds support to decrypt and load encrypted
   image back to DDR as per destination address. The image has
   to be encrypted using xilinx bootgen tool and to get only the
   encrypted image from tool use -split option while invoking
   bootgen.

Signed-off-by: Siva Durga Prasad Paladugu &lt;siva.durga.paladugu@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
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<pre>
This patch basically adds two new commands for loadig secure
images.
1. zynq rsa adds support to load secure image which can be both
   authenticated or encrypted or both authenticated and encrypted
   image in xilinx bootimage(BOOT.bin) format.
2. zynq aes command adds support to decrypt and load encrypted
   image back to DDR as per destination address. The image has
   to be encrypted using xilinx bootgen tool and to get only the
   encrypted image from tool use -split option while invoking
   bootgen.

Signed-off-by: Siva Durga Prasad Paladugu &lt;siva.durga.paladugu@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>arm: zynq: Rework FPGA initialization</title>
<updated>2018-05-11T07:23:43+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2018-01-17T13:56:22+00:00</published>
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<id>4aba5fb857c1b0067226dbd457d51ac2b2825427</id>
<content type='text'>
This commit moves the FPGA descriptor definition
to mach-zynq, where it makes more sense.

Based on patches from Ariel D'Alessandro &lt;ariel@vanguardiasur.com.ar&gt;
and Ezequiel Garcia &lt;ezequiel@vanguardiasur.com.ar&gt;

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
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<pre>
This commit moves the FPGA descriptor definition
to mach-zynq, where it makes more sense.

Based on patches from Ariel D'Alessandro &lt;ariel@vanguardiasur.com.ar&gt;
and Ezequiel Garcia &lt;ezequiel@vanguardiasur.com.ar&gt;

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>SPDX: Convert all of our single license tags to Linux Kernel style</title>
<updated>2018-05-07T13:34:12+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-05-06T21:58:06+00:00</published>
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<id>83d290c56fab2d38cd1ab4c4cc7099559c1d5046</id>
<content type='text'>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
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<pre>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: zynq: Add support for Zynq 7000S 7007s/7012s/7014s devices</title>
<updated>2016-11-15T14:28:04+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2016-10-18T14:10:25+00:00</published>
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<id>05c59d0bc83f28888e5f2cc11b679a721605a46b</id>
<content type='text'>
Zynq 7000S (Single A9 core) devices is using different ID code.
This patch adds this new codes and assign them.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
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<pre>
Zynq 7000S (Single A9 core) devices is using different ID code.
This patch adds this new codes and assign them.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: zynqpl: Add support for zc7035</title>
<updated>2015-01-21T09:25:53+00:00</updated>
<author>
<name>Siva Durga Prasad Paladugu</name>
<email>siva.durga.paladugu@xilinx.com</email>
</author>
<published>2014-11-25T09:59:54+00:00</published>
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<id>b9103809eb9052f40479d2d741e980832b75ebba</id>
<content type='text'>
Added support for zc7035

Signed-off-by: Siva Durga Prasad Paladugu &lt;sivadur@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
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<pre>
Added support for zc7035

Signed-off-by: Siva Durga Prasad Paladugu &lt;sivadur@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>fpga: xilinx: zynqpl: Setup NULL fpga_op without driver</title>
<updated>2015-01-21T09:25:03+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2014-07-16T08:47:13+00:00</published>
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<id>345f9e195675207372efbb492f29dcfdcb938fd7</id>
<content type='text'>
Set fpga operations to NULL for cases where
FPGA is setup in board file but driver is not added

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
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<pre>
Set fpga operations to NULL for cases where
FPGA is setup in board file but driver is not added

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: xilinx: Simplify load/dump/info function handling</title>
<updated>2014-05-13T07:13:59+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2014-03-13T12:07:57+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=14cfc4f3735d9704cb6a630ef302be596d380684'/>
<id>14cfc4f3735d9704cb6a630ef302be596d380684</id>
<content type='text'>
Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
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<pre>
Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: xilinx: Avoid CamelCase for in Xilinx_desc</title>
<updated>2014-05-13T07:12:53+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2014-03-13T11:49:21+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f8c1be9816a60d1f627954fe202b502917c69863'/>
<id>f8c1be9816a60d1f627954fe202b502917c69863</id>
<content type='text'>
No functional changes.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
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<pre>
No functional changes.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</pre>
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</content>
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