- mmc minor update for better debug and error check - fsl_esdhc sysctl set and make sure delay check for HS400
Pack struct efi_mm_communicate_header as done in EDK2 as seen in
release 201808 [1]. If not packed sizeof() for the structure adds
4 additional bytes on 32bit targets which breaks the ABI.
Link: [1] https://github.com/tianocore/edk2/blob/edk2-stable201808/MdePkg/Include/Protocol/MmCommunication.h#L21
Fixes: 23a397d2e2fb ("efi_loader: Add headers for EDK2 StandAloneMM communication")
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
For eMMC HS400 mode, the DLL reset is a required step for mmc rescan.
This step has not been documented in reference manual, but the RM will
be fixed sooner or later.
In previous commit to support eMMC HS400,
db8f936 mmc: fsl_esdhc: support eMMC HS400 mode
the steps to configure DLL could be found in commit message,
13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL].
14. Wait for delay chain to lock.
these would be fixed as,
13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL].
13.1 Write DLLCFG0[DLL_RESET] to 1 and wait for 1us,
then write DLLCFG0[DLL_RESET]
14. Wait for delay chain to lock.
This patch is to add the step of DLL reset, and make sure delay chain
locked for HS400.
Fixes: db8f93672b42 ("mmc: fsl_esdhc: support eMMC HS400 mode")
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Handle the register RCC_MP_GCR without SET/CLR registers but with a direct access to bit BOOT_MCU: - deassert => set the bit: The MCU will not be in HOLD_BOOT - assert => clear the bit: The MCU will be set in HOLD_BOOT With this patch the RCC driver handles the MCU_HOLD_BOOT_R value added in binding stm32mp1-resets.h Cc: Fabien DESSENNE <fabien.dessenne@st.com> Cc: Arnaud POULIQUEN <arnaud.pouliquen@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
On some board, the ID pin is not connected so the B session must be overridden with "u-boot,force_b_session_valid" but the VBus sensing must continue to be handle. To managed it, this patch adds a new DT field "u-boot,force-vbus-detection" to use with "u-boot,force_b_session_valid" Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Pull request for UEFI sub-system for efi-2021-01-rc3 (2) The parameter check for UEFI service GetNextVariableName() is corrected. The dependencies of CONFIG_DFU_TFTP are simplified. The set of supported hash algorithms reported by the EFI_TCG2_PROTOCOL is corrected.
On pull reuqest https://lists.denx.de/pipermail/u-boot/2020-November/432735.html V4 of the patchset was sent instead of the v5. This is the v4->v5 missing diff Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Remove fixed configuration and detect flash based on DT. Also increase amount of flash sectors to 2048 because on kc705 flash has 1027 sectors. Bank # 1: CFI conformant flash (16 x 16) Size: 128 MB in 1027 Sectors Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x8962 Erase timeout: 4096 ms, write timeout: 2 ms Buffer write timeout: 5 ms, buffer size: 1024 bytes Signed-off-by: Michal Simek <michal.simek@xilinx.com>
XIP is not enabled in SPL. SPL_NOR is enabled but any macro setting with using SYS_FLASH_BASE are wrong because it is not aligned with DM. That's why change these macro and align them with TEXT_BASE macro. Information should be find at run time based on DT but implementation is not done yet. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
CONFIG_SYS_FDT_SIZE is not use anywhere that's why remove it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>