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<title>u-boot.git/include, branch v2025.10-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>include: configs: Add config header file for Agilex7 M-series</title>
<updated>2025-08-08T14:20:52+00:00</updated>
<author>
<name>Tingting Meng</name>
<email>tingting.meng@altera.com</email>
</author>
<published>2025-08-04T01:24:52+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f64130138aa743e1508f275c56593b85168b53a2'/>
<id>f64130138aa743e1508f275c56593b85168b53a2</id>
<content type='text'>
Add config header file for new platform Agilex7 M-series.

Signed-off-by: Tingting Meng &lt;tingting.meng@altera.com&gt;
Signed-off-by: Alif Zakuan Yuslaimi &lt;alif.zakuan.yuslaimi@altera.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@altera.com&gt;
</content>
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<pre>
Add config header file for new platform Agilex7 M-series.

Signed-off-by: Tingting Meng &lt;tingting.meng@altera.com&gt;
Signed-off-by: Alif Zakuan Yuslaimi &lt;alif.zakuan.yuslaimi@altera.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@altera.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: socfpga: soc64: Perform warm reset after L2 reset in SPL</title>
<updated>2025-08-08T14:20:50+00:00</updated>
<author>
<name>Alif Zakuan Yuslaimi</name>
<email>alif.zakuan.yuslaimi@altera.com</email>
</author>
<published>2025-08-04T01:24:45+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=71916a72f106ed2aaae5a49885fb86623e5f7aec'/>
<id>71916a72f106ed2aaae5a49885fb86623e5f7aec</id>
<content type='text'>
SPL checks for a magic word in the system manager's scratch
register to determine if an L2 reset has occurred. If detected,
SPL places all slave CPUs (CPU1–3) into WFI mode. The master
CPU (CPU0) then initiates a warm reset by writing to the RMR_EL3
system register and also enters WFI mode.

This warm reset flow is handled entirely within the HPS. The
function `socfpga_sysreset_request()` triggers the warm
reset, and upon SPL re-entry, the updated `lowlevel_init_soc64.S`
handles the necessary initialization.

Signed-off-by: Alif Zakuan Yuslaimi &lt;alif.zakuan.yuslaimi@altera.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@altera.com&gt;
</content>
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<pre>
SPL checks for a magic word in the system manager's scratch
register to determine if an L2 reset has occurred. If detected,
SPL places all slave CPUs (CPU1–3) into WFI mode. The master
CPU (CPU0) then initiates a warm reset by writing to the RMR_EL3
system register and also enters WFI mode.

This warm reset flow is handled entirely within the HPS. The
function `socfpga_sysreset_request()` triggers the warm
reset, and upon SPL re-entry, the updated `lowlevel_init_soc64.S`
handles the necessary initialization.

Signed-off-by: Alif Zakuan Yuslaimi &lt;alif.zakuan.yuslaimi@altera.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@altera.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sysreset: socfpga: soc64: Enable L2 reset</title>
<updated>2025-08-08T14:20:50+00:00</updated>
<author>
<name>Alif Zakuan Yuslaimi</name>
<email>alif.zakuan.yuslaimi@altera.com</email>
</author>
<published>2025-08-04T01:24:44+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c8f5166cff0ccdb1966ed786dba88e9548ce632e'/>
<id>c8f5166cff0ccdb1966ed786dba88e9548ce632e</id>
<content type='text'>
Put all slave CPUs (CPU1-3) into WFI mode. Master CPU (CPU0) writes
the magic word into system manager's scratch register to indicate
the system has performed L2 reset and request reset manager to
perform hardware handshake and then trigger L2 reset. CPU0 put
itself into WFI mode. L2 reset will reboot all HPS CPU cores after
which all HPS cores are in WFI mode. L2 reset is followed by warm
reset request by SPL via RMR_EL3 system register.

Signed-off-by: Alif Zakuan Yuslaimi &lt;alif.zakuan.yuslaimi@altera.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@altera.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Put all slave CPUs (CPU1-3) into WFI mode. Master CPU (CPU0) writes
the magic word into system manager's scratch register to indicate
the system has performed L2 reset and request reset manager to
perform hardware handshake and then trigger L2 reset. CPU0 put
itself into WFI mode. L2 reset will reboot all HPS CPU cores after
which all HPS cores are in WFI mode. L2 reset is followed by warm
reset request by SPL via RMR_EL3 system register.

Signed-off-by: Alif Zakuan Yuslaimi &lt;alif.zakuan.yuslaimi@altera.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@altera.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>include: configs: socfpga: Add environment variables for distro boot</title>
<updated>2025-08-08T14:20:49+00:00</updated>
<author>
<name>Alif Zakuan Yuslaimi</name>
<email>alif.zakuan.yuslaimi@altera.com</email>
</author>
<published>2025-08-04T01:24:42+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9a7881abeb8c57e6d132c9303e487409a5340e51'/>
<id>9a7881abeb8c57e6d132c9303e487409a5340e51</id>
<content type='text'>
Added environment variables needed to support NAND distro boot

Signed-off-by: Alif Zakuan Yuslaimi &lt;alif.zakuan.yuslaimi@altera.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@altera.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Added environment variables needed to support NAND distro boot

Signed-off-by: Alif Zakuan Yuslaimi &lt;alif.zakuan.yuslaimi@altera.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@altera.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cmd: Add i3c command support.</title>
<updated>2025-08-06T06:41:30+00:00</updated>
<author>
<name>Dinesh Maniyam</name>
<email>dinesh.maniyam@altera.com</email>
</author>
<published>2025-08-06T04:32:32+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b875409da7370a9dc4e1abbaf40fa33c6717e854'/>
<id>b875409da7370a9dc4e1abbaf40fa33c6717e854</id>
<content type='text'>
Add i3c command file to support select, get i3c device
target list, read and write operation.

Signed-off-by: Dinesh Maniyam &lt;dinesh.maniyam@altera.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add i3c command file to support select, get i3c device
target list, read and write operation.

Signed-off-by: Dinesh Maniyam &lt;dinesh.maniyam@altera.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>i3c: master: dw-i3c-master: Fix OD_TIMING for spike filter</title>
<updated>2025-08-06T06:41:14+00:00</updated>
<author>
<name>Dinesh Maniyam</name>
<email>dinesh.maniyam@altera.com</email>
</author>
<published>2025-08-06T04:32:31+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=82cc368cd2b3bc8664d7e12f4f87af49c1783237'/>
<id>82cc368cd2b3bc8664d7e12f4f87af49c1783237</id>
<content type='text'>
Fix the I3C device with spike filter unable to detect issue by setting
tHIGH_INIT to 200ns for first broadcast address.
This is according to MIPI SPEC 1.1.1 for first broadcast address
which is already part of linux upstreamed patch.

Signed-off-by: Dinesh Maniyam &lt;dinesh.maniyam@altera.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Fix the I3C device with spike filter unable to detect issue by setting
tHIGH_INIT to 200ns for first broadcast address.
This is according to MIPI SPEC 1.1.1 for first broadcast address
which is already part of linux upstreamed patch.

Signed-off-by: Dinesh Maniyam &lt;dinesh.maniyam@altera.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: i3c: Add i3c uclass driver.</title>
<updated>2025-08-06T06:37:34+00:00</updated>
<author>
<name>Dinesh Maniyam</name>
<email>dinesh.maniyam@altera.com</email>
</author>
<published>2025-08-06T04:32:26+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e49a513760893082313b8369dc7b08f98f1055e6'/>
<id>e49a513760893082313b8369dc7b08f98f1055e6</id>
<content type='text'>
Enable i3c general uclass driver. This uclass driver will have
genaral read and write api to call the specific i3c driver.

Signed-off-by: Dinesh Maniyam &lt;dinesh.maniyam@altera.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Enable i3c general uclass driver. This uclass driver will have
genaral read and write api to call the specific i3c driver.

Signed-off-by: Dinesh Maniyam &lt;dinesh.maniyam@altera.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: i3c: Add driver for MIPI DWI3C</title>
<updated>2025-08-06T06:37:13+00:00</updated>
<author>
<name>Dinesh Maniyam</name>
<email>dinesh.maniyam@altera.com</email>
</author>
<published>2025-08-06T04:32:25+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1009c96f1590e1cd1938ab4607eeaf0d8cc485f2'/>
<id>1009c96f1590e1cd1938ab4607eeaf0d8cc485f2</id>
<content type='text'>
Enable driver for Synopsis MIPI DWI3C for the family
device agilex5. This driver is migrated from linux version 6.6.37 LTS

Signed-off-by: Dinesh Maniyam &lt;dinesh.maniyam@altera.com&gt;
</content>
<content type='xhtml'>
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<pre>
Enable driver for Synopsis MIPI DWI3C for the family
device agilex5. This driver is migrated from linux version 6.6.37 LTS

Signed-off-by: Dinesh Maniyam &lt;dinesh.maniyam@altera.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: i3c: Add new i3c uclass id</title>
<updated>2025-08-06T06:36:59+00:00</updated>
<author>
<name>Dinesh Maniyam</name>
<email>dinesh.maniyam@altera.com</email>
</author>
<published>2025-08-06T04:32:24+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=633c0cf4867bebf84b151d5c7b9bb4154beabd6b'/>
<id>633c0cf4867bebf84b151d5c7b9bb4154beabd6b</id>
<content type='text'>
Add i3c general uclass id.

Signed-off-by: Dinesh Maniyam &lt;dinesh.maniyam@altera.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add i3c general uclass id.

Signed-off-by: Dinesh Maniyam &lt;dinesh.maniyam@altera.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: bcm281xx: Remove ethernet driver</title>
<updated>2025-08-01T07:30:47+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2025-07-18T01:15:44+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3c1ac44caaa243acb7c3fe0aca412778b8cc28e6'/>
<id>3c1ac44caaa243acb7c3fe0aca412778b8cc28e6</id>
<content type='text'>
As no platforms enable the ethernet driver, remove it.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
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<pre>
As no platforms enable the ethernet driver, remove it.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
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