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<title>u-boot.git/lib, branch v2019.01-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>hashtable: fix length calculation in hexport_r</title>
<updated>2018-12-15T16:49:19+00:00</updated>
<author>
<name>AKASHI Takahiro</name>
<email>takahiro.akashi@linaro.org</email>
</author>
<published>2018-12-14T09:42:51+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4bca32497c09ef53ad669dfa4c413c00321ad7ca'/>
<id>4bca32497c09ef53ad669dfa4c413c00321ad7ca</id>
<content type='text'>
The commit below incorrectly fixed hexport_r();
 &gt;	size = totlen + 1;
One extra byte is necessary to NULL-terminate a whole buffer, "resp."

Fixes: f1b20acb4a03 ("hashtable: Fix length calculation in hexport_r")
Signed-off-by: AKASHI Takahiro &lt;takahiro.akashi@linaro.org&gt;
</content>
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<pre>
The commit below incorrectly fixed hexport_r();
 &gt;	size = totlen + 1;
One extra byte is necessary to NULL-terminate a whole buffer, "resp."

Fixes: f1b20acb4a03 ("hashtable: Fix length calculation in hexport_r")
Signed-off-by: AKASHI Takahiro &lt;takahiro.akashi@linaro.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>spl: fix build failure with !CONFIG_SPL_PCI_SUPPORT</title>
<updated>2018-12-12T17:14:23+00:00</updated>
<author>
<name>Sekhar Nori</name>
<email>nsekhar@ti.com</email>
</author>
<published>2018-12-06T10:10:08+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d50d6817b583d20bf1c6e26c656d125bde5e4e4b'/>
<id>d50d6817b583d20bf1c6e26c656d125bde5e4e4b</id>
<content type='text'>
Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but
CONFIG_SPL_PCI_SUPPORT disabled, results in following linker
error:

lib/built-in.o: In function `fdtdec_get_pci_bar32':
lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32'
fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32'

This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c
while SPL build does not descend into drivers/pci directory in
drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled.

Fix this by applying appropriate #define guards in lib/fdtdec.c.
It looks like ns16550.c has the same problem, so fixed that too.

To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI
(enables use of CONFIG_IS_ENABLED() macro).

Suggested-by: Vignesh R &lt;vigneshr@ti.com&gt;
Signed-off-by: Sekhar Nori &lt;nsekhar@ti.com&gt;
Reviewed-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
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<pre>
Building U-Boot with CONFIG_PCI and CONFIG_DM_PCI enabled, but
CONFIG_SPL_PCI_SUPPORT disabled, results in following linker
error:

lib/built-in.o: In function `fdtdec_get_pci_bar32':
lib/fdtdec.c:305: undefined reference to `dm_pci_read_bar32'
fdtdec.c:305:(.text.fdtdec_get_pci_bar32+0x24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `dm_pci_read_bar32'

This is because reference to dm_pci_read_bar32() remains in lib/fdtdec.c
while SPL build does not descend into drivers/pci directory in
drivers/Makefile if CONFIG_SPL_PCI_SUPPORT is not enabled.

Fix this by applying appropriate #define guards in lib/fdtdec.c.
It looks like ns16550.c has the same problem, so fixed that too.

To simplify this, CONFIG_SPL_PCI_SUPPORT is renamed to CONFIG_SPL_PCI
(enables use of CONFIG_IS_ENABLED() macro).

Suggested-by: Vignesh R &lt;vigneshr@ti.com&gt;
Signed-off-by: Sekhar Nori &lt;nsekhar@ti.com&gt;
Reviewed-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>lib: fdtdec: Add function re-setup the fdt more effeciently</title>
<updated>2018-12-10T06:21:21+00:00</updated>
<author>
<name>Jean-Jacques Hiblot</name>
<email>jjhiblot@ti.com</email>
</author>
<published>2018-12-07T13:50:52+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f1d2bc9034053e7d8ad0e77b9a0399f451bb5b80'/>
<id>f1d2bc9034053e7d8ad0e77b9a0399f451bb5b80</id>
<content type='text'>
In some cases it may be useful to be able to change the fdt we have been
using and use another one instead. For example, the TI platforms uses an
EEPROM to store board information and, based on the type of board,
different dtbs are used by the SPL. When DM_I2C is used, a first dtb must
be used before the I2C is initialized and only then the final dtb can be
selected.
To speed up the process and reduce memory usage, introduce a new function
fdtdec_setup_best_match() that re-use the DTBs loaded in memory by
fdtdec_setup() to select the best match.

Signed-off-by: Jean-Jacques Hiblot &lt;jjhiblot@ti.com&gt;
Reviewed-by: Heiko Schocher &lt;hs@denx.de&gt;
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<pre>
In some cases it may be useful to be able to change the fdt we have been
using and use another one instead. For example, the TI platforms uses an
EEPROM to store board information and, based on the type of board,
different dtbs are used by the SPL. When DM_I2C is used, a first dtb must
be used before the I2C is initialized and only then the final dtb can be
selected.
To speed up the process and reduce memory usage, introduce a new function
fdtdec_setup_best_match() that re-use the DTBs loaded in memory by
fdtdec_setup() to select the best match.

Signed-off-by: Jean-Jacques Hiblot &lt;jjhiblot@ti.com&gt;
Reviewed-by: Heiko Schocher &lt;hs@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Roll CRC16-CCITT into the hash infrastructure</title>
<updated>2018-12-09T01:18:44+00:00</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2018-11-25T18:22:19+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=51c2345bd24837f9f67f16268da6dc71573f1325'/>
<id>51c2345bd24837f9f67f16268da6dc71573f1325</id>
<content type='text'>
The CRC16-CCITT checksum function is useful for space-constrained
applications (such as obtaining a checksum across a 2KBit or 4KBit
EEPROM) in boot applications. It has not been accessible from boot
scripts until now (due to not having a dedicated command and not being
supported by the hash infrstructure) limiting its applicability
outside of custom commands.

This adds the CRC16-CCITT (poly 0x1021, init 0x0) algorithm to the
list of available hashes and adds a new crc16_ccitt_wd_buf() to make
this possible.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
[trini: Fix building crc16.o for SPL/TPL]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
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<pre>
The CRC16-CCITT checksum function is useful for space-constrained
applications (such as obtaining a checksum across a 2KBit or 4KBit
EEPROM) in boot applications. It has not been accessible from boot
scripts until now (due to not having a dedicated command and not being
supported by the hash infrstructure) limiting its applicability
outside of custom commands.

This adds the CRC16-CCITT (poly 0x1021, init 0x0) algorithm to the
list of available hashes and adds a new crc16_ccitt_wd_buf() to make
this possible.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
[trini: Fix building crc16.o for SPL/TPL]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>lib: merge CRC16-CCITT into u-boot/crc.h</title>
<updated>2018-12-09T01:18:32+00:00</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2018-11-25T18:22:18+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a740ee913ec8ba04cc53100440f94841648324e2'/>
<id>a740ee913ec8ba04cc53100440f94841648324e2</id>
<content type='text'>
This merges the CRC16-CCITT headers into u-boot/crc.h to prepare for
rolling CRC16 into the hash infrastructure.  Given that CRC8, CRC32
and CRC32-C already have their prototypes in a single header file, it
seems a good idea to also include CRC16-CCITT in the same.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
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<pre>
This merges the CRC16-CCITT headers into u-boot/crc.h to prepare for
rolling CRC16 into the hash infrastructure.  Given that CRC8, CRC32
and CRC32-C already have their prototypes in a single header file, it
seems a good idea to also include CRC16-CCITT in the same.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>tpm: Fix a logging warning in unpack_byte_string()</title>
<updated>2018-12-05T13:01:34+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2018-11-24T04:29:35+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5092af6b571c883c49da2b6df7419d73874cdba4'/>
<id>5092af6b571c883c49da2b6df7419d73874cdba4</id>
<content type='text'>
Fix the printf() string to avoid a warning.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
Fix the printf() string to avoid a warning.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>tpm: Remove use of build-time TPM versions</title>
<updated>2018-12-05T13:01:34+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2018-11-24T04:29:32+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0a60a0a65fa98f265c79f3928d8628aabcba8a92'/>
<id>0a60a0a65fa98f265c79f3928d8628aabcba8a92</id>
<content type='text'>
There is only one place in the code which assumes at build-time that we
are using either a v1 or a v2 TPM. Fix this up and add a new function to
return the version of a TPM.

Supported TPM versions (v1 and v2) can be enabled independently and it is
possible to use both versions at once. This is useful for sandbox when
running tests.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
There is only one place in the code which assumes at build-time that we
are using either a v1 or a v2 TPM. Fix this up and add a new function to
return the version of a TPM.

Supported TPM versions (v1 and v2) can be enabled independently and it is
possible to use both versions at once. This is useful for sandbox when
running tests.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sandbox: physmem: Use mapping to support sandbox</title>
<updated>2018-12-05T13:01:34+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2018-11-24T04:29:26+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e3491fb11f54e642925f587ed2dd6c98aea9c65d'/>
<id>e3491fb11f54e642925f587ed2dd6c98aea9c65d</id>
<content type='text'>
Replace the raw cast with a map_sysmem() call so this code works with
sandbox.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
Replace the raw cast with a map_sysmem() call so this code works with
sandbox.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot</title>
<updated>2018-12-03T22:52:40+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-12-03T22:52:40+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f388e3bed7318efe97058b673801dda6f563d319'/>
<id>f388e3bed7318efe97058b673801dda6f563d319</id>
<content type='text'>
Patch queue for efi - 2018-12-03

This release is fully packed with lots of glorious improvements in UEFI
land again!

  - Make PE images more standards compliant
  - Improve sandbox support
  - Improve correctness
  - Fix RISC-V execution on virt model
  - Honor board defined top of ram (fixes a few boards)
  - Imply DM USB access when distro boot is available
  - Code cleanups
</content>
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<pre>
Patch queue for efi - 2018-12-03

This release is fully packed with lots of glorious improvements in UEFI
land again!

  - Make PE images more standards compliant
  - Improve sandbox support
  - Improve correctness
  - Fix RISC-V execution on virt model
  - Honor board defined top of ram (fixes a few boards)
  - Imply DM USB access when distro boot is available
  - Code cleanups
</pre>
</div>
</content>
</entry>
<entry>
<title>rsa: add support of padding pss</title>
<updated>2018-12-03T15:44:10+00:00</updated>
<author>
<name>Philippe Reynes</name>
<email>philippe.reynes@softathome.com</email>
</author>
<published>2018-11-14T12:51:01+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=061daa0b61f0fbeb214c566f3adb23da05545320'/>
<id>061daa0b61f0fbeb214c566f3adb23da05545320</id>
<content type='text'>
We add the support of the padding pss for rsa signature.
This new padding is often recommended instead of pkcs-1.5.

Signed-off-by: Philippe Reynes &lt;philippe.reynes@softathome.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
We add the support of the padding pss for rsa signature.
This new padding is often recommended instead of pkcs-1.5.

Signed-off-by: Philippe Reynes &lt;philippe.reynes@softathome.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
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