u-boot.git/nand_spl/board, branch v2009.08

Fix all linker scripts for older binutils versions (pre-2.16)

2009-08-21T21:13:34Z

Commit f62fb99941c6 fixed handling of all rodata sections by using a wildcard combined with calls to ld's builtin functions SORT_BY_ALIGNMENT() and SORT_BY_NAME(). Unfortunately these functions were only introduced with biunutils version 2.16, so the modification broke building with all tool chains using older binutils. This patch makes it work again. This is done by omitting the use of these functions for such old tool chains. This will result in slightly larger target binaries, as the rodata sections are no longer in optimal order alignment-wise which reauls in unused gaps, but the effect was found to be insignificant - especially compared to the fact that you cannot build U-Boot at all in the current state. As ld seems to have no support for conditionals we run the linker script through the C preprocessor which can be easily used to remove the unwanted function calls. Note that the C preprocessor must be run with the "-ansi" (or a "-std=") option to make sure all the system-specific predefined macros outside the reserved namespace are suppressed. Otherise, cpp might for example substitute "powerpc" to "1", thus corrupting for example "OUTPUT_ARCH(powerpc)" etc. Signed-off-by: Wolfgang Denk Cc: Mike Frysinger

ppc4xx: Canyonlands-NAND-boot: Support 2 Crucial 512MByte SODIMM's

2009-07-30T05:22:18Z

Some Canyonlands boards are equipped with different SODIMM's. This is no problem with the "normal" NOR booting Canyonlands U-Boot, since it automatically detects the SODIMM's via SPD data and correctly configures them. But the NAND booting version is different. Here we only have 4k of image size to completely setup the hardware, including DDR2 setup. So we need to use a fixed DDR2 setup here. This doesn't work for different SODIMM's right now. Currently only this Crucial SODIMM is support: CT6464AC667.8FB (dual ranked) Now some boards are shipped with this SODIMM: CT6464AC667.4FE (single ranked) This patch now supports both SODIMM's by configuring first for the dual ranked DIMM. A quick shows, if this module is really installed. If this test fails, the DDR2 controller is re-configured for the single ranked SODIMM. Tested with those SODIMM's: CT6464AC667.8FB (dual ranked) CT6464AC667.4FE (single ranked) Signed-off-by: Stefan Roese

nand/ppc4xx: Move PPC4xx NAND driver to common NAND driver directory

2009-07-16T22:52:02Z

Signed-off-by: Stefan Roese Cc: Scott Wood Signed-off-by: Scott Wood

MX31: Add NAND SPL boot support to i.MX31 PDK board.

2009-07-06T19:53:18Z

Signed-off-by: Magnus Lilja

Fix e-mail address of Gary Jennejohn.

2009-05-15T20:11:59Z

Signed-off-by: Detlev Zundel

Fix all linker script to handle all rodata sections

2009-03-20T21:39:12Z

A recent gcc added a new unaligned rodata section called '.rodata.str1.1', which needs to be added the the linker script. Instead of just adding this one section, we use a wildcard ".rodata*" to get all rodata linker section gcc has now and might add in the future. However, '*(.rodata*)' by itself will result in sub-optimal section ordering. The sections will be sorted by object file, which causes extra padding between the unaligned rodata.str.1.1 of one object file and the aligned rodata of the next object file. This is easy to fix by using the SORT_BY_ALIGNMENT command. This patch has not be tested one most of the boards modified. Some boards have a linker script that looks something like this: *(.text) . = ALIGN(16); *(.rodata) *(.rodata.str1.4) *(.eh_frame) I change this to: *(.text) . = ALIGN(16); *(.eh_frame) *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) This means the start of rodata will no longer be 16 bytes aligned. However, the boundary between text and rodata/eh_frame is still aligned to 16 bytes, which is what I think the real purpose of the ALIGN call is. Signed-off-by: Trent Piepho

SIMPC8313 board: fix out of tree building.

2009-03-09T09:51:39Z

Fix typo in makefile which broke out of tree builds. Also use expolicit "rm" instead of "ln -sf" which is known to be unreliable. Signed-off-by: Wolfgang Denk

mpc83xx: fix undefined reference to `flush_cache' error in simpc8313 build

2009-01-28T09:00:56Z

extend commit c70564e6b1bd08f3230182392238907f3531a87e "NAND: Fix cache and memory inconsistency issue" to add the cache.o dependency to the simpc8313 build and fix this: ...Large Page NAND...Configuring for SIMPC8313 board... nand_boot_fsl_elbc.o: In function `nand_boot': nand_spl/board/sheldon/simpc8313/nand_boot_fsl_elbc.c:150: undefined reference to `flush_cache' make[1]: *** [/home/r1aaha/git/u-boot-mpc83xx/nand_spl/u-boot-spl] Error 1 make: *** [nand_spl] Error 2 Signed-off-by: Kim Phillips

Merge branch 'next'

2009-01-23T23:48:24Z

mpc83xx: New board support for SIMPC8313

2009-01-23T17:31:18Z

This patch will create a new board, SIMPC8313, from Sheldon Instruments. This board boots from NAND devices and is configureable for either large or small page devices. The board supports non-soldered DDR2, one ethernet port, a Marvell 88E1118 PHY, and PCI host support. The board also has a FPGA connected to the eLBC providing glue logic to a TMS320C67xx DSP. Signed-off-by: Ron Madrid Signed-off-by: Kim Phillips