u-boot.git/nand_spl, branch v1.3.0

[ppc4xx] Individual handling of sdram.c for bamboo_nand build

2007-09-11T10:57:52+00:00

Bamboo has a file sdram.c which needs special treatment when building in
separate directory. It has to be linked to build directory otherwise it is
not seen.

Signed-off-by: Grzegorz Bernacki

[ppc4xx] Fix problem with NAND booting on AMCC Acadia

2007-06-19T14:42:31+00:00

The latest changes showed a problem with the location of the NAND-SPL
image in the OCM and the init-data area (incl. cache). This patch
fixes this problem.

Signed-off-by: Stefan Roese

ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval board

2007-06-06T09:42:13+00:00

This patch adds NAND booting support for the AMCC Acadia eval board.

Please make sure to configure jumper J7 to position 2-3 when booting
from NOR, and to position 1-2 when booting for NAND.

I also added a board command to configure the I2C bootstrap EEPROM
values. Right now only 267MHz is support for booting either via NOR
or NAND FLASH. Here the usage:

=> bootstrap 267 nor	;to configure the board for 267MHz NOR booting
=> bootstrap 267 nand	;to configure the board for 267MHz NNAND booting

Signed-off-by: Stefan Roese

Merge with /home/stefan/git/u-boot/bamboo-nand

2007-06-01T14:15:34+00:00

ppc4xx: Update Sequoia NAND booting support with ECC

2007-06-01T13:29:04+00:00

Signed-off-by: Stefan Roese

ppc4xx: Add NAND booting support for AMCC Bamboo (440EP) eval board

2007-06-01T13:27:11+00:00

This patch adds NAND booting support for the AMCC Bamboo eval board.
Since the NAND-SPL boot image is limited to 4kbytes, this version
only supports the onboard 64MBytes of DDR. The DIMM modules can't be
supported, since the setup code for I2C DIMM autodetection and
configuration is too big for this NAND bootloader.

Signed-off-by: Stefan Roese

NAND: Add ECC support to NAND booting support in nand_spl/nand_boot.c

2007-06-01T13:23:04+00:00

The U-Boot NAND booting support is now extended to support ECC
upon loading of the NAND U-Boot image.

Tested on AMCC Sequoia (440EPx) and Bamboo (440EP).

Signed-off-by: Stefan Roese

ppc4xx: Sequoia: Remove cpu/ppc4xx/speed.c from NAND booting

2007-05-05T06:29:01+00:00

Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
for the 4k NAND boot image so define bus_frequency to 133MHz here
which is save for the refresh counter setup.

Signed-off-by: Stefan Roese

[PATCH] Speed optimization of AMCC Sequoia/Rainier DDR2 setup

2007-03-06T06:47:04+00:00

As provided by the AMCC applications team, this patch optimizes the
DDR2 setup for 166MHz bus speed. The values provided are also save
to use on a "normal" 133MHz PLB bus system. Only the refresh counter
setup has to be adjusted as done in this patch.

For this the NAND booting version had to include the "speed.c" file
from the cpu/ppc4xx directory. With this addition the NAND SPL image
will just fit into the 4kbytes of program space. gcc version 4.x as
provided with ELDK 4.x is needed to generate this optimized code.

Signed-off-by: Stefan Roese

[PATCH] Add DDR2 optimization code for Sequoia (440EPx) board

2007-01-05T09:38:05+00:00

This code will optimize the DDR2 controller setup on a board specific
basis.

Note: This code doesn't work right now on the NAND booting image for the
Sequoia board, since it doesn't fit into the 4kBytes for the SPL image.

Signed-off-by: Stefan Roese