u-boot.git/post, branch v1.3.2

Fix warnings while compilation of post/drivers/memory.c

2008-03-02T20:42:20+00:00

Fix warnings while compilation with new gcc in eldk-4.2

Signed-off-by: Anatolij Gustschin

POST: Disable cache while SPR POST

2008-03-02T20:33:51+00:00

Currently (since commit b2e2142c) u-boot crashes on
sequoia board while SPR test if CONFIG_4xx_DCACHE is
enabled. This patch disables the cache while SPR test.

Signed-off-by: Anatolij Gustschin

Fix CPU POST test failure

2008-02-21T10:25:47+00:00

The CPU POST test code (run from cpu_post_exec_31()) doesn't follow the
ABI carefully, at least the CR3, CR4, and CR5 fields of CR are clobbered
by it. The gcc-4.2 with its more aggressive optimization exposes this fact.
This patch just saves the CR value before running the test code, so allowing
it to do anything it wants with CR.

Signed-off-by: Dmitry Rakhchev 
Acked-by: Yuri Tikhonov 
--

Add attribute POST_PREREL to ECC memory POST

2008-02-06T23:22:59+00:00

Signed-off-by: Larry Johnson

ppc4xx: Refactor ECC POST for AMCC Denali core

2008-01-16T10:23:33+00:00

The ECC POST reported intermittent failures running after power-up on
the Korat PPC440EPx board.  Even when the test passed, the debugging
output occasionally reported additional unexpected ECC errors.

This refactoring has three main objectives: (1) minimize the code
executed with ECC enabled during the tests, (2) add more checking of the
results so any unexpected ECC errors would cause the test to fail, and
(3) use synchronization (only) where required by the processor.

Signed-off-by: Larry Johnson

ppc_4xx: Fix post spr.c for PPC405

2008-01-14T14:52:52+00:00

post/cpu/ppc4xx/spr.c contained a few checks for registers only present
for PPC440 and derivates processor.

Signed-off-by: Niklaus Giger

POST: Execute SPR test after relocation

2008-01-09T09:38:58+00:00

On LWMON5 we now use d-cache as init-ram and stack. The SPR POST test uses
self modifying code and this doesn't work with stack in d-cache, since
I can't move the code from d-cache to i-cache. We move the SPR test to
be executed a little later, after relocation. Then stack is located in
SDRAM and this self-modifying code is no problem anymore.

Signed-off-by: Stefan Roese

Cosmetic changes to ECC POST for AMCC Denali core

2007-12-27T18:35:35+00:00

Signed-off-by: Larry Johnson

ppc4xx: Fix compilation problem in 405 cache POST test

2007-12-27T18:35:35+00:00

Signed-off-by: Stefan Roese

ppc4xx: Fix problem in 44x cache POST routine

2007-12-27T18:35:34+00:00

As repoted by Larry Johnson, running "diag run cache" caused a crash
in U-Boot. This problem was introduced by a patch that removed the
TLB entry for the cache test after the test has completed. Since this
TLB was only setup once, a 2nd attempt to run this cache test
failed with a crash. Now this TLB entry is created every time the
routine is called.

Signed-off-by: Stefan Roese