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<title>u-boot.git/scripts/Makefile.spl, branch v2020.01-rc3</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>spl: separate SPL_FRAMEWORK config for spl and tpl</title>
<updated>2019-11-17T09:22:53+00:00</updated>
<author>
<name>Heiko Stuebner</name>
<email>heiko.stuebner@theobroma-systems.com</email>
</author>
<published>2019-07-16T08:12:02+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=22b7b860051d3f18cfd3bb9750b907174b3eee2b'/>
<id>22b7b860051d3f18cfd3bb9750b907174b3eee2b</id>
<content type='text'>
Right now enabling SPL_FRAMEWORK will also enable it for the TPL in all
cases, making the TPL bigger. There may be cases where the TPL is really
size constrained due to its underlying ram size.

Therefore introduce a new TPL_FRAMEWORK option and make the relevant
conditionals check for both. The default is set to "y if SPL_FRAMEWORK"
to mimic the previous behaviour where the TPL would always get the
SPL framework if it was enabled in SPL.

Signed-off-by: Heiko Stuebner &lt;heiko.stuebner@theobroma-systems.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
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<pre>
Right now enabling SPL_FRAMEWORK will also enable it for the TPL in all
cases, making the TPL bigger. There may be cases where the TPL is really
size constrained due to its underlying ram size.

Therefore introduce a new TPL_FRAMEWORK option and make the relevant
conditionals check for both. The default is set to "y if SPL_FRAMEWORK"
to mimic the previous behaviour where the TPL would always get the
SPL framework if it was enabled in SPL.

Signed-off-by: Heiko Stuebner &lt;heiko.stuebner@theobroma-systems.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>usb: Add Cadence USB3 host and gadget driver</title>
<updated>2019-11-06T23:24:59+00:00</updated>
<author>
<name>Vignesh Raghavendra</name>
<email>vigneshr@ti.com</email>
</author>
<published>2019-10-01T11:56:33+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7e91f6ccdc84fe5952e5c26769e65d12e5fc4733'/>
<id>7e91f6ccdc84fe5952e5c26769e65d12e5fc4733</id>
<content type='text'>
Add support for USB3 host and gadget driver. This is a direct sync of
Linux kernel Cadence USB stack that from v5.4-rc1 release.
Driver has been modified so that it compiles without errors against
U-Boot code base.
Features not required for U-Boot such as scatter-gather DMA and OTG
interrupt handling has been dropped.

Signed-off-by: Jean-Jacques Hiblot &lt;jjhiblot@ti.com&gt;
[jjhiblot@ti.com: Add PHY support]
Signed-off-by: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add support for USB3 host and gadget driver. This is a direct sync of
Linux kernel Cadence USB stack that from v5.4-rc1 release.
Driver has been modified so that it compiles without errors against
U-Boot code base.
Features not required for U-Boot such as scatter-gather DMA and OTG
interrupt handling has been dropped.

Signed-off-by: Jean-Jacques Hiblot &lt;jjhiblot@ti.com&gt;
[jjhiblot@ti.com: Add PHY support]
Signed-off-by: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>binman: x86: Separate out 16-bit reset and init code</title>
<updated>2019-10-15T14:40:02+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-08-24T13:22:49+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5e239183f62cc3740bf775e5204591cea5bf02ae'/>
<id>5e239183f62cc3740bf775e5204591cea5bf02ae</id>
<content type='text'>
At present these two sections of code are linked together into a single
2KB chunk in a single file. Some Intel SoCs like to have a FIT (Firmware
Interface Table) in the ROM and the pointer for this needs to go at
0xffffffc0 which is in the middle of these two sections.

Make use of the new 'reset' entry and change the existing 16-bit entry to
include just the 16-bit data.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
At present these two sections of code are linked together into a single
2KB chunk in a single file. Some Intel SoCs like to have a FIT (Firmware
Interface Table) in the ROM and the pointer for this needs to go at
0xffffffc0 which is in the middle of these two sections.

Make use of the new 'reset' entry and change the existing 16-bit entry to
include just the 16-bit data.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: Allow 16-bit init to be in TPL</title>
<updated>2019-05-08T05:02:13+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-04-26T03:58:53+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d68574a72da5376784cbf3a553d82c6acfcd6824'/>
<id>d68574a72da5376784cbf3a553d82c6acfcd6824</id>
<content type='text'>
At present we support having 16-bit init be in SPL or U-Boot proper, but
not TPL. Add support for this so that TPL can boot.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
At present we support having 16-bit init be in SPL or U-Boot proper, but
not TPL. Add support for this so that TPL can boot.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spl: Allow sandbox to build a device-tree file</title>
<updated>2019-05-08T04:44:07+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-04-26T03:58:38+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4fc2365ccb911a1a3401e88be702c5c42ab6386a'/>
<id>4fc2365ccb911a1a3401e88be702c5c42ab6386a</id>
<content type='text'>
At present only OF_SEPARATE is considered valid for building a device-tree
file in SPL. However sandbox uses OF_HOSTFILE instead. Update the logic to
handle this and make it easier to understand.

Note that the new logic is not quite the same as the old logic. It was
previously assumed that checking for:

   $(CONFIG_$(SPL_TPL_)OF_CONTROL)
   $(CONFIG_OF_SEPARATE)
   $(CONFIG_$(SPL_TPL_)OF_PLATDATA)

producing 'yy' meant that the first two were 'y' and the last was empty.
Strictly speaking it would be possible for any two of the three to be 'y'
and still yield the same result. However, that was not the intention of
the new logic, since OF_PLATDATA always ensures that no device-tree file
is included. So in effect the new logic is the same, with the addition of
OF_HOSTFILE as an option for OP_SEPARATE.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
At present only OF_SEPARATE is considered valid for building a device-tree
file in SPL. However sandbox uses OF_HOSTFILE instead. Update the logic to
handle this and make it easier to understand.

Note that the new logic is not quite the same as the old logic. It was
previously assumed that checking for:

   $(CONFIG_$(SPL_TPL_)OF_CONTROL)
   $(CONFIG_OF_SEPARATE)
   $(CONFIG_$(SPL_TPL_)OF_PLATDATA)

producing 'yy' meant that the first two were 'y' and the last was empty.
Strictly speaking it would be possible for any two of the three to be 'y'
and still yield the same result. However, that was not the intention of
the new logic, since OF_PLATDATA always ensures that no device-tree file
is included. So in effect the new logic is the same, with the addition of
OF_HOSTFILE as an option for OP_SEPARATE.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Makefile.spl: Move generated AT91SAM NAND image boot.bin to spl directory</title>
<updated>2019-04-09T06:28:50+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2019-04-02T08:57:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=581e711ad1216fa791bf20a3598c601af77a77b1'/>
<id>581e711ad1216fa791bf20a3598c601af77a77b1</id>
<content type='text'>
This patch moves the AT91SAM NAND booting SPL image "boot.bin" which
includes the ECC values from the root directory into the spl directory,
where all SPL related images are located.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Heiko Schocher &lt;hs@denx.de&gt;
Cc: Andreas Bießmann &lt;andreas@biessmann.org&gt;
Cc: Eugen Hristev &lt;eugen.hristev@microchip.com&gt;
Reviewed-by: Heiko Schocher &lt;hs@denx.de&gt;
Tested on the taurus board:
Tested-by: Heiko Schocher &lt;hs@denx.de&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch moves the AT91SAM NAND booting SPL image "boot.bin" which
includes the ECC values from the root directory into the spl directory,
where all SPL related images are located.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Heiko Schocher &lt;hs@denx.de&gt;
Cc: Andreas Bießmann &lt;andreas@biessmann.org&gt;
Cc: Eugen Hristev &lt;eugen.hristev@microchip.com&gt;
Reviewed-by: Heiko Schocher &lt;hs@denx.de&gt;
Tested on the taurus board:
Tested-by: Heiko Schocher &lt;hs@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: socfpga: Build sfp image only for Gen5 and Arria10 devices</title>
<updated>2019-03-21T02:31:01+00:00</updated>
<author>
<name>Dalon Westergreen</name>
<email>dalon.westergreen@intel.com</email>
</author>
<published>2019-03-20T20:15:21+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e3ada91e49848ddcd3293a737cf08e48b2d72e42'/>
<id>e3ada91e49848ddcd3293a737cf08e48b2d72e42</id>
<content type='text'>
The sfp file is only valid for Gen5 (Cyclone5 &amp; Arria5) and Arria10
devices.  The file should only be built for these devices.

Signed-off-by: Dalon Westergreen &lt;dalon.westergreen@intel.com&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The sfp file is only valid for Gen5 (Cyclone5 &amp; Arria5) and Arria10
devices.  The file should only be built for these devices.

Signed-off-by: Dalon Westergreen &lt;dalon.westergreen@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>linker: Modify linker scripts to be more generic</title>
<updated>2019-01-27T03:55:53+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2019-01-22T22:09:26+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2f41ade79e5969ebea03a7dcadbeae8e03787d7e'/>
<id>2f41ade79e5969ebea03a7dcadbeae8e03787d7e</id>
<content type='text'>
Make use of "IMAGE_MAX_SIZE" and "IMAGE_TEXT_BASE" rather than
CONFIG_SPL_MAX_SIZE and CONFIG_SPL_TEXT_BASE.  This lets us re-use the
same script for both SPL and TPL.  Add logic to scripts/Makefile.spl to
pass in the right value when preprocessing the script.

Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Cc: Jagan Teki &lt;jagan@openedev.com&gt;
Cc: Maxime Ripard &lt;maxime.ripard@bootlin.com&gt;
Cc: Andreas Bießmann &lt;andreas@biessmann.org&gt;
Cc: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Cc: Michal Simek &lt;monstr@monstr.eu&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Cc: York Sun &lt;york.sun@nxp.com&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Heiko Schocher &lt;hs@denx.de&gt;
Cc: Adam Ford &lt;aford173@gmail.com&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Tested-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Tested-by: Adam Ford &lt;aford173@gmail.com&gt; #da850evm &amp; omap3_logic_somlv
Reviewed-by: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Make use of "IMAGE_MAX_SIZE" and "IMAGE_TEXT_BASE" rather than
CONFIG_SPL_MAX_SIZE and CONFIG_SPL_TEXT_BASE.  This lets us re-use the
same script for both SPL and TPL.  Add logic to scripts/Makefile.spl to
pass in the right value when preprocessing the script.

Cc: Stefano Babic &lt;sbabic@denx.de&gt;
Cc: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Cc: Jagan Teki &lt;jagan@openedev.com&gt;
Cc: Maxime Ripard &lt;maxime.ripard@bootlin.com&gt;
Cc: Andreas Bießmann &lt;andreas@biessmann.org&gt;
Cc: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Cc: Michal Simek &lt;monstr@monstr.eu&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Cc: York Sun &lt;york.sun@nxp.com&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Heiko Schocher &lt;hs@denx.de&gt;
Cc: Adam Ford &lt;aford173@gmail.com&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Tested-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Tested-by: Adam Ford &lt;aford173@gmail.com&gt; #da850evm &amp; omap3_logic_somlv
Reviewed-by: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>PowerPC: Stop re-using CONFIG_SPL_TEXT_BASE for TPL</title>
<updated>2019-01-27T03:55:53+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2019-01-22T22:09:24+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a6d6812a212cf2ac263b23e68e6cbf719e64ac20'/>
<id>a6d6812a212cf2ac263b23e68e6cbf719e64ac20</id>
<content type='text'>
Rather than checking for CONFIG_TPL_BUILD and then re-defining
CONFIG_SPL_TEXT_BASE make use of CONFIG_TPL_TEXT_BASE directly.

Cc: York Sun &lt;york.sun@nxp.com&gt;
Cc: Po Liu &lt;po.liu@nxp.com&gt;
Cc: Qiang Zhao &lt;qiang.zhao@nxp.com&gt;
Cc: Timur Tabi &lt;timur@tabi.org&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Rather than checking for CONFIG_TPL_BUILD and then re-defining
CONFIG_SPL_TEXT_BASE make use of CONFIG_TPL_TEXT_BASE directly.

Cc: York Sun &lt;york.sun@nxp.com&gt;
Cc: Po Liu &lt;po.liu@nxp.com&gt;
Cc: Qiang Zhao &lt;qiang.zhao@nxp.com&gt;
Cc: Timur Tabi &lt;timur@tabi.org&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: zynqmp: Align u-boot-spl.bin for boot.bin creation</title>
<updated>2019-01-24T09:03:44+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2019-01-16T11:14:00+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a903dcf7dee787320d7cfee969de322ac7a30ee1'/>
<id>a903dcf7dee787320d7cfee969de322ac7a30ee1</id>
<content type='text'>
Bootrom is not capable to work with non align bootloader partition
that's why it is necessary to align it before boot.bin creation.
The patch is creating new spl/u-boot-spl-align.bin which is used only
for boot.bin.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Bootrom is not capable to work with non align bootloader partition
that's why it is necessary to align it before boot.bin creation.
The patch is creating new spl/u-boot-spl-align.bin which is used only
for boot.bin.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
