u-boot.git/tools/binman, branch v2023.10

binman: doc: Remove incomplete sentence

2023-09-29T10:56:49Z

This is the difference between version 1 and 2 of Massimo's patch: binman: doc: fix reference tag placement for Logging section v2: https://lore.kernel.org/u-boot/20230913161633.999542-1-massimo.pegorer+oss@gmail.com/ v1: https://lore.kernel.org/u-boot/20230909135235.21242-1-massimo.pegorer+oss@gmail.com/ Fixes: 0f40e23fd22 ("binman: add documentation for binman sign option") Signed-off-by: Massimo Pegorer Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass Acked-by: Massimo Pegorer

binman: Fix SyntaxWarning: invalid escape sequence '\('

2023-09-23T15:00:37Z

Reproduct warning: $ git clean -dfx $ make CROSS_COMPILE="" qemu-x86_64_defconfig $ make -j8 ... u-boot/tools/binman/etype/section.py:25: SyntaxWarning: invalid escape sequence '\(' """Entry that contains other entries Signed-off-by: Rong Tao

binman: doc: fix reference tag placement for Logging section

2023-09-16T16:17:25Z

Move BinmanLogging reference tag after section "Signing FIT container with private key in an image" and just before section "Logging". Fixes: 0f40e23fd22 ("binman: add documentation for binman sign option") Signed-off-by: Massimo Pegorer Reviewed-by: Heinrich Schuchardt

Revert "binman: Add a temporary hack for duplicate phandles"

2023-08-28T19:59:22Z

The affected boards have been fixed, so drop this hack. This reverts commit 288ae53cb73605500b7fc01e5919753c878466be. Signed-off-by: Simon Glass Acked-by: Tim Harvey

binman: ftest: Add test for xilinx-bootgen etype

2023-08-05T17:38:59Z

Add test for the 'xilinx-bootgen' etype Signed-off-by: Lukas Funke Reviewed-by: Simon Glass Allow missing bootgen tool; comment testXilinxBootgenMissing() comment: Signed-off-by: Simon Glass

binman: etype: Add xilinx-bootgen etype

2023-08-05T17:33:18Z

This adds a new etype 'xilinx-bootgen'. By using this etype it is possible to created an signed SPL (FSBL in Xilinx terms) for ZynqMP boards. The etype uses Xilinx Bootgen tools in order to transform the SPL into a bootable image and sign the image with a given primary and secondary public key. For more information to signing the FSBL please refer to the Xilinx Bootgen documentation. Here is an example of the etype in use: spl { filename = "boot.signed.bin"; xilinx-bootgen { pmufw-filename = "pmu-firmware.elf"; psk-key-name-hint = "psk0"; ssk-key-name-hint = "ssk0"; auth-params = "ppk_select=0", "spk_id=0x00000000"; u-boot-spl-nodtb { }; u-boot-spl-dtb { }; }; }; For this to work the hash of the primary public key has to be fused into the ZynqMP device and authentication (RSA_EN) has to be set. For testing purposes: if ppk hash check should be skipped one can add the property 'fsbl_config = "bh_auth_enable";' to the etype. However, this should only be used for testing(!). Signed-off-by: Lukas Funke Reviewed-by: Simon Glass

binman: btool: Add Xilinx Bootgen btool

2023-08-05T17:31:59Z

Add the Xilinx Bootgen as bintool. Xilinx Bootgen is used to create bootable SPL (FSBL in Xilinx terms) images for Zynq/ZynqMP devices. The btool creates a signed version of the SPL. Additionally to signing the key source for the decryption engine can be passend to the boot image. Signed-off-by: Lukas Funke

binman: Renumber 291 and 292 test files

2023-08-05T17:31:59Z

These have ended up with the same numbers as earlier files. Fix them. Signed-off-by: Simon Glass

binman: Add a temporary hack for duplicate phandles

2023-08-02T18:05:57Z

Three boards use a phandle in a FIT generator and the maintainer is away. For now, add a hack to allow this. Signed-off-by: Simon Glass

binman: Support templates containing phandles

2023-08-02T18:05:57Z

This provides support for phandles to be copied over from templates. This is not quite safe, since if the template is instantiated twice (i.e. in two different nodes), then duplicate phandles will be found. This will result in an error. Signed-off-by: Simon Glass