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<title>u-boot.git/tools/omap, branch v2016.03</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>Add GPL-2.0+ SPDX-License-Identifier to source files</title>
<updated>2013-07-24T13:44:38+00:00</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2013-07-08T07:37:19+00:00</published>
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<id>1a4596601fd395f3afb8f82f3f840c5e00bdd57a</id>
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Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
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Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
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</entry>
<entry>
<title>omap: Improve PLL parameter calculation tool</title>
<updated>2011-12-06T22:59:34+00:00</updated>
<author>
<name>Aneesh V</name>
<email>aneesh@ti.com</email>
</author>
<published>2011-11-21T23:38:57+00:00</published>
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<id>28a181ff81826bfa53f42c9790cc7397ef9a2dc9</id>
<content type='text'>
Improve the tool that finds multiplier and divider for PLLs:
The previous algorithm could get stuck on local maxima
and required the user to specify the tolerance. Improve
the algorithm to go through the entire search space and find
the optimal solution.

Signed-off-by: Aneesh V &lt;aneesh@ti.com&gt;
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<pre>
Improve the tool that finds multiplier and divider for PLLs:
The previous algorithm could get stuck on local maxima
and required the user to specify the tolerance. Improve
the algorithm to go through the entire search space and find
the optimal solution.

Signed-off-by: Aneesh V &lt;aneesh@ti.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>omap4: add clock support</title>
<updated>2011-08-03T10:49:19+00:00</updated>
<author>
<name>Aneesh V</name>
<email>aneesh@ti.com</email>
</author>
<published>2011-07-21T13:10:07+00:00</published>
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<id>3776801d0ae4c147cba3110f71441edefe46a02c</id>
<content type='text'>
Add support for:
1. DPLL locking
2. Initialization of clock domains and clock modules
3. Setting up the right voltage on voltage rails

This work draws upon previous work done for x-loader by:
	Santosh Shilimkar &lt;santosh.shilimkar@ti.com&gt;
	Rajendra Nayak &lt;rnayak@ti.com&gt;

Signed-off-by: Aneesh V &lt;aneesh@ti.com&gt;
Signed-off-by: Sandeep Paulraj &lt;s-paulraj@ti.com&gt;
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<pre>
Add support for:
1. DPLL locking
2. Initialization of clock domains and clock modules
3. Setting up the right voltage on voltage rails

This work draws upon previous work done for x-loader by:
	Santosh Shilimkar &lt;santosh.shilimkar@ti.com&gt;
	Rajendra Nayak &lt;rnayak@ti.com&gt;

Signed-off-by: Aneesh V &lt;aneesh@ti.com&gt;
Signed-off-by: Sandeep Paulraj &lt;s-paulraj@ti.com&gt;
</pre>
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</entry>
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