u-boot.git/tools, branch v2023.10-rc2

buildman: Drop warning about orphaned defconfigs

2023-08-05T17:39:23+00:00

Some boards use a MAINTAINERS entry to specify common files without
referencing any defconfigs. This is allowed and should not result in a
warning.

Drop the warning in this case.

Signed-off-by: Simon Glass

buildman: Exit after reading toolchain

2023-08-05T17:39:23+00:00

Recent refactoring changed buildman to continue operation after fetching
a toolchain. Fix this.

Fixes: b8680646521 ("bulidman: Move toolchain handling to a function")

Signed-off-by: Simon Glass

binman: ftest: Add test for xilinx-bootgen etype

2023-08-05T17:38:59+00:00

Add test for the 'xilinx-bootgen' etype

Signed-off-by: Lukas Funke 
Reviewed-by: Simon Glass 
Allow missing bootgen tool; comment testXilinxBootgenMissing() comment:
Signed-off-by: Simon Glass

binman: etype: Add xilinx-bootgen etype

2023-08-05T17:33:18+00:00

This adds a new etype 'xilinx-bootgen'. By using this etype it is
possible to created an signed SPL (FSBL in Xilinx terms) for
ZynqMP boards.

The etype uses Xilinx Bootgen tools in order to transform the SPL into
a bootable image and sign the image with a given primary and secondary
public key. For more information to signing the FSBL please refer to the
Xilinx Bootgen documentation.

Here is an example of the etype in use:

    spl {
        filename = "boot.signed.bin";

        xilinx-bootgen {
            pmufw-filename = "pmu-firmware.elf";
            psk-key-name-hint = "psk0";
            ssk-key-name-hint = "ssk0";
            auth-params = "ppk_select=0", "spk_id=0x00000000";

            u-boot-spl-nodtb {
            };
            u-boot-spl-dtb {
            };
        };
    };

For this to work the hash of the primary public key has to be fused
into the ZynqMP device and authentication (RSA_EN) has to be set.

For testing purposes: if ppk hash check should be skipped one can add
the property 'fsbl_config = "bh_auth_enable";' to the etype. However,
this should only be used for testing(!).

Signed-off-by: Lukas Funke 
Reviewed-by: Simon Glass

binman: btool: Add Xilinx Bootgen btool

2023-08-05T17:31:59+00:00

Add the Xilinx Bootgen as bintool. Xilinx Bootgen is used to create
bootable SPL (FSBL in Xilinx terms) images for Zynq/ZynqMP devices. The
btool creates a signed version of the SPL. Additionally to signing the
key source for the decryption engine can be passend to the boot image.

Signed-off-by: Lukas Funke

binman: Renumber 291 and 292 test files

2023-08-05T17:31:59+00:00

These have ended up with the same numbers as earlier files. Fix them.

Signed-off-by: Simon Glass

tools: mtk_image: use uint32_t for ghf header magic and version

2023-08-03T13:40:50+00:00

This patch converts magic and version fields of ghf common header
to one field with the type of uint32_t to make this header flexible
for futher updates.

Signed-off-by: Weijie Gao

binman: Add a temporary hack for duplicate phandles

2023-08-02T18:05:57+00:00

Three boards use a phandle in a FIT generator and the maintainer is
away. For now, add a hack to allow this.

Signed-off-by: Simon Glass

binman: Support templates containing phandles

2023-08-02T18:05:57+00:00

This provides support for phandles to be copied over from templates. This
is not quite safe, since if the template is instantiated twice (i.e. in
two different nodes), then duplicate phandles will be found. This will
result in an error.

Signed-off-by: Simon Glass

binman: Remove templates after use

2023-08-02T18:05:57+00:00

It is not necessary to keep templates around after they have been
processed. They can cause confusion and potentially duplicate phandles.

Remove them.

Use the same means of detecting a template node in _ReadImageDesc so that
the two places are consistent.

Signed-off-by: Simon Glass