diff options
| author | Balaji Selvanathan <[email protected]> | 2026-02-13 14:31:19 +0530 |
|---|---|---|
| committer | Casey Connolly <[email protected]> | 2026-03-24 11:34:58 +0100 |
| commit | c4169dfa1dcc2dc4876b10e1b1dc3de6b96ffd80 (patch) | |
| tree | 5c2b6eb462f7b61374b4cd3875bfd0a955d12b9e | |
| parent | c4f40d092590a7b4649d354c810114d5041f8cca (diff) | |
clk: qcom: qcs615: Add GCC_AHB2PHY_WEST_CLK clock support
Add GCC_AHB2PHY_WEST_CLK gate clock definition to the QCS615
clock driver. This clock is required for proper PHY operation
and eliminates clock-related warnings during USB initialization.
Signed-off-by: Balaji Selvanathan <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Casey Connolly <[email protected]>
| -rw-r--r-- | drivers/clk/qcom/clock-qcs615.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c index 65b8db04020..2087fc38f63 100644 --- a/drivers/clk/qcom/clock-qcs615.c +++ b/drivers/clk/qcom/clock-qcs615.c @@ -67,6 +67,7 @@ static const struct gate_clk qcs615_clks[] = { GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf054, BIT(0)), GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf058, BIT(0)), GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x8c014, BIT(0)), + GATE_CLK(GCC_AHB2PHY_WEST_CLK, 0x6a004, BIT(0)), GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT), GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT), GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT), |