ddr: altera: Add delay before writing to MBRDADDR register

Add a delay of 1ms before writing the address of the data for HIP
interface into the Responder Mailbox Read Address Register.

The UIBSSM mailbox require some time to settle down while waiting
for the MBRDADATA_VALID bit to become 1 without this delay,
specifically the board will timeout while waiting for
MBRDDATA_VALID bit to 1 after setting to 1.

This 1ms delay has been tested thoroughly and no intermittent issues
with UIBSSM mailbox communication is observed.

Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Signed-off-by: Boon Khai Ng <[email protected]>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/ddr/altera/uibssm_mailbox.c b/drivers/ddr/altera/uibssm_mailbox.c
index deef61f1178..2316e602d3a 100644
--- a/drivers/ddr/altera/uibssm_mailbox.c
+++ b/drivers/ddr/altera/uibssm_mailbox.c
@@ -243,6 +243,8 @@ static u32 uib_mailbox_read_request(u32 target_read_addr, phys_addr_t csr_addr)
 		hang();
 	}
 
+	mdelay(1);
+
 	/* Write <target read address> to chms0034 MBRDADDR */
 	debug("%s: #2 Write 0x%x to UIB_R_MBRDADDR\n", __func__, target_read_addr);
 	writel(target_read_addr, csr_addr + UIB_R_MBRDADDR);