arm64: imx8mp: Add 4G 1r DRAM timings on DH i.MX8MP DHCOM SoM

Introduce timing patch which converts 2 GiB DRAM timings to 4 GiB 1-rank
timings. This is a new configuration which carries IS43LQ32K01B DRAM part.
The 512 MiB SoM strapping that was never used is repurposed for this part.

Signed-off-by: Marek Vasut <[email protected]>

3 files changed, 142 insertions, 3 deletions

diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing.h b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h
index ef899dc0678..5dc841a7f5a 100644
--- a/board/dhelectronics/dh_imx8mp/lpddr4_timing.h
+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h
@@ -7,7 +7,7 @@
 #define __LPDDR4_TIMING_H__
 
 static const u16 dh_imx8mp_dhcom_dram_size[] = {
-	512, 1024, 1536, 2048, 3072, 4096, 6144, 8192
+	4096, 1024, 1536, 2048, 3072, 4096, 6144, 8192
 };
 
 extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32;
@@ -15,6 +15,7 @@ static __maybe_unused struct dram_timing_info *dh_imx8mp_dhcom_dram_timing =
 	&dh_imx8mp_dhcom_dram_timing_16g_x32;
 void dh_imx8mp_dhcom_dram_patch_16g_x32_to_16g_x32(void);
 void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_2r(void);
+void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_1r(void);
 
 u8 dh_get_memcfg(void);
 
diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c b/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c
index f93b3082b63..9574e920352 100644
--- a/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c
+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c
@@ -1910,3 +1910,141 @@ void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_2r(void)
 			ddr_fsp0_2d_cfg[i].val = 0x3;
 	}
 };
+
+/* Convert 2 GiB DRAM settings to 4 GiB 1-rank DRAM settings. */
+void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_1r(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(ddr_ddrc_cfg); i++) {
+		if (ddr_ddrc_cfg[i].reg == 0x3d400064)
+			ddr_ddrc_cfg[i].val = 0x6d0156;
+		if (ddr_ddrc_cfg[i].reg == 0x3d400138)
+			ddr_ddrc_cfg[i].val = 0x15d;
+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)
+		if (ddr_ddrc_cfg[i].reg == 0x3d400200)
+			ddr_ddrc_cfg[i].val = 0x1f;
+		if (ddr_ddrc_cfg[i].reg == 0x3d40020c)
+			ddr_ddrc_cfg[i].val = 0x14141400;
+#else
+		if (ddr_ddrc_cfg[i].reg == 0x3d400200)
+			ddr_ddrc_cfg[i].val = 0x17;
+#endif
+		if (ddr_ddrc_cfg[i].reg == 0x3d40021c)
+			ddr_ddrc_cfg[i].val = 0xf04;
+		if (ddr_ddrc_cfg[i].reg == 0x3d402024)
+			ddr_ddrc_cfg[i].val = 0x61a800;
+		if (ddr_ddrc_cfg[i].reg == 0x3d402064)
+			ddr_ddrc_cfg[i].val = 0x18004c;
+		if (ddr_ddrc_cfg[i].reg == 0x3d4020dc)
+			ddr_ddrc_cfg[i].val = 0x940009;
+		if (ddr_ddrc_cfg[i].reg == 0x3d402100)
+			ddr_ddrc_cfg[i].val = 0xc080609;
+		if (ddr_ddrc_cfg[i].reg == 0x3d402104)
+			ddr_ddrc_cfg[i].val = 0x3040d;
+		if (ddr_ddrc_cfg[i].reg == 0x3d402108)
+			ddr_ddrc_cfg[i].val = 0x3060a0c;
+		if (ddr_ddrc_cfg[i].reg == 0x3d402110)
+			ddr_ddrc_cfg[i].val = 0x4040204;
+		if (ddr_ddrc_cfg[i].reg == 0x3d402114)
+			ddr_ddrc_cfg[i].val = 0x2030303;
+		if (ddr_ddrc_cfg[i].reg == 0x3d402138)
+			ddr_ddrc_cfg[i].val = 0x4e;
+		if (ddr_ddrc_cfg[i].reg == 0x3d402144)
+			ddr_ddrc_cfg[i].val = 0x280014;
+		if (ddr_ddrc_cfg[i].reg == 0x3d402180)
+			ddr_ddrc_cfg[i].val = 0xc80006;
+		if (ddr_ddrc_cfg[i].reg == 0x3d402190)
+			ddr_ddrc_cfg[i].val = 0x3878202;
+		if (ddr_ddrc_cfg[i].reg == 0x3d4021b4)
+			ddr_ddrc_cfg[i].val = 0x702;
+		if (ddr_ddrc_cfg[i].reg == 0x3d403024)
+			ddr_ddrc_cfg[i].val = 0x493fe1;
+		if (ddr_ddrc_cfg[i].reg == 0x3d403064)
+			ddr_ddrc_cfg[i].val = 0x12003a;
+		if (ddr_ddrc_cfg[i].reg == 0x3d403100)
+			ddr_ddrc_cfg[i].val = 0xa070507;
+		if (ddr_ddrc_cfg[i].reg == 0x3d403104)
+			ddr_ddrc_cfg[i].val = 0x3040a;
+		if (ddr_ddrc_cfg[i].reg == 0x3d403108)
+			ddr_ddrc_cfg[i].val = 0x203070b;
+		if (ddr_ddrc_cfg[i].reg == 0x3d403110)
+			ddr_ddrc_cfg[i].val = 0x3040203;
+		if (ddr_ddrc_cfg[i].reg == 0x3d403114)
+			ddr_ddrc_cfg[i].val = 0x2030303;
+		if (ddr_ddrc_cfg[i].reg == 0x3d403138)
+			ddr_ddrc_cfg[i].val = 0x3b;
+		if (ddr_ddrc_cfg[i].reg == 0x3d403144)
+			ddr_ddrc_cfg[i].val = 0x1f0010;
+		if (ddr_ddrc_cfg[i].reg == 0x3d403180)
+			ddr_ddrc_cfg[i].val = 0x970005;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(ddr_ddrphy_cfg); i++) {
+		if (ddr_ddrphy_cfg[i].reg == 0x12002e)
+			ddr_ddrphy_cfg[i].val = 0x1;
+		if (ddr_ddrphy_cfg[i].reg == 0x22002e)
+			ddr_ddrphy_cfg[i].val = 0x1;
+		if (ddr_ddrphy_cfg[i].reg == 0x120008)
+			ddr_ddrphy_cfg[i].val = 0xc8;
+		if (ddr_ddrphy_cfg[i].reg == 0x220008)
+			ddr_ddrphy_cfg[i].val = 0x96;
+		if (ddr_ddrphy_cfg[i].reg == 0x200f0)
+			ddr_ddrphy_cfg[i].val = 0x500;
+		if (ddr_ddrphy_cfg[i].reg == 0x200f4)
+			ddr_ddrphy_cfg[i].val = 0x5555;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(ddr_fsp1_cfg); i++) {
+		if (ddr_fsp1_cfg[i].reg == 0x54002)
+			ddr_fsp1_cfg[i].val = 0x1;
+		if (ddr_fsp1_cfg[i].reg == 0x54003)
+			ddr_fsp1_cfg[i].val = 0x320;
+		if (ddr_fsp1_cfg[i].reg == 0x54019)
+			ddr_fsp1_cfg[i].val = 0x994;
+		if (ddr_fsp1_cfg[i].reg == 0x5401f)
+			ddr_fsp1_cfg[i].val = 0x994;
+		if (ddr_fsp1_cfg[i].reg == 0x54032)
+			ddr_fsp1_cfg[i].val = 0x9400;
+		if (ddr_fsp1_cfg[i].reg == 0x54033)
+			ddr_fsp1_cfg[i].val = 0xf309;
+		if (ddr_fsp1_cfg[i].reg == 0x54038)
+			ddr_fsp1_cfg[i].val = 0x9400;
+		if (ddr_fsp1_cfg[i].reg == 0x54039)
+			ddr_fsp1_cfg[i].val = 0xf309;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(ddr_fsp2_cfg); i++) {
+		if (ddr_fsp2_cfg[i].reg == 0x54002)
+			ddr_fsp2_cfg[i].val = 0x2;
+		if (ddr_fsp2_cfg[i].reg == 0x54003)
+			ddr_fsp2_cfg[i].val = 0x258;
+		if (ddr_fsp2_cfg[i].reg == 0x54019)
+			ddr_fsp2_cfg[i].val = 0x994;
+		if (ddr_fsp2_cfg[i].reg == 0x5401f)
+			ddr_fsp2_cfg[i].val = 0x994;
+		if (ddr_fsp2_cfg[i].reg == 0x54032)
+			ddr_fsp2_cfg[i].val = 0x9400;
+		if (ddr_fsp2_cfg[i].reg == 0x54033)
+			ddr_fsp2_cfg[i].val = 0xf309;
+		if (ddr_fsp2_cfg[i].reg == 0x54038)
+			ddr_fsp2_cfg[i].val = 0x9400;
+		if (ddr_fsp2_cfg[i].reg == 0x54039)
+			ddr_fsp2_cfg[i].val = 0xf309;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(ddr_phy_pie); i++) {
+		if (ddr_phy_pie[i].reg == 0x12000b)
+			ddr_phy_pie[i].val = 0xe1;
+		if (ddr_phy_pie[i].reg == 0x12000c)
+			ddr_phy_pie[i].val = 0x32;
+		if (ddr_phy_pie[i].reg == 0x12000d)
+			ddr_phy_pie[i].val = 0x1f4;
+		if (ddr_phy_pie[i].reg == 0x22000b)
+			ddr_phy_pie[i].val = 0xa8;
+		if (ddr_phy_pie[i].reg == 0x22000c)
+			ddr_phy_pie[i].val = 0x25;
+		if (ddr_phy_pie[i].reg == 0x22000d)
+			ddr_phy_pie[i].val = 0x177;
+	}
+};
diff --git a/board/dhelectronics/dh_imx8mp/spl.c b/board/dhelectronics/dh_imx8mp/spl.c
index 8b9dddab79a..aab8550023e 100644
--- a/board/dhelectronics/dh_imx8mp/spl.c
+++ b/board/dhelectronics/dh_imx8mp/spl.c
@@ -107,7 +107,7 @@ static int dh_imx8mp_board_power_init(void)
 typedef void (*patch_func_t)(void);
 
 static const patch_func_t dram_patch_fn[8] = {
-	NULL,							/* 512 MiB */
+	dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_1r,	/* 4096 MiB 1-rank */
 	NULL,							/* 1024 MiB */
 	NULL,							/* 1536 MiB */
 	dh_imx8mp_dhcom_dram_patch_16g_x32_to_16g_x32,		/* 2048 MiB */
@@ -168,7 +168,7 @@ static void dh_imx8mp_dhcom_dram_scrub_32g_x32(void)
 typedef void (*scrub_func_t)(void);
 
 static const scrub_func_t dram_scrub_fn[8] = {
-	NULL,					/* 512 MiB */
+	dh_imx8mp_dhcom_dram_scrub_32g_x32,	/* 4096 MiB 1-rank */
 	NULL,					/* 1024 MiB */
 	NULL,					/* 1536 MiB */
 	dh_imx8mp_dhcom_dram_scrub_16g_x32,	/* 2048 MiB */