diff options
| author | Dinesh Maniyam <[email protected]> | 2026-03-04 11:37:34 +0800 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-08-19 10:36:03 -0600 |
| commit | dcc4b293bcb00a9c519036129c0949e257c65e19 (patch) | |
| tree | 0807b1965b916040b4b125723bfe7752bb3782f4 | |
| parent | 3db4396fe029d38e180b0fa0eee039935c9f868b (diff) | |
arm: socfpga: Add NAND register address and data register
These are required by denali_spl.c for Arria10. Pre-set nand base and
data address will be used for spl nand read and write.
Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Dinesh Maniyam <[email protected]>
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h index b947cc07291..120cbfa23a5 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h @@ -12,6 +12,8 @@ #define SOCFPGA_SDMMC_ADDRESS 0xff808000 #define SOCFPGA_QSPIREGS_ADDRESS 0xff809000 #define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000 +#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000 +#define SOCFPGA_NANDDATA_ADDRESS 0xffb90000 #define SOCFPGA_UART1_ADDRESS 0xffc02100 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xffcfa000 #define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffcfe400 |