diff options
| author | Anton Vorontsov <[email protected]> | 2009-02-19 18:20:39 +0300 |
|---|---|---|
| committer | Kim Phillips <[email protected]> | 2009-03-05 18:13:11 -0600 |
| commit | 7e2ec1de1d2d723b59d7dd2fb85ff71b952d63af (patch) | |
| tree | 362134aa7c56b1860c8bfc286517d8a71d919c55 | |
| parent | 7e91558032a0c1932dd7f4f562f9c7cc55efc496 (diff) | |
mpc83xx: MPC837XEMDS: Initialize SerDes before negating PCIE reset signal
The SerDes initialization should be finished before negating the reset
signal according to the reference manual. This isn't an issue on real
hardware, but we'd better stick to the specifications anyway.
Suggested-by: Liu Dave <[email protected]>
Signed-off-by: Anton Vorontsov <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
| -rw-r--r-- | board/freescale/mpc837xemds/pci.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c index 31116b31ce5..29de2e77f01 100644 --- a/board/freescale/mpc837xemds/pci.c +++ b/board/freescale/mpc837xemds/pci.c @@ -115,6 +115,13 @@ skip_pci: if (PARTID_NO_E(spridr) == SPR_8379) return; + if (pex2) + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + else + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + /* Configure the clock for PCIE controller */ clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1); @@ -132,13 +139,6 @@ skip_pci: out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); - if (pex2) - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - else - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg, 0); } |