diff options
| author | Niklas Söderlund <[email protected]> | 2025-12-28 23:07:17 +0100 |
|---|---|---|
| committer | Marek Vasut <[email protected]> | 2025-12-29 20:47:53 +0100 |
| commit | 06df1a5072af74039732dee631c810dd8cd3471c (patch) | |
| tree | 60e1e40d3a5ea1d92f348f58cec93cd726dfa8b6 | |
| parent | 3147cd713ea4777b78397d935a0732e41e8a35f8 (diff) | |
clk: renesas: Do not disable realtime modules on R8A77995 D3
Later versions of the datasheet makes it clear D3 do not have any
realtime module stop control registers (RMSTPCRx). Remove the
manipulation of them from the module clock table to match this.
Suggested-by: Marek Vasut <[email protected]>
Signed-off-by: Niklas Söderlund <[email protected]>
| -rw-r--r-- | drivers/clk/renesas/r8a77995-cpg-mssr.c | 24 | ||||
| -rw-r--r-- | drivers/clk/renesas/renesas-cpg-mssr.c | 3 |
2 files changed, 14 insertions, 13 deletions
diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index 309b0aec8e2..53b098eae61 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -216,18 +216,18 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = { }; static const struct mstp_stop_table r8a77995_mstp_table[] = { - { 0x00210000, 0x0, 0x00210000, 0 }, - { 0x03e01000, 0x0, 0x03e01000, 0 }, - { 0x000e2fdc, 0x2000, 0x000e2fd8, 0 }, - { 0xc00014df, 0x400, 0xc00014df, 0 }, - { 0x80000004, 0x80, 0x80000004, 0 }, - { 0x40d20004, 0x0, 0x40d20004, 0 }, - { 0x08c0008c, 0x0, 0x08c0008c, 0 }, - { 0x09941c18, 0x0, 0x09941c18, 0 }, - { 0x00801087, 0x0, 0x00801087, 0 }, - { 0xf143dfc0, 0x0, 0xf143dfc0, 0 }, - { 0x063e1820, 0x0, 0x063e1820, 0 }, - { 0x00000000, 0x0, 0x00000000, 0 }, + { 0x00210000, 0x0, 0, 0 }, + { 0x03e01000, 0x0, 0, 0 }, + { 0x000e2fdc, 0x2000, 0, 0 }, + { 0xc00014df, 0x400, 0, 0 }, + { 0x80000004, 0x80, 0, 0 }, + { 0x40d20004, 0x0, 0, 0 }, + { 0x08c0008c, 0x0, 0, 0 }, + { 0x09941c18, 0x0, 0, 0 }, + { 0x00801087, 0x0, 0, 0 }, + { 0xf143dfc0, 0x0, 0, 0 }, + { 0x063e1820, 0x0, 0, 0 }, + { 0x00000000, 0x0, 0, 0 }, }; static const void *r8a77995_get_pll_config(const u32 cpg_mode) diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index 39ff4541c1e..4b07dbb3277 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -127,7 +127,8 @@ int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info) info->mstp_table[i].sdis, info->mstp_table[i].sen); - if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) + if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4 || + renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77995) continue; clrsetbits_le32(base + RMSTPCR(i), |