Merge tag 'qcom-2024.04-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-snapdragon

Qualcomm architecture changes:

* Move clock and pinctrl drivers out of mach-snapdragon
* Various clock driver improvements
* Convert PMIC power/reset key driver to use the button API
* Preparetory work for migrating to upstream DT

38 files changed, 140 insertions, 1949 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2d4458b7b56..9e73b69f1e1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -776,6 +776,8 @@ config ARCH_IPQ40XX
 	select CLK
 	select SMEM
 	select OF_CONTROL
+	select CLK_QCOM_IPQ4019
+	select PINCTRL_QCOM_IPQ4019
 	imply CMD_DM
 
 config ARCH_KEYSTONE
@@ -1076,6 +1078,7 @@ config ARCH_SNAPDRAGON
 	select DM
 	select DM_GPIO
 	select DM_SERIAL
+	select DM_RESET
 	select GPIO_EXTRA_HEADER
 	select MSM_SMEM
 	select OF_CONTROL
diff --git a/arch/arm/dts/dragonboard410c-uboot.dtsi b/arch/arm/dts/dragonboard410c-uboot.dtsi
index 3b0bd0ed0a1..cec64bf80f9 100644
--- a/arch/arm/dts/dragonboard410c-uboot.dtsi
+++ b/arch/arm/dts/dragonboard410c-uboot.dtsi
@@ -42,14 +42,3 @@
 		gpios = <&pm8916_gpios 3 0>;
 	};
 };
-
-
-&pm8916_pon {
-	key_vol_down {
-		gpios = <&pm8916_pon 1 0>;
-	};
-
-	key_power {
-		gpios = <&pm8916_pon 0 0>;
-	};
-};
diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index 9230dd3fd96..6a4e3ccf17b 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -147,20 +147,31 @@
 				#address-cells = <0x1>;
 				#size-cells = <0x1>;
 
-				pm8916_pon: pm8916_pon@800 {
-					compatible = "qcom,pm8916-pwrkey";
-					reg = <0x800 0x96>;
-					#gpio-cells = <2>;
-					gpio-controller;
+				pon@800 {
+					compatible = "qcom,pm8916-pon";
+					reg = <0x800 0x100>;
+					mode-bootloader = <0x2>;
+					mode-recovery = <0x1>;
+
+					pwrkey {
+						compatible = "qcom,pm8941-pwrkey";
+						debounce = <15625>;
+						bias-pull-up;
+					};
+
+					pm8916_resin: resin {
+						compatible = "qcom,pm8941-resin";
+						debounce = <15625>;
+						bias-pull-up;
+					};
 				};
 
 				pm8916_gpios: pm8916_gpios@c000 {
 					compatible = "qcom,pm8916-gpio";
 					reg = <0xc000 0x400>;
 					gpio-controller;
-					gpio-count = <4>;
+					gpio-ranges = <&pm8916_gpios 0 0 4>;
 					#gpio-cells = <2>;
-					gpio-bank-name="pmic";
 				};
 			};
 
diff --git a/arch/arm/dts/dragonboard820c-uboot.dtsi b/arch/arm/dts/dragonboard820c-uboot.dtsi
index 457728a43ec..d93c7c1fbde 100644
--- a/arch/arm/dts/dragonboard820c-uboot.dtsi
+++ b/arch/arm/dts/dragonboard820c-uboot.dtsi
@@ -30,15 +30,3 @@
 		};
 	};
 };
-
-&pm8994_pon {
-	key_vol_down {
-		gpios = <&pm8994_pon 1 0>;
-		label = "key_vol_down";
-	};
-
-	key_power {
-		gpios = <&pm8994_pon 0 0>;
-		label = "key_power";
-	};
-};
diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts
index ad201d48749..146a0af8aaf 100644
--- a/arch/arm/dts/dragonboard820c.dts
+++ b/arch/arm/dts/dragonboard820c.dts
@@ -109,21 +109,31 @@
 				#address-cells = <0x1>;
 				#size-cells = <0x1>;
 
-				pm8994_pon: pm8994_pon@800 {
-					compatible = "qcom,pm8994-pwrkey";
-					reg = <0x800 0x96>;
-					#gpio-cells = <2>;
-					gpio-controller;
-					gpio-bank-name="pm8994_key.";
+				pm8994_pon: pon@800 {
+					compatible = "qcom,pm8916-pon";
+					reg = <0x800 0x100>;
+					mode-bootloader = <0x2>;
+					mode-recovery = <0x1>;
+
+					pwrkey {
+						compatible = "qcom,pm8941-pwrkey";
+						debounce = <15625>;
+						bias-pull-up;
+					};
+
+					pm8994_resin: resin {
+						compatible = "qcom,pm8941-resin";
+						debounce = <15625>;
+						bias-pull-up;
+					};
 				};
 
 				pm8994_gpios: pm8994_gpios@c000 {
 					compatible = "qcom,pm8994-gpio";
 					reg = <0xc000 0x400>;
 					gpio-controller;
-					gpio-count = <24>;
+					gpio-ranges = <&pm8994_gpios 0 0 22>;
 					#gpio-cells = <2>;
-					gpio-bank-name="pm8994.";
 				};
 			};
 
diff --git a/arch/arm/dts/dragonboard845c-uboot.dtsi b/arch/arm/dts/dragonboard845c-uboot.dtsi
index 7106db8a734..775f45c0149 100644
--- a/arch/arm/dts/dragonboard845c-uboot.dtsi
+++ b/arch/arm/dts/dragonboard845c-uboot.dtsi
@@ -19,19 +19,8 @@
 			bootph-all;
 		};
 
-		pinctrl_north@3900000 {
+		pinctrl@3400000 {
 			bootph-all;
 		};
 	};
 };
-
-&pm8998_pon {
-	key_vol_down {
-		gpios = <&pm8998_pon 1 0>;
-		label = "key_vol_down";
-	};
-	key_power {
-		gpios = <&pm8998_pon 0 0>;
-		label = "key_power";
-	};
-};
diff --git a/arch/arm/dts/dragonboard845c.dts b/arch/arm/dts/dragonboard845c.dts
index b4f057ac653..054f253eb32 100644
--- a/arch/arm/dts/dragonboard845c.dts
+++ b/arch/arm/dts/dragonboard845c.dts
@@ -41,4 +41,8 @@
 	};
 };
 
+&pm8998_resin {
+	status = "okay";
+};
+
 #include "dragonboard845c-uboot.dtsi"
diff --git a/arch/arm/dts/qcom-ipq4019.dtsi b/arch/arm/dts/qcom-ipq4019.dtsi
index 0850ae56e9a..f9489e42ea2 100644
--- a/arch/arm/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/dts/qcom-ipq4019.dtsi
@@ -66,14 +66,6 @@
 			status = "disabled";
 		};
 
-		reset: gcc-reset@1800000 {
-			compatible = "qcom,gcc-reset-ipq4019";
-			reg = <0x1800000 0x60000>;
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-			bootph-all;
-		};
-
 		soc_gpios: pinctrl@1000000 {
 			compatible = "qcom,ipq4019-pinctrl";
 			reg = <0x1000000 0x300000>;
@@ -136,7 +128,7 @@
 			#phy-cells = <0>;
 			reg = <0x9a000 0x800>;
 			reg-names = "phy_base";
-			resets = <&reset USB3_UNIPHY_PHY_ARES>;
+			resets = <&gcc USB3_UNIPHY_PHY_ARES>;
 			reset-names = "por_rst";
 			status = "disabled";
 		};
@@ -146,7 +138,7 @@
 			#phy-cells = <0>;
 			reg = <0xa6000 0x40>;
 			reg-names = "phy_base";
-			resets = <&reset USB3_HSPHY_POR_ARES>, <&reset USB3_HSPHY_S_ARES>;
+			resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
 			reset-names = "por_rst", "srif_rst";
 			status = "disabled";
 		};
@@ -179,7 +171,7 @@
 			#phy-cells = <0>;
 			reg = <0xa8000 0x40>;
 			reg-names = "phy_base";
-			resets = <&reset USB2_HSPHY_POR_ARES>, <&reset USB2_HSPHY_S_ARES>;
+			resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
 			reset-names = "por_rst", "srif_rst";
 			status = "disabled";
 		};
diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts
index 8d7893c1169..07bf7dd0b32 100644
--- a/arch/arm/dts/qcs404-evb.dts
+++ b/arch/arm/dts/qcs404-evb.dts
@@ -208,11 +208,6 @@
 			#address-cells = <0x1>;
 			#size-cells = <0x0>;
 			#clock-cells = <1>;
-		};
-
-		reset: gcc-reset@1800000 {
-			compatible = "qcom,gcc-reset-qcs404";
-			reg = <0x1800000 0x80000>;
 			#reset-cells = <1>;
 		};
 
@@ -245,8 +240,8 @@
 			clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
 				 <&gcc GCC_USB3_PHY_PIPE_CLK>;
 			clock-names = "ahb", "pipe";
-			resets = <&reset GCC_USB3_PHY_BCR>,
-				 <&reset GCC_USB3PHY_PHY_BCR>;
+			resets = <&gcc GCC_USB3_PHY_BCR>,
+				 <&gcc GCC_USB3PHY_PHY_BCR>;
 			reset-names = "com", "phy";
 		};
 
@@ -257,8 +252,8 @@
 			clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
 				 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 			clock-names = "ahb", "sleep";
-			resets = <&reset GCC_USB_HS_PHY_CFG_AHB_BCR>,
-				 <&reset GCC_USB2A_PHY_BCR>;
+			resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
+				 <&gcc GCC_USB2A_PHY_BCR>;
 			reset-names = "phy", "por";
 		};
 
@@ -269,8 +264,8 @@
 			clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
 				 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 			clock-names = "ahb", "sleep";
-			resets = <&reset GCC_QUSB2_PHY_BCR>,
-				 <&reset GCC_USB2_HS_PHY_ONLY_BCR>;
+			resets = <&gcc GCC_QUSB2_PHY_BCR>,
+				 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
 			reset-names = "phy", "por";
 		};
 
@@ -335,7 +330,7 @@
 				 <&gcc GCC_ETH_PTP_CLK>,
 				 <&gcc GCC_ETH_RGMII_CLK>;
 
-			resets = <&reset GCC_EMAC_BCR>;
+			resets = <&gcc GCC_EMAC_BCR>;
 			reset-names = "emac";
 
 			snps,tso;
@@ -367,9 +362,10 @@
 
 		spmi@200f000 {
 			compatible = "qcom,spmi-pmic-arb";
-			reg = <0x200f000 0x1000
-			       0x2400000 0x400000
-			       0x2c00000 0x400000>;
+			reg = <0x200f000 0x001000>,
+			      <0x2400000 0x800000>,
+			      <0x2c00000 0x800000>;
+			reg-names = "core", "chnls", "obsrvr";
 			#address-cells = <0x1>;
 			#size-cells = <0x1>;
 
@@ -383,9 +379,8 @@
 					compatible = "qcom,pms405-gpio";
 					reg = <0xc000 0x400>;
 					gpio-controller;
-					gpio-count = <12>;
+					gpio-ranges = <&pms405_gpios 0 0 12>;
 					#gpio-cells = <2>;
-					gpio-bank-name="pmic";
 				};
 			};
 		};
diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
index 3b86b9328fc..96c9749a52c 100644
--- a/arch/arm/dts/sdm845.dtsi
+++ b/arch/arm/dts/sdm845.dtsi
@@ -26,23 +26,13 @@
 			#power-domain-cells = <1>;
 		};
 
-		gpio_north: gpio_north@3900000 {
-			#gpio-cells = <2>;
-			compatible = "qcom,sdm845-pinctrl";
-			reg = <0x3900000 0x400000>;
-			gpio-count = <150>;
-			gpio-controller;
-			gpio-ranges = <&gpio_north 0 0 150>;
-			gpio-bank-name = "soc_north.";
-		};
-
-		tlmm_north: pinctrl_north@3900000 {
+		tlmm: pinctrl@3400000 {
 			compatible = "qcom,sdm845-pinctrl";
-			reg = <0x3900000 0x400000>;
+			reg = <0x3400000 0xc00000>;
 			gpio-count = <150>;
 			gpio-controller;
 			#gpio-cells = <2>;
-			gpio-ranges = <&tlmm_north 0 0 150>;
+			gpio-ranges = <&tlmm 0 0 150>;
 
 			/* DEBUG UART */
 			qup_uart9: qup-uart9-default {
@@ -73,7 +63,7 @@
 			reg = <0xc440000 0x1100>,
 			      <0xc600000 0x2000000>,
 			      <0xe600000 0x100000>;
-			reg-names = "cnfg", "core", "obsrvr";
+			reg-names = "core", "chnls", "obsrvr";
 			#address-cells = <0x1>;
 			#size-cells = <0x1>;
 
@@ -88,21 +78,33 @@
 				#address-cells = <0x1>;
 				#size-cells = <0x1>;
 
-				pm8998_pon: pm8998_pon@800 {
-					compatible = "qcom,pm8998-pwrkey";
+				pm8998_pon: pon@800 {
+					compatible = "qcom,pm8998-pon";
+
 					reg = <0x800 0x100>;
-					#gpio-cells = <2>;
-					gpio-controller;
-					gpio-bank-name = "pm8998_key.";
+					mode-bootloader = <0x2>;
+					mode-recovery = <0x1>;
+
+					pm8998_pwrkey: pwrkey {
+						compatible = "qcom,pm8941-pwrkey";
+						debounce = <15625>;
+						bias-pull-up;
+					};
+
+					pm8998_resin: resin {
+						compatible = "qcom,pm8941-resin";
+						debounce = <15625>;
+						bias-pull-up;
+						status = "disabled";
+					};
 				};
 
 				pm8998_gpios: pm8998_gpios@c000 {
 					compatible = "qcom,pm8998-gpio";
 					reg = <0xc000 0x1a00>;
 					gpio-controller;
-					gpio-count = <21>;
+					gpio-ranges = <&pm8998_gpios 0 0 26>;
 					#gpio-cells = <2>;
-					gpio-bank-name = "pm8998.";
 				};
 			};
 
diff --git a/arch/arm/dts/starqltechn-uboot.dtsi b/arch/arm/dts/starqltechn-uboot.dtsi
index d81a22ffe49..55c6d18412b 100644
--- a/arch/arm/dts/starqltechn-uboot.dtsi
+++ b/arch/arm/dts/starqltechn-uboot.dtsi
@@ -19,22 +19,9 @@
 		clock-controller@100000 {
 			bootph-all;
 		};
-		gpio_north@3900000 {
-			bootph-all;
-		};
-		pinctrl_north@3900000 {
+		pinctrl@3400000 {
 			bootph-all;
 		};
 	};
 };
 
-&pm8998_pon {
-	key_vol_down {
-		gpios = <&pm8998_pon 1 0>;
-		label = "key_vol_down";
-	};
-	key_power {
-		gpios = <&pm8998_pon 0 0>;
-		label = "key_power";
-	};
-};
diff --git a/arch/arm/dts/starqltechn.dts b/arch/arm/dts/starqltechn.dts
index eec51d165f9..0842e19adb6 100644
--- a/arch/arm/dts/starqltechn.dts
+++ b/arch/arm/dts/starqltechn.dts
@@ -45,35 +45,23 @@
 		format = "a8r8g8b8";
 	};
 
-	gpio-keys {
-		compatible = "gpio-keys";
-
-		key-pwr {
-			label = "Power";
-			linux,code = <KEY_ENTER>;
-			gpios = <&pm8998_pon 0 GPIO_ACTIVE_LOW>;
-		};
-
-		key-vol-down {
-			label = "Volume Down";
-			linux,code = <KEY_DOWN>;
-			gpios = <&pm8998_pon 1 GPIO_ACTIVE_LOW>;
-		};
-	};
-
 	soc: soc {
 		serial@a84000 {
 			status = "okay";
 		};
+	};
+};
 
-		pinctrl_north@3900000 {
-			muic_i2c: muic_i2c {
-				pins = "GPIO_33", "GPIO_34";
-				drive-strength = <0x2>;
-				function = "gpio";
-				bias-disable;
-			};
-		};
+&pm8998_resin {
+	status = "okay";
+};
+
+&tlmm {
+	muic_i2c: muic-i2c-n {
+		pins = "GPIO_33", "GPIO_34";
+		drive-strength = <0x2>;
+		function = "gpio";
+		bias-disable;
 	};
 };
 
diff --git a/arch/arm/mach-ipq40xx/Makefile b/arch/arm/mach-ipq40xx/Makefile
deleted file mode 100644
index 08a65b8854d..00000000000
--- a/arch/arm/mach-ipq40xx/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2019 Sartura Ltd.
-#
-# Author: Robert Marko <[email protected]>
-
-obj-y += clock-ipq4019.o
-obj-y += pinctrl-snapdragon.o
-obj-y += pinctrl-ipq4019.o
diff --git a/arch/arm/mach-ipq40xx/clock-ipq4019.c b/arch/arm/mach-ipq40xx/clock-ipq4019.c
deleted file mode 100644
index c1d5c4ecdd8..00000000000
--- a/arch/arm/mach-ipq40xx/clock-ipq4019.c
+++ /dev/null
@@ -1,88 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Clock drivers for Qualcomm IPQ40xx
- *
- * Copyright (c) 2020 Sartura Ltd.
- *
- * Author: Robert Marko <[email protected]>
- *
- */
-
-#include <clk-uclass.h>
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-
-#include <dt-bindings/clock/qcom,ipq4019-gcc.h>
-
-struct msm_clk_priv {
-	phys_addr_t base;
-};
-
-ulong msm_set_rate(struct clk *clk, ulong rate)
-{
-	switch (clk->id) {
-	case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/
-		/* This clock is already initialized by SBL1 */
-		return 0;
-	default:
-		return -EINVAL;
-	}
-}
-
-static int msm_clk_probe(struct udevice *dev)
-{
-	struct msm_clk_priv *priv = dev_get_priv(dev);
-
-	priv->base = dev_read_addr(dev);
-	if (priv->base == FDT_ADDR_T_NONE)
-		return -EINVAL;
-
-	return 0;
-}
-
-static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
-{
-	return msm_set_rate(clk, rate);
-}
-
-static int msm_enable(struct clk *clk)
-{
-	switch (clk->id) {
-	case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/
-		/* This clock is already initialized by SBL1 */
-		return 0;
-	case GCC_PRNG_AHB_CLK: /*PRNG*/
-		/* This clock is already initialized by SBL1 */
-		return 0;
-	case GCC_USB3_MASTER_CLK:
-	case GCC_USB3_SLEEP_CLK:
-	case GCC_USB3_MOCK_UTMI_CLK:
-	case GCC_USB2_MASTER_CLK:
-	case GCC_USB2_SLEEP_CLK:
-	case GCC_USB2_MOCK_UTMI_CLK:
-		/* These clocks is already initialized by SBL1 */
-		return 0;
-	default:
-		return -EINVAL;
-	}
-}
-
-static struct clk_ops msm_clk_ops = {
-	.set_rate = msm_clk_set_rate,
-	.enable = msm_enable,
-};
-
-static const struct udevice_id msm_clk_ids[] = {
-	{ .compatible = "qcom,gcc-ipq4019" },
-	{ }
-};
-
-U_BOOT_DRIVER(clk_msm) = {
-	.name		= "clk_msm",
-	.id		= UCLASS_CLK,
-	.of_match	= msm_clk_ids,
-	.ops		= &msm_clk_ops,
-	.priv_auto	= sizeof(struct msm_clk_priv),
-	.probe		= msm_clk_probe,
-};
diff --git a/arch/arm/mach-ipq40xx/pinctrl-ipq4019.c b/arch/arm/mach-ipq40xx/pinctrl-ipq4019.c
deleted file mode 100644
index 3e365f8cc86..00000000000
--- a/arch/arm/mach-ipq40xx/pinctrl-ipq4019.c
+++ /dev/null
@@ -1,54 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Qualcomm IPQ40xx pinctrl
- *
- * Copyright (c) 2019 Sartura Ltd.
- *
- * Author: Robert Marko <[email protected]>
- */
-
-#include "pinctrl-snapdragon.h"
-#include <common.h>
-
-#define MAX_PIN_NAME_LEN 32
-static char pin_name[MAX_PIN_NAME_LEN];
-
-static const struct pinctrl_function msm_pinctrl_functions[] = {
-	{"gpio", 0},
-	{"blsp_uart0_0", 1}, /* Only for GPIO:16,17 */
-	{"blsp_uart0_1", 2}, /* Only for GPIO:60,61 */
-	{"blsp_uart1", 1},
-	{"blsp_spi0_0", 1}, /* Only for GPIO:12,13,14,15 */
-	{"blsp_spi0_1", 2}, /* Only for GPIO:54,55,56,57 */
-	{"blsp_spi1", 2},
-	{"mdio_0", 1}, /* Only for GPIO6 */
-	{"mdio_1", 2}, /* Only for GPIO53 */
-	{"mdc_0", 1}, /* Only for GPIO7 */
-	{"mdc_1", 2}, /* Only for GPIO52 */
-};
-
-static const char *ipq4019_get_function_name(struct udevice *dev,
-					     unsigned int selector)
-{
-	return msm_pinctrl_functions[selector].name;
-}
-
-static const char *ipq4019_get_pin_name(struct udevice *dev,
-					unsigned int selector)
-{
-	snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
-	return pin_name;
-}
-
-static unsigned int ipq4019_get_function_mux(unsigned int selector)
-{
-	return msm_pinctrl_functions[selector].val;
-}
-
-struct msm_pinctrl_data ipq4019_data = {
-	.pin_count = 100,
-	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
-	.get_function_name = ipq4019_get_function_name,
-	.get_function_mux = ipq4019_get_function_mux,
-	.get_pin_name = ipq4019_get_pin_name,
-};
diff --git a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c
deleted file mode 100644
index 036fec93d72..00000000000
--- a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c
+++ /dev/null
@@ -1,166 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * TLMM driver for Qualcomm IPQ40xx
- *
- * (C) Copyright 2018 Ramon Fried <[email protected]>
- *
- * Copyright (c) 2020 Sartura Ltd.
- *
- * Author: Robert Marko <[email protected]>
- *
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <dm/device_compat.h>
-#include <dm/lists.h>
-#include <dm/pinctrl.h>
-#include <linux/bitops.h>
-#include "pinctrl-snapdragon.h"
-
-struct msm_pinctrl_priv {
-	phys_addr_t base;
-	struct msm_pinctrl_data *data;
-};
-
-#define GPIO_CONFIG_OFFSET(x)         ((x) * 0x1000)
-#define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
-#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
-#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
-#define TLMM_GPIO_DISABLE BIT(9)
-
-static const struct pinconf_param msm_conf_params[] = {
-	{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 },
-	{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
-	{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 2 },
-};
-
-static int msm_get_functions_count(struct udevice *dev)
-{
-	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
-	return priv->data->functions_count;
-}
-
-static int msm_get_pins_count(struct udevice *dev)
-{
-	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
-	return priv->data->pin_count;
-}
-
-static const char *msm_get_function_name(struct udevice *dev,
-					 unsigned int selector)
-{
-	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
-	return priv->data->get_function_name(dev, selector);
-}
-
-static int msm_pinctrl_probe(struct udevice *dev)
-{
-	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
-	priv->base = devfdt_get_addr(dev);
-	priv->data = (struct msm_pinctrl_data *)dev->driver_data;
-
-	return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
-}
-
-static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector)
-{
-	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
-	return priv->data->get_pin_name(dev, selector);
-}
-
-static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
-			  unsigned int func_selector)
-{
-	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
-	clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
-			TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
-			priv->data->get_function_mux(func_selector) << 2);
-	return 0;
-}
-
-static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
-			   unsigned int param, unsigned int argument)
-{
-	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
-	switch (param) {
-	case PIN_CONFIG_DRIVE_STRENGTH:
-		clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
-				TLMM_DRV_STRENGTH_MASK, argument << 6);
-		break;
-	case PIN_CONFIG_BIAS_DISABLE:
-		clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
-			     TLMM_GPIO_PULL_MASK);
-		break;
-	case PIN_CONFIG_BIAS_PULL_UP:
-		clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
-			     TLMM_GPIO_PULL_MASK, argument);
-		break;
-	default:
-		return 0;
-	}
-
-	return 0;
-}
-
-static int msm_pinctrl_bind(struct udevice *dev)
-{
-	ofnode node = dev_ofnode(dev);
-	const char *name;
-	int ret;
-
-	ofnode_get_property(node, "gpio-controller", &ret);
-	if (ret < 0)
-		return 0;
-
-	/* Get the name of gpio node */
-	name = ofnode_get_name(node);
-	if (!name)
-		return -EINVAL;
-
-	/* Bind gpio node */
-	ret = device_bind_driver_to_node(dev, "gpio_msm",
-					 name, node, NULL);
-	if (ret)
-		return ret;
-
-	dev_dbg(dev, "bind %s\n", name);
-
-	return 0;
-}
-
-static struct pinctrl_ops msm_pinctrl_ops = {
-	.get_pins_count = msm_get_pins_count,
-	.get_pin_name = msm_get_pin_name,
-	.set_state = pinctrl_generic_set_state,
-	.pinmux_set = msm_pinmux_set,
-	.pinconf_num_params = ARRAY_SIZE(msm_conf_params),
-	.pinconf_params = msm_conf_params,
-	.pinconf_set = msm_pinconf_set,
-	.get_functions_count = msm_get_functions_count,
-	.get_function_name = msm_get_function_name,
-};
-
-static const struct udevice_id msm_pinctrl_ids[] = {
-	{ .compatible = "qcom,ipq4019-pinctrl", .data = (ulong)&ipq4019_data },
-	{ }
-};
-
-U_BOOT_DRIVER(pinctrl_snapdraon) = {
-	.name		= "pinctrl_msm",
-	.id		= UCLASS_PINCTRL,
-	.of_match	= msm_pinctrl_ids,
-	.priv_auto	= sizeof(struct msm_pinctrl_priv),
-	.ops		= &msm_pinctrl_ops,
-	.probe		= msm_pinctrl_probe,
-	.bind		= msm_pinctrl_bind,
-};
diff --git a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h
deleted file mode 100644
index b4823a309fc..00000000000
--- a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Qualcomm Pin control
- *
- * (C) Copyright 2018 Ramon Fried <[email protected]>
- *
- */
-#ifndef _PINCTRL_SNAPDRAGON_H
-#define _PINCTRL_SNAPDRAGON_H
-
-struct msm_pinctrl_data {
-	int pin_count;
-	int functions_count;
-	const char *(*get_function_name)(struct udevice *dev,
-					 unsigned int selector);
-	unsigned int (*get_function_mux)(unsigned int selector);
-	const char *(*get_pin_name)(struct udevice *dev,
-				    unsigned int selector);
-};
-
-struct pinctrl_function {
-	const char *name;
-	int val;
-};
-
-extern struct msm_pinctrl_data ipq4019_data;
-
-#endif
diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
index 2fc1521e2d3..ad667108191 100644
--- a/arch/arm/mach-snapdragon/Kconfig
+++ b/arch/arm/mach-snapdragon/Kconfig
@@ -15,6 +15,9 @@ config SPL_SYS_MALLOC_F_LEN
 config SDM845
 	bool "Qualcomm Snapdragon 845 SoC"
 	select LINUX_KERNEL_IMAGE_HEADER
+	imply CLK_QCOM_SDM845
+	imply PINCTRL_QCOM_SDM845
+	imply BUTTON_QCOM_PMIC
 
 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
 	default 0x80000000
@@ -26,6 +29,9 @@ config TARGET_DRAGONBOARD410C
 	bool "96Boards Dragonboard 410C"
 	select BOARD_LATE_INIT
 	select ENABLE_ARM_SOC_BOOT0_HOOK
+	imply CLK_QCOM_APQ8016
+	imply PINCTRL_QCOM_APQ8016
+	imply BUTTON_QCOM_PMIC
 	help
 	  Support for 96Boards Dragonboard 410C. This board complies with
 	  96Board Open Platform Specifications. Features:
@@ -39,6 +45,9 @@ config TARGET_DRAGONBOARD410C
 
 config TARGET_DRAGONBOARD820C
 	bool "96Boards Dragonboard 820C"
+	imply CLK_QCOM_APQ8096
+	imply PINCTRL_QCOM_APQ8096
+	imply BUTTON_QCOM_PMIC
 	help
 	  Support for 96Boards Dragonboard 820C. This board complies with
 	  96Board Open Platform Specifications. Features:
@@ -72,6 +81,8 @@ config TARGET_STARQLTECHN
 config TARGET_QCS404EVB
 	bool "Qualcomm Technologies, Inc. QCS404 EVB"
 	select LINUX_KERNEL_IMAGE_HEADER
+	imply CLK_QCOM_QCS404
+	imply PINCTRL_QCOM_QCS404
 	help
 	  Support for Qualcomm Technologies, Inc. QCS404 evaluation board.
 	  Features:
diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
index cbaaf23f6b5..3a3a297c176 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -2,20 +2,10 @@
 #
 # (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
 
-obj-$(CONFIG_SDM845) += clock-sdm845.o
 obj-$(CONFIG_SDM845) += sysmap-sdm845.o
 obj-$(CONFIG_SDM845) += init_sdm845.o
-obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o
 obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
-obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o
 obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
 obj-y += misc.o
-obj-y += clock-snapdragon.o
 obj-y += dram.o
-obj-y += pinctrl-snapdragon.o
-obj-y += pinctrl-apq8016.o
-obj-y += pinctrl-apq8096.o
-obj-y += pinctrl-qcs404.o
-obj-y += pinctrl-sdm845.o
-obj-$(CONFIG_TARGET_QCS404EVB) += clock-qcs404.o
 obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o
diff --git a/arch/arm/mach-snapdragon/clock-apq8016.c b/arch/arm/mach-snapdragon/clock-apq8016.c
deleted file mode 100644
index 23a37a1714d..00000000000
--- a/arch/arm/mach-snapdragon/clock-apq8016.c
+++ /dev/null
@@ -1,118 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Clock drivers for Qualcomm APQ8016
- *
- * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
- *
- * Based on Little Kernel driver, simplified
- */
-
-#include <common.h>
-#include <clk-uclass.h>
-#include <dm.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <linux/bitops.h>
-#include "clock-snapdragon.h"
-
-/* GPLL0 clock control registers */
-#define GPLL0_STATUS_ACTIVE BIT(17)
-
-static const struct bcr_regs sdc_regs[] = {
-	{
-	.cfg_rcgr = SDCC_CFG_RCGR(1),
-	.cmd_rcgr = SDCC_CMD_RCGR(1),
-	.M = SDCC_M(1),
-	.N = SDCC_N(1),
-	.D = SDCC_D(1),
-	},
-	{
-	.cfg_rcgr = SDCC_CFG_RCGR(2),
-	.cmd_rcgr = SDCC_CMD_RCGR(2),
-	.M = SDCC_M(2),
-	.N = SDCC_N(2),
-	.D = SDCC_D(2),
-	}
-};
-
-static struct pll_vote_clk gpll0_vote_clk = {
-	.status = GPLL0_STATUS,
-	.status_bit = GPLL0_STATUS_ACTIVE,
-	.ena_vote = APCS_GPLL_ENA_VOTE,
-	.vote_bit = BIT(0),
-};
-
-static struct vote_clk gcc_blsp1_ahb_clk = {
-	.cbcr_reg = BLSP1_AHB_CBCR,
-	.ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
-	.vote_bit = BIT(10),
-};
-
-/* SDHCI */
-static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
-{
-	int div = 8; /* 100MHz default */
-
-	if (rate == 200000000)
-		div = 4;
-
-	clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot));
-	/* 800Mhz/div, gpll0 */
-	clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0,
-			     CFG_CLK_SRC_GPLL0);
-	clk_enable_gpll0(priv->base, &gpll0_vote_clk);
-	clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
-
-	return rate;
-}
-
-static const struct bcr_regs uart2_regs = {
-	.cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
-	.cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
-	.M = BLSP1_UART2_APPS_M,
-	.N = BLSP1_UART2_APPS_N,
-	.D = BLSP1_UART2_APPS_D,
-};
-
-/* UART: 115200 */
-static int clk_init_uart(struct msm_clk_priv *priv)
-{
-	/* Enable AHB clock */
-	clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
-
-	/* 7372800 uart block clock @ GPLL0 */
-	clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625,
-			     CFG_CLK_SRC_GPLL0);
-
-	/* Vote for gpll0 clock */
-	clk_enable_gpll0(priv->base, &gpll0_vote_clk);
-
-	/* Enable core clk */
-	clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
-
-	return 0;
-}
-
-ulong msm_set_rate(struct clk *clk, ulong rate)
-{
-	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
-
-	switch (clk->id) {
-	case 0: /* SDC1 */
-		return clk_init_sdc(priv, 0, rate);
-		break;
-	case 1: /* SDC2 */
-		return clk_init_sdc(priv, 1, rate);
-		break;
-	case 4: /* UART2 */
-		return clk_init_uart(priv);
-		break;
-	default:
-		return 0;
-	}
-}
-
-int msm_enable(struct clk *clk)
-{
-	return 0;
-}
diff --git a/arch/arm/mach-snapdragon/clock-apq8096.c b/arch/arm/mach-snapdragon/clock-apq8096.c
deleted file mode 100644
index 66184596d56..00000000000
--- a/arch/arm/mach-snapdragon/clock-apq8096.c
+++ /dev/null
@@ -1,100 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Clock drivers for Qualcomm APQ8096
- *
- * (C) Copyright 2017 Jorge Ramirez Ortiz <[email protected]>
- *
- * Based on Little Kernel driver, simplified
- */
-
-#include <common.h>
-#include <clk-uclass.h>
-#include <dm.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <linux/bitops.h>
-#include "clock-snapdragon.h"
-
-/* GPLL0 clock control registers */
-#define GPLL0_STATUS_ACTIVE		BIT(30)
-#define APCS_GPLL_ENA_VOTE_GPLL0	BIT(0)
-
-static const struct bcr_regs sdc_regs = {
-	.cfg_rcgr = SDCC2_CFG_RCGR,
-	.cmd_rcgr = SDCC2_CMD_RCGR,
-	.M = SDCC2_M,
-	.N = SDCC2_N,
-	.D = SDCC2_D,
-};
-
-static const struct pll_vote_clk gpll0_vote_clk = {
-	.status = GPLL0_STATUS,
-	.status_bit = GPLL0_STATUS_ACTIVE,
-	.ena_vote = APCS_GPLL_ENA_VOTE,
-	.vote_bit = APCS_GPLL_ENA_VOTE_GPLL0,
-};
-
-static struct vote_clk gcc_blsp2_ahb_clk = {
-	.cbcr_reg = BLSP2_AHB_CBCR,
-	.ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
-	.vote_bit = BIT(15),
-};
-
-static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)
-{
-	int div = 3;
-
-	clk_enable_cbc(priv->base + SDCC2_AHB_CBCR);
-	clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0,
-			     CFG_CLK_SRC_GPLL0);
-	clk_enable_gpll0(priv->base, &gpll0_vote_clk);
-	clk_enable_cbc(priv->base + SDCC2_APPS_CBCR);
-
-	return rate;
-}
-
-static const struct bcr_regs uart2_regs = {
-	.cfg_rcgr = BLSP2_UART2_APPS_CFG_RCGR,
-	.cmd_rcgr = BLSP2_UART2_APPS_CMD_RCGR,
-	.M = BLSP2_UART2_APPS_M,
-	.N = BLSP2_UART2_APPS_N,
-	.D = BLSP2_UART2_APPS_D,
-};
-
-static int clk_init_uart(struct msm_clk_priv *priv)
-{
-	/* Enable AHB clock */
-	clk_enable_vote_clk(priv->base, &gcc_blsp2_ahb_clk);
-
-	/* 7372800 uart block clock @ GPLL0 */
-	clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 192, 15625,
-			     CFG_CLK_SRC_GPLL0);
-
-	/* Vote for gpll0 clock */
-	clk_enable_gpll0(priv->base, &gpll0_vote_clk);
-
-	/* Enable core clk */
-	clk_enable_cbc(priv->base + BLSP2_UART2_APPS_CBCR);
-
-	return 0;
-}
-
-ulong msm_set_rate(struct clk *clk, ulong rate)
-{
-	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
-
-	switch (clk->id) {
-	case 0: /* SDC1 */
-		return clk_init_sdc(priv, rate);
-		break;
-	case 4: /*UART2*/
-		return clk_init_uart(priv);
-	default:
-		return 0;
-	}
-}
-
-int msm_enable(struct clk *clk)
-{
-	return 0;
-}
diff --git a/arch/arm/mach-snapdragon/clock-qcs404.c b/arch/arm/mach-snapdragon/clock-qcs404.c
deleted file mode 100644
index 3357b54c30c..00000000000
--- a/arch/arm/mach-snapdragon/clock-qcs404.c
+++ /dev/null
@@ -1,237 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Clock drivers for Qualcomm QCS404
- *
- * (C) Copyright 2022 Sumit Garg <[email protected]>
- */
-
-#include <common.h>
-#include <clk-uclass.h>
-#include <dm.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <linux/bitops.h>
-#include "clock-snapdragon.h"
-
-#include <dt-bindings/clock/qcom,gcc-qcs404.h>
-
-/* GPLL0 clock control registers */
-#define GPLL0_STATUS_ACTIVE BIT(31)
-
-#define CFG_CLK_SRC_GPLL1	BIT(8)
-#define GPLL1_STATUS_ACTIVE	BIT(31)
-
-static struct vote_clk gcc_blsp1_ahb_clk = {
-	.cbcr_reg = BLSP1_AHB_CBCR,
-	.ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
-	.vote_bit = BIT(10) | BIT(5) | BIT(4),
-};
-
-static const struct bcr_regs uart2_regs = {
-	.cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
-	.cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
-	.M = BLSP1_UART2_APPS_M,
-	.N = BLSP1_UART2_APPS_N,
-	.D = BLSP1_UART2_APPS_D,
-};
-
-static const struct bcr_regs sdc_regs = {
-	.cfg_rcgr = SDCC_CFG_RCGR(1),
-	.cmd_rcgr = SDCC_CMD_RCGR(1),
-	.M = SDCC_M(1),
-	.N = SDCC_N(1),
-	.D = SDCC_D(1),
-};
-
-static struct pll_vote_clk gpll0_vote_clk = {
-	.status = GPLL0_STATUS,
-	.status_bit = GPLL0_STATUS_ACTIVE,
-	.ena_vote = APCS_GPLL_ENA_VOTE,
-	.vote_bit = BIT(0),
-};
-
-static struct pll_vote_clk gpll1_vote_clk = {
-	.status = GPLL1_STATUS,
-	.status_bit = GPLL1_STATUS_ACTIVE,
-	.ena_vote = APCS_GPLL_ENA_VOTE,
-	.vote_bit = BIT(1),
-};
-
-static const struct bcr_regs usb30_master_regs = {
-	.cfg_rcgr = USB30_MASTER_CFG_RCGR,
-	.cmd_rcgr = USB30_MASTER_CMD_RCGR,
-	.M = USB30_MASTER_M,
-	.N = USB30_MASTER_N,
-	.D = USB30_MASTER_D,
-};
-
-static const struct bcr_regs emac_regs = {
-	.cfg_rcgr = EMAC_CFG_RCGR,
-	.cmd_rcgr = EMAC_CMD_RCGR,
-	.M = EMAC_M,
-	.N = EMAC_N,
-	.D = EMAC_D,
-};
-
-static const struct bcr_regs emac_ptp_regs = {
-	.cfg_rcgr = EMAC_PTP_CFG_RCGR,
-	.cmd_rcgr = EMAC_PTP_CMD_RCGR,
-	.M = EMAC_M,
-	.N = EMAC_N,
-	.D = EMAC_D,
-};
-
-static const struct bcr_regs blsp1_qup0_i2c_apps_regs = {
-	.cmd_rcgr = BLSP1_QUP0_I2C_APPS_CMD_RCGR,
-	.cfg_rcgr = BLSP1_QUP0_I2C_APPS_CFG_RCGR,
-	/* mnd_width = 0 */
-};
-
-static const struct bcr_regs blsp1_qup1_i2c_apps_regs = {
-	.cmd_rcgr = BLSP1_QUP1_I2C_APPS_CMD_RCGR,
-	.cfg_rcgr = BLSP1_QUP1_I2C_APPS_CFG_RCGR,
-	/* mnd_width = 0 */
-};
-
-static const struct bcr_regs blsp1_qup2_i2c_apps_regs = {
-	.cmd_rcgr = BLSP1_QUP2_I2C_APPS_CMD_RCGR,
-	.cfg_rcgr = BLSP1_QUP2_I2C_APPS_CFG_RCGR,
-	/* mnd_width = 0 */
-};
-
-static const struct bcr_regs blsp1_qup3_i2c_apps_regs = {
-	.cmd_rcgr = BLSP1_QUP3_I2C_APPS_CMD_RCGR,
-	.cfg_rcgr = BLSP1_QUP3_I2C_APPS_CFG_RCGR,
-	/* mnd_width = 0 */
-};
-
-static const struct bcr_regs blsp1_qup4_i2c_apps_regs = {
-	.cmd_rcgr = BLSP1_QUP4_I2C_APPS_CMD_RCGR,
-	.cfg_rcgr = BLSP1_QUP4_I2C_APPS_CFG_RCGR,
-	/* mnd_width = 0 */
-};
-
-ulong msm_set_rate(struct clk *clk, ulong rate)
-{
-	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
-
-	switch (clk->id) {
-	case GCC_BLSP1_UART2_APPS_CLK:
-		/* UART: 115200 */
-		clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125,
-				     CFG_CLK_SRC_CXO);
-		clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
-		break;
-	case GCC_BLSP1_AHB_CLK:
-		clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
-		break;
-	case GCC_SDCC1_APPS_CLK:
-		/* SDCC1: 200MHz */
-		clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 4, 0, 0,
-				     CFG_CLK_SRC_GPLL0);
-		clk_enable_gpll0(priv->base, &gpll0_vote_clk);
-		clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));
-		break;
-	case GCC_SDCC1_AHB_CLK:
-		clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
-		break;
-	case GCC_ETH_RGMII_CLK:
-		if (rate == 250000000)
-			clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 0, 0,
-					     CFG_CLK_SRC_GPLL1);
-		else if (rate == 125000000)
-			clk_rcg_set_rate_mnd(priv->base, &emac_regs, 4, 0, 0,
-					     CFG_CLK_SRC_GPLL1);
-		else if (rate == 50000000)
-			clk_rcg_set_rate_mnd(priv->base, &emac_regs, 10, 0, 0,
-					     CFG_CLK_SRC_GPLL1);
-		else if (rate == 5000000)
-			clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 1, 50,
-					     CFG_CLK_SRC_GPLL1);
-		break;
-	default:
-		return 0;
-	}
-
-	return 0;
-}
-
-int msm_enable(struct clk *clk)
-{
-	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
-
-	switch (clk->id) {
-	case GCC_USB30_MASTER_CLK:
-		clk_enable_cbc(priv->base + USB30_MASTER_CBCR);
-		clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 4, 0, 0,
-				     CFG_CLK_SRC_GPLL0);
-		break;
-	case GCC_SYS_NOC_USB3_CLK:
-		clk_enable_cbc(priv->base + SYS_NOC_USB3_CBCR);
-		break;
-	case GCC_USB30_SLEEP_CLK:
-		clk_enable_cbc(priv->base + USB30_SLEEP_CBCR);
-		break;
-	case GCC_USB30_MOCK_UTMI_CLK:
-		clk_enable_cbc(priv->base + USB30_MOCK_UTMI_CBCR);
-		break;
-	case GCC_USB_HS_PHY_CFG_AHB_CLK:
-		clk_enable_cbc(priv->base + USB_HS_PHY_CFG_AHB_CBCR);
-		break;
-	case GCC_USB2A_PHY_SLEEP_CLK:
-		clk_enable_cbc(priv->base + USB_HS_PHY_CFG_AHB_CBCR);
-		break;
-	case GCC_ETH_PTP_CLK:
-		/* SPEED_1000: freq -> 250MHz */
-		clk_enable_cbc(priv->base + ETH_PTP_CBCR);
-		clk_enable_gpll0(priv->base, &gpll1_vote_clk);
-		clk_rcg_set_rate_mnd(priv->base, &emac_ptp_regs, 2, 0, 0,
-				     CFG_CLK_SRC_GPLL1);
-		break;
-	case GCC_ETH_RGMII_CLK:
-		/* SPEED_1000: freq -> 250MHz */
-		clk_enable_cbc(priv->base + ETH_RGMII_CBCR);
-		clk_enable_gpll0(priv->base, &gpll1_vote_clk);
-		clk_rcg_set_rate_mnd(priv->base, &emac_regs, 2, 0, 0,
-				     CFG_CLK_SRC_GPLL1);
-		break;
-	case GCC_ETH_SLAVE_AHB_CLK:
-		clk_enable_cbc(priv->base + ETH_SLAVE_AHB_CBCR);
-		break;
-	case GCC_ETH_AXI_CLK:
-		clk_enable_cbc(priv->base + ETH_AXI_CBCR);
-		break;
-	case GCC_BLSP1_AHB_CLK:
-		clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
-		break;
-	case GCC_BLSP1_QUP0_I2C_APPS_CLK:
-		clk_enable_cbc(priv->base + BLSP1_QUP0_I2C_APPS_CBCR);
-		clk_rcg_set_rate(priv->base, &blsp1_qup0_i2c_apps_regs, 0,
-				 CFG_CLK_SRC_CXO);
-		break;
-	case GCC_BLSP1_QUP1_I2C_APPS_CLK:
-		clk_enable_cbc(priv->base + BLSP1_QUP1_I2C_APPS_CBCR);
-		clk_rcg_set_rate(priv->base, &blsp1_qup1_i2c_apps_regs, 0,
-				 CFG_CLK_SRC_CXO);
-		break;
-	case GCC_BLSP1_QUP2_I2C_APPS_CLK:
-		clk_enable_cbc(priv->base + BLSP1_QUP2_I2C_APPS_CBCR);
-		clk_rcg_set_rate(priv->base, &blsp1_qup2_i2c_apps_regs, 0,
-				 CFG_CLK_SRC_CXO);
-		break;
-	case GCC_BLSP1_QUP3_I2C_APPS_CLK:
-		clk_enable_cbc(priv->base + BLSP1_QUP3_I2C_APPS_CBCR);
-		clk_rcg_set_rate(priv->base, &blsp1_qup3_i2c_apps_regs, 0,
-				 CFG_CLK_SRC_CXO);
-		break;
-	case GCC_BLSP1_QUP4_I2C_APPS_CLK:
-		clk_enable_cbc(priv->base + BLSP1_QUP4_I2C_APPS_CBCR);
-		clk_rcg_set_rate(priv->base, &blsp1_qup4_i2c_apps_regs, 0,
-				 CFG_CLK_SRC_CXO);
-		break;
-	default:
-		return 0;
-	}
-
-	return 0;
-}
diff --git a/arch/arm/mach-snapdragon/clock-sdm845.c b/arch/arm/mach-snapdragon/clock-sdm845.c
deleted file mode 100644
index d6df0365afc..00000000000
--- a/arch/arm/mach-snapdragon/clock-sdm845.c
+++ /dev/null
@@ -1,98 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Clock drivers for Qualcomm SDM845
- *
- * (C) Copyright 2017 Jorge Ramirez Ortiz <[email protected]>
- * (C) Copyright 2021 Dzmitry Sankouski <[email protected]>
- *
- * Based on Little Kernel driver, simplified
- */
-
-#include <common.h>
-#include <clk-uclass.h>
-#include <dm.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <linux/bitops.h>
-#include <dt-bindings/clock/qcom,gcc-sdm845.h>
-#include "clock-snapdragon.h"
-
-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
-
-struct freq_tbl {
-	uint freq;
-	uint src;
-	u8 pre_div;
-	u16 m;
-	u16 n;
-};
-
-static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
-	F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
-	F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
-	F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
-	F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
-	F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
-	F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
-	F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
-	F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
-	F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
-	F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
-	F(102400000, CFG_CLK_SRC_GPLL0_EVEN, 1, 128, 375),
-	F(112000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 28, 75),
-	F(117964800, CFG_CLK_SRC_GPLL0_EVEN, 1, 6144, 15625),
-	F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0),
-	F(128000000, CFG_CLK_SRC_GPLL0, 1, 16, 75),
-	{ }
-};
-
-static const struct bcr_regs uart2_regs = {
-	.cfg_rcgr = SE9_UART_APPS_CFG_RCGR,
-	.cmd_rcgr = SE9_UART_APPS_CMD_RCGR,
-	.M = SE9_UART_APPS_M,
-	.N = SE9_UART_APPS_N,
-	.D = SE9_UART_APPS_D,
-};
-
-const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate)
-{
-	if (!f)
-		return NULL;
-
-	if (!f->freq)
-		return f;
-
-	for (; f->freq; f++)
-		if (rate <= f->freq)
-			return f;
-
-	/* Default to our fastest rate */
-	return f - 1;
-}
-
-static int clk_init_uart(struct msm_clk_priv *priv, uint rate)
-{
-	const struct freq_tbl *freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate);
-
-	clk_rcg_set_rate_mnd(priv->base, &uart2_regs,
-						freq->pre_div, freq->m, freq->n, freq->src);
-
-	return 0;
-}
-
-ulong msm_set_rate(struct clk *clk, ulong rate)
-{
-	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
-
-	switch (clk->id) {
-	case GCC_QUPV3_WRAP1_S1_CLK: /*UART2*/
-		return clk_init_uart(priv, rate);
-	default:
-		return 0;
-	}
-}
-
-int msm_enable(struct clk *clk)
-{
-	return 0;
-}
diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c
deleted file mode 100644
index 0ac45dce9a9..00000000000
--- a/arch/arm/mach-snapdragon/clock-snapdragon.c
+++ /dev/null
@@ -1,181 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Clock drivers for Qualcomm APQ8016, APQ8096
- *
- * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
- *
- * Based on Little Kernel driver, simplified
- */
-
-#include <common.h>
-#include <clk-uclass.h>
-#include <dm.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <linux/bitops.h>
-#include "clock-snapdragon.h"
-
-/* CBCR register fields */
-#define CBCR_BRANCH_ENABLE_BIT  BIT(0)
-#define CBCR_BRANCH_OFF_BIT     BIT(31)
-
-extern ulong msm_set_rate(struct clk *clk, ulong rate);
-extern int msm_enable(struct clk *clk);
-
-/* Enable clock controlled by CBC soft macro */
-void clk_enable_cbc(phys_addr_t cbcr)
-{
-	setbits_le32(cbcr, CBCR_BRANCH_ENABLE_BIT);
-
-	while (readl(cbcr) & CBCR_BRANCH_OFF_BIT)
-		;
-}
-
-void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0)
-{
-	if (readl(base + gpll0->status) & gpll0->status_bit)
-		return; /* clock already enabled */
-
-	setbits_le32(base + gpll0->ena_vote, gpll0->vote_bit);
-
-	while ((readl(base + gpll0->status) & gpll0->status_bit) == 0)
-		;
-}
-
-#define BRANCH_ON_VAL (0)
-#define BRANCH_NOC_FSM_ON_VAL BIT(29)
-#define BRANCH_CHECK_MASK GENMASK(31, 28)
-
-void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk)
-{
-	u32 val;
-
-	setbits_le32(base + vclk->ena_vote, vclk->vote_bit);
-	do {
-		val = readl(base + vclk->cbcr_reg);
-		val &= BRANCH_CHECK_MASK;
-	} while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL));
-}
-
-#define APPS_CMD_RCGR_UPDATE BIT(0)
-
-/* Update clock command via CMD_RCGR */
-void clk_bcr_update(phys_addr_t apps_cmd_rcgr)
-{
-	setbits_le32(apps_cmd_rcgr, APPS_CMD_RCGR_UPDATE);
-
-	/* Wait for frequency to be updated. */
-	while (readl(apps_cmd_rcgr) & APPS_CMD_RCGR_UPDATE)
-		;
-}
-
-#define CFG_MODE_DUAL_EDGE (0x2 << 12) /* Counter mode */
-
-#define CFG_MASK 0x3FFF
-
-#define CFG_DIVIDER_MASK 0x1F
-
-/* root set rate for clocks with half integer and MND divider */
-void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
-			  int div, int m, int n, int source)
-{
-	u32 cfg;
-	/* M value for MND divider. */
-	u32 m_val = m;
-	/* NOT(N-M) value for MND divider. */
-	u32 n_val = ~((n) - (m)) * !!(n);
-	/* NOT 2D value for MND divider. */
-	u32 d_val = ~(n);
-
-	/* Program MND values */
-	writel(m_val, base + regs->M);
-	writel(n_val, base + regs->N);
-	writel(d_val, base + regs->D);
-
-	/* setup src select and divider */
-	cfg  = readl(base + regs->cfg_rcgr);
-	cfg &= ~CFG_MASK;
-	cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */
-
-	/* Set the divider; HW permits fraction dividers (+0.5), but
-	   for simplicity, we will support integers only */
-	if (div)
-		cfg |= (2 * div - 1) & CFG_DIVIDER_MASK;
-
-	if (n_val)
-		cfg |= CFG_MODE_DUAL_EDGE;
-
-	writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */
-
-	/* Inform h/w to start using the new config. */
-	clk_bcr_update(base + regs->cmd_rcgr);
-}
-
-/* root set rate for clocks with half integer and mnd_width=0 */
-void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div,
-		      int source)
-{
-	u32 cfg;
-
-	/* setup src select and divider */
-	cfg  = readl(base + regs->cfg_rcgr);
-	cfg &= ~CFG_MASK;
-	cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */
-
-	/*
-	 * Set the divider; HW permits fraction dividers (+0.5), but
-	 * for simplicity, we will support integers only
-	 */
-	if (div)
-		cfg |= (2 * div - 1) & CFG_DIVIDER_MASK;
-
-	writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */
-
-	/* Inform h/w to start using the new config. */
-	clk_bcr_update(base + regs->cmd_rcgr);
-}
-
-static int msm_clk_probe(struct udevice *dev)
-{
-	struct msm_clk_priv *priv = dev_get_priv(dev);
-
-	priv->base = dev_read_addr(dev);
-	if (priv->base == FDT_ADDR_T_NONE)
-		return -EINVAL;
-
-	return 0;
-}
-
-static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
-{
-	return msm_set_rate(clk, rate);
-}
-
-static int msm_clk_enable(struct clk *clk)
-{
-	return msm_enable(clk);
-}
-
-static struct clk_ops msm_clk_ops = {
-	.set_rate = msm_clk_set_rate,
-	.enable = msm_clk_enable,
-};
-
-static const struct udevice_id msm_clk_ids[] = {
-	{ .compatible = "qcom,gcc-msm8916" },
-	{ .compatible = "qcom,gcc-apq8016" },
-	{ .compatible = "qcom,gcc-msm8996" },
-	{ .compatible = "qcom,gcc-apq8096" },
-	{ .compatible = "qcom,gcc-sdm845" },
-	{ .compatible = "qcom,gcc-qcs404" },
-	{ }
-};
-
-U_BOOT_DRIVER(clk_msm) = {
-	.name		= "clk_msm",
-	.id		= UCLASS_CLK,
-	.of_match	= msm_clk_ids,
-	.ops		= &msm_clk_ops,
-	.priv_auto	= sizeof(struct msm_clk_priv),
-	.probe		= msm_clk_probe,
-};
diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.h b/arch/arm/mach-snapdragon/clock-snapdragon.h
deleted file mode 100644
index c90bbefa588..00000000000
--- a/arch/arm/mach-snapdragon/clock-snapdragon.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Qualcomm APQ8016, APQ8096, SDM845
- *
- * (C) Copyright 2017 Jorge Ramirez-Ortiz <[email protected]>
- */
-#ifndef _CLOCK_SNAPDRAGON_H
-#define _CLOCK_SNAPDRAGON_H
-
-#define CFG_CLK_SRC_CXO   (0 << 8)
-#define CFG_CLK_SRC_GPLL0 (1 << 8)
-#define CFG_CLK_SRC_GPLL0_EVEN (6 << 8)
-#define CFG_CLK_SRC_MASK  (7 << 8)
-
-struct pll_vote_clk {
-	uintptr_t status;
-	int status_bit;
-	uintptr_t ena_vote;
-	int vote_bit;
-};
-
-struct vote_clk {
-	uintptr_t cbcr_reg;
-	uintptr_t ena_vote;
-	int vote_bit;
-};
-struct bcr_regs {
-	uintptr_t cfg_rcgr;
-	uintptr_t cmd_rcgr;
-	uintptr_t M;
-	uintptr_t N;
-	uintptr_t D;
-};
-
-struct msm_clk_priv {
-	phys_addr_t base;
-};
-
-void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0);
-void clk_bcr_update(phys_addr_t apps_cmd_rgcr);
-void clk_enable_cbc(phys_addr_t cbcr);
-void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk);
-void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
-			  int div, int m, int n, int source);
-void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div,
-		      int source);
-
-#endif
diff --git a/arch/arm/mach-snapdragon/include/mach/gpio.h b/arch/arm/mach-snapdragon/include/mach/gpio.h
index bbc2bc16175..8dac62f870b 100644
--- a/arch/arm/mach-snapdragon/include/mach/gpio.h
+++ b/arch/arm/mach-snapdragon/include/mach/gpio.h
@@ -1,8 +1,28 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Empty gpio.h
+ * Qualcomm common pin control data.
  *
- * This file must stay as arch/arm/include/asm/gpio.h requires it.
- *
- * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
+ * Copyright (C) 2023 Linaro Ltd.
  */
+#ifndef _QCOM_GPIO_H_
+#define _QCOM_GPIO_H_
+
+#include <asm/types.h>
+#include <stdbool.h>
+
+struct msm_pin_data {
+	int pin_count;
+	const unsigned int *pin_offsets;
+};
+
+static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selector)
+{
+	u32 out = (selector * 0x1000);
+
+	if (offs)
+		return out + offs[selector];
+
+	return out;
+}
+
+#endif /* _QCOM_GPIO_H_ */
diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h
deleted file mode 100644
index d9a3b1af986..00000000000
--- a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Qualcomm APQ8916 sysmap
- *
- * (C) Copyright 2015 Mateusz Kulikowski <[email protected]>
- */
-#ifndef _MACH_SYSMAP_APQ8016_H
-#define _MACH_SYSMAP_APQ8016_H
-
-#define GICD_BASE			(0x0b000000)
-#define GICC_BASE			(0x0b002000)
-
-/* Clocks: (from CLK_CTL_BASE)  */
-#define GPLL0_STATUS			(0x2101C)
-#define APCS_GPLL_ENA_VOTE		(0x45000)
-#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004)
-
-#define SDCC_BCR(n)			((n * 0x1000) + 0x41000)
-#define SDCC_CMD_RCGR(n)		((n * 0x1000) + 0x41004)
-#define SDCC_CFG_RCGR(n)		((n * 0x1000) + 0x41008)
-#define SDCC_M(n)			((n * 0x1000) + 0x4100C)
-#define SDCC_N(n)			((n * 0x1000) + 0x41010)
-#define SDCC_D(n)			((n * 0x1000) + 0x41014)
-#define SDCC_APPS_CBCR(n)		((n * 0x1000) + 0x41018)
-#define SDCC_AHB_CBCR(n)		((n * 0x1000) + 0x4101C)
-
-/* BLSP1 AHB clock (root clock for BLSP) */
-#define BLSP1_AHB_CBCR			0x1008
-
-/* Uart clock control registers */
-#define BLSP1_UART2_BCR			(0x3028)
-#define BLSP1_UART2_APPS_CBCR		(0x302C)
-#define BLSP1_UART2_APPS_CMD_RCGR	(0x3034)
-#define BLSP1_UART2_APPS_CFG_RCGR	(0x3038)
-#define BLSP1_UART2_APPS_M		(0x303C)
-#define BLSP1_UART2_APPS_N		(0x3040)
-#define BLSP1_UART2_APPS_D		(0x3044)
-
-#endif
diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h
deleted file mode 100644
index 36a902bd929..00000000000
--- a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Qualcomm APQ8096 sysmap
- *
- * (C) Copyright 2017 Jorge Ramirez-Ortiz <[email protected]>
- */
-#ifndef _MACH_SYSMAP_APQ8096_H
-#define _MACH_SYSMAP_APQ8096_H
-
-#define TLMM_BASE_ADDR			(0x1010000)
-
-/* Strength (sdc1) */
-#define SDC1_HDRV_PULL_CTL_REG		(TLMM_BASE_ADDR + 0x0012D000)
-
-/* Clocks: (from CLK_CTL_BASE)  */
-#define GPLL0_STATUS			(0x0000)
-#define APCS_GPLL_ENA_VOTE		(0x52000)
-#define APCS_CLOCK_BRANCH_ENA_VOTE	(0x52004)
-
-#define SDCC2_BCR			(0x14000) /* block reset */
-#define SDCC2_APPS_CBCR			(0x14004) /* branch control */
-#define SDCC2_AHB_CBCR			(0x14008)
-#define SDCC2_CMD_RCGR			(0x14010)
-#define SDCC2_CFG_RCGR			(0x14014)
-#define SDCC2_M				(0x14018)
-#define SDCC2_N				(0x1401C)
-#define SDCC2_D				(0x14020)
-
-#define BLSP2_AHB_CBCR			(0x25004)
-#define BLSP2_UART2_APPS_CBCR		(0x29004)
-#define BLSP2_UART2_APPS_CMD_RCGR	(0x2900C)
-#define BLSP2_UART2_APPS_CFG_RCGR	(0x29010)
-#define BLSP2_UART2_APPS_M		(0x29014)
-#define BLSP2_UART2_APPS_N		(0x29018)
-#define BLSP2_UART2_APPS_D		(0x2901C)
-
-#endif
diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h b/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h
deleted file mode 100644
index 5768fb13775..00000000000
--- a/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Qualcomm QCS404 sysmap
- *
- * (C) Copyright 2022 Sumit Garg <[email protected]>
- */
-#ifndef _MACH_SYSMAP_QCS404_H
-#define _MACH_SYSMAP_QCS404_H
-
-#define GICD_BASE			(0x0b000000)
-#define GICC_BASE			(0x0b002000)
-
-/* Clocks: (from CLK_CTL_BASE)  */
-#define GPLL0_STATUS			(0x21000)
-#define GPLL1_STATUS			(0x20000)
-#define APCS_GPLL_ENA_VOTE		(0x45000)
-#define APCS_CLOCK_BRANCH_ENA_VOTE	(0x45004)
-
-/* BLSP1 AHB clock (root clock for BLSP) */
-#define BLSP1_AHB_CBCR			0x1008
-
-/* Uart clock control registers */
-#define BLSP1_UART2_BCR			(0x3028)
-#define BLSP1_UART2_APPS_CBCR		(0x302C)
-#define BLSP1_UART2_APPS_CMD_RCGR	(0x3034)
-#define BLSP1_UART2_APPS_CFG_RCGR	(0x3038)
-#define BLSP1_UART2_APPS_M		(0x303C)
-#define BLSP1_UART2_APPS_N		(0x3040)
-#define BLSP1_UART2_APPS_D		(0x3044)
-
-/* I2C controller clock control registerss */
-#define BLSP1_QUP0_I2C_APPS_CBCR	(0x6028)
-#define BLSP1_QUP0_I2C_APPS_CMD_RCGR	(0x602C)
-#define BLSP1_QUP0_I2C_APPS_CFG_RCGR	(0x6030)
-#define BLSP1_QUP1_I2C_APPS_CBCR	(0x2008)
-#define BLSP1_QUP1_I2C_APPS_CMD_RCGR	(0x200C)
-#define BLSP1_QUP1_I2C_APPS_CFG_RCGR	(0x2010)
-#define BLSP1_QUP2_I2C_APPS_CBCR	(0x3010)
-#define BLSP1_QUP2_I2C_APPS_CMD_RCGR	(0x3000)
-#define BLSP1_QUP2_I2C_APPS_CFG_RCGR	(0x3004)
-#define BLSP1_QUP3_I2C_APPS_CBCR	(0x4020)
-#define BLSP1_QUP3_I2C_APPS_CMD_RCGR	(0x4000)
-#define BLSP1_QUP3_I2C_APPS_CFG_RCGR	(0x4004)
-#define BLSP1_QUP4_I2C_APPS_CBCR	(0x5020)
-#define BLSP1_QUP4_I2C_APPS_CMD_RCGR	(0x5000)
-#define BLSP1_QUP4_I2C_APPS_CFG_RCGR	(0x5004)
-
-/* SD controller clock control registers */
-#define SDCC_BCR(n)			(((n) * 0x1000) + 0x41000)
-#define SDCC_CMD_RCGR(n)		(((n) * 0x1000) + 0x41004)
-#define SDCC_CFG_RCGR(n)		(((n) * 0x1000) + 0x41008)
-#define SDCC_M(n)			(((n) * 0x1000) + 0x4100C)
-#define SDCC_N(n)			(((n) * 0x1000) + 0x41010)
-#define SDCC_D(n)			(((n) * 0x1000) + 0x41014)
-#define SDCC_APPS_CBCR(n)		(((n) * 0x1000) + 0x41018)
-#define SDCC_AHB_CBCR(n)		(((n) * 0x1000) + 0x4101C)
-
-/* USB-3.0 controller clock control registers */
-#define SYS_NOC_USB3_CBCR		(0x26014)
-#define USB30_BCR			(0x39000)
-#define USB3PHY_BCR			(0x39008)
-#define USB30_MASTER_CBCR		(0x3900C)
-#define USB30_SLEEP_CBCR		(0x39010)
-#define USB30_MOCK_UTMI_CBCR		(0x39014)
-#define USB30_MOCK_UTMI_CMD_RCGR	(0x3901C)
-#define USB30_MOCK_UTMI_CFG_RCGR	(0x39020)
-#define USB30_MASTER_CMD_RCGR		(0x39028)
-#define USB30_MASTER_CFG_RCGR		(0x3902C)
-#define USB30_MASTER_M			(0x39030)
-#define USB30_MASTER_N			(0x39034)
-#define USB30_MASTER_D			(0x39038)
-#define USB2A_PHY_SLEEP_CBCR		(0x4102C)
-#define USB_HS_PHY_CFG_AHB_CBCR		(0x41030)
-
-/* ETH controller clock control registers */
-#define ETH_PTP_CBCR			(0x4e004)
-#define ETH_RGMII_CBCR			(0x4e008)
-#define ETH_SLAVE_AHB_CBCR		(0x4e00c)
-#define ETH_AXI_CBCR			(0x4e010)
-#define EMAC_PTP_CMD_RCGR		(0x4e014)
-#define EMAC_PTP_CFG_RCGR		(0x4e018)
-#define EMAC_CMD_RCGR			(0x4e01c)
-#define EMAC_CFG_RCGR			(0x4e020)
-#define EMAC_M				(0x4e024)
-#define EMAC_N				(0x4e028)
-#define EMAC_D				(0x4e02c)
-
-#endif
diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h b/arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h
deleted file mode 100644
index 7165985bcd1..00000000000
--- a/arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Qualcomm SDM845 sysmap
- *
- * (C) Copyright 2021 Dzmitry Sankouski <[email protected]>
- */
-#ifndef _MACH_SYSMAP_SDM845_H
-#define _MACH_SYSMAP_SDM845_H
-
-#define TLMM_BASE_ADDR			(0x1010000)
-
-/* Strength (sdc1) */
-#define SDC1_HDRV_PULL_CTL_REG		(TLMM_BASE_ADDR + 0x0012D000)
-
-/* Clocks: (from CLK_CTL_BASE)  */
-#define GPLL0_STATUS			(0x0000)
-#define APCS_GPLL_ENA_VOTE		(0x52000)
-#define APCS_CLOCK_BRANCH_ENA_VOTE	(0x52004)
-
-#define SDCC2_BCR			(0x14000) /* block reset */
-#define SDCC2_APPS_CBCR			(0x14004) /* branch control */
-#define SDCC2_AHB_CBCR			(0x14008)
-#define SDCC2_CMD_RCGR			(0x1400c)
-#define SDCC2_CFG_RCGR			(0x14010)
-#define SDCC2_M				(0x14014)
-#define SDCC2_N				(0x14018)
-#define SDCC2_D				(0x1401C)
-
-#define RCG2_CFG_REG			0x4
-#define M_REG			0x8
-#define N_REG			0xc
-#define D_REG			0x10
-
-#define SE9_AHB_CBCR			(0x25004)
-#define SE9_UART_APPS_CBCR		(0x29004)
-#define SE9_UART_APPS_CMD_RCGR	(0x18148)
-#define SE9_UART_APPS_CFG_RCGR	(0x1814C)
-#define SE9_UART_APPS_M		(0x18150)
-#define SE9_UART_APPS_N		(0x18154)
-#define SE9_UART_APPS_D		(0x18158)
-
-#endif
diff --git a/arch/arm/mach-snapdragon/init_sdm845.c b/arch/arm/mach-snapdragon/init_sdm845.c
index 1f885023943..067acc9a6f4 100644
--- a/arch/arm/mach-snapdragon/init_sdm845.c
+++ b/arch/arm/mach-snapdragon/init_sdm845.c
@@ -5,6 +5,7 @@
  * (C) Copyright 2021 Dzmitry Sankouski <[email protected]>
  */
 
+#include <button.h>
 #include <init.h>
 #include <env.h>
 #include <common.h>
@@ -32,46 +33,18 @@ __weak int board_init(void)
 /* Check for vol- and power buttons */
 __weak int misc_init_r(void)
 {
-	struct udevice *pon;
-	struct gpio_desc resin;
-	int node, ret;
+	struct udevice *btn;
+	int ret;
+	enum button_state_t state;
 
-	ret = uclass_get_device_by_name(UCLASS_GPIO, "pm8998_pon@800", &pon);
+	ret = button_get_by_label("pwrkey", &btn);
 	if (ret < 0) {
-		printf("Failed to find PMIC pon node. Check device tree\n");
-		return 0;
+		printf("Couldn't find power button!\n");
+		return ret;
 	}
 
-	node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon),
-				  "key_vol_down");
-	if (node < 0) {
-		printf("Failed to find key_vol_down node. Check device tree\n");
-		return 0;
-	}
-	if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
-				       &resin, 0)) {
-		printf("Failed to request key_vol_down button.\n");
-		return 0;
-	}
-	if (dm_gpio_get_value(&resin)) {
-		env_set("key_vol_down", "1");
-		printf("Volume down button pressed\n");
-	} else {
-		env_set("key_vol_down", "0");
-	}
-
-	node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon),
-				  "key_power");
-	if (node < 0) {
-		printf("Failed to find key_power node. Check device tree\n");
-		return 0;
-	}
-	if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
-				       &resin, 0)) {
-		printf("Failed to request key_power button.\n");
-		return 0;
-	}
-	if (dm_gpio_get_value(&resin)) {
+	state = button_get_state(btn);
+	if (state == BUTTON_ON) {
 		env_set("key_power", "1");
 		printf("Power button pressed\n");
 	} else {
diff --git a/arch/arm/mach-snapdragon/pinctrl-apq8016.c b/arch/arm/mach-snapdragon/pinctrl-apq8016.c
deleted file mode 100644
index 70c0be0bca9..00000000000
--- a/arch/arm/mach-snapdragon/pinctrl-apq8016.c
+++ /dev/null
@@ -1,61 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Qualcomm APQ8016 pinctrl
- *
- * (C) Copyright 2018 Ramon Fried <[email protected]>
- *
- */
-
-#include "pinctrl-snapdragon.h"
-#include <common.h>
-
-#define MAX_PIN_NAME_LEN 32
-static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
-static const char * const msm_pinctrl_pins[] = {
-	"SDC1_CLK",
-	"SDC1_CMD",
-	"SDC1_DATA",
-	"SDC2_CLK",
-	"SDC2_CMD",
-	"SDC2_DATA",
-	"QDSD_CLK",
-	"QDSD_CMD",
-	"QDSD_DATA0",
-	"QDSD_DATA1",
-	"QDSD_DATA2",
-	"QDSD_DATA3",
-};
-
-static const struct pinctrl_function msm_pinctrl_functions[] = {
-	{"blsp1_uart", 2},
-};
-
-static const char *apq8016_get_function_name(struct udevice *dev,
-					     unsigned int selector)
-{
-	return msm_pinctrl_functions[selector].name;
-}
-
-static const char *apq8016_get_pin_name(struct udevice *dev,
-					unsigned int selector)
-{
-	if (selector < 122) {
-		snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
-		return pin_name;
-	} else {
-		return msm_pinctrl_pins[selector - 122];
-	}
-}
-
-static unsigned int apq8016_get_function_mux(unsigned int selector)
-{
-	return msm_pinctrl_functions[selector].val;
-}
-
-struct msm_pinctrl_data apq8016_data = {
-	.pin_count = 133,
-	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
-	.get_function_name = apq8016_get_function_name,
-	.get_function_mux = apq8016_get_function_mux,
-	.get_pin_name = apq8016_get_pin_name,
-};
diff --git a/arch/arm/mach-snapdragon/pinctrl-apq8096.c b/arch/arm/mach-snapdragon/pinctrl-apq8096.c
deleted file mode 100644
index 45462f01c2c..00000000000
--- a/arch/arm/mach-snapdragon/pinctrl-apq8096.c
+++ /dev/null
@@ -1,56 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Qualcomm APQ8096 pinctrl
- *
- * (C) Copyright 2019 Ramon Fried <[email protected]>
- *
- */
-
-#include "pinctrl-snapdragon.h"
-#include <common.h>
-
-#define MAX_PIN_NAME_LEN 32
-static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
-static const char * const msm_pinctrl_pins[] = {
-	"SDC1_CLK",
-	"SDC1_CMD",
-	"SDC1_DATA",
-	"SDC2_CLK",
-	"SDC2_CMD",
-	"SDC2_DATA",
-	"SDC1_RCLK",
-};
-
-static const struct pinctrl_function msm_pinctrl_functions[] = {
-	{"blsp_uart8", 2},
-};
-
-static const char *apq8096_get_function_name(struct udevice *dev,
-					     unsigned int selector)
-{
-	return msm_pinctrl_functions[selector].name;
-}
-
-static const char *apq8096_get_pin_name(struct udevice *dev,
-					unsigned int selector)
-{
-	if (selector < 150) {
-		snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
-		return pin_name;
-	} else {
-		return msm_pinctrl_pins[selector - 150];
-	}
-}
-
-static unsigned int apq8096_get_function_mux(unsigned int selector)
-{
-	return msm_pinctrl_functions[selector].val;
-}
-
-struct msm_pinctrl_data apq8096_data = {
-	.pin_count = 157,
-	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
-	.get_function_name = apq8096_get_function_name,
-	.get_function_mux = apq8096_get_function_mux,
-	.get_pin_name = apq8096_get_pin_name,
-};
diff --git a/arch/arm/mach-snapdragon/pinctrl-qcs404.c b/arch/arm/mach-snapdragon/pinctrl-qcs404.c
deleted file mode 100644
index a6e53c4412e..00000000000
--- a/arch/arm/mach-snapdragon/pinctrl-qcs404.c
+++ /dev/null
@@ -1,68 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Qualcomm QCS404 pinctrl
- *
- * (C) Copyright 2022 Sumit Garg <[email protected]>
- */
-
-#include "pinctrl-snapdragon.h"
-#include <common.h>
-
-#define MAX_PIN_NAME_LEN 32
-static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
-static const char * const msm_pinctrl_pins[] = {
-	"SDC1_RCLK",
-	"SDC1_CLK",
-	"SDC1_CMD",
-	"SDC1_DATA",
-	"SDC2_CLK",
-	"SDC2_CMD",
-	"SDC2_DATA",
-};
-
-static const struct pinctrl_function msm_pinctrl_functions[] = {
-	{"blsp_uart2", 1},
-	{"rgmii_int", 1},
-	{"rgmii_ck", 1},
-	{"rgmii_tx", 1},
-	{"rgmii_ctl", 1},
-	{"rgmii_rx", 1},
-	{"rgmii_mdio", 1},
-	{"rgmii_mdc", 1},
-	{"blsp_i2c0", 3},
-	{"blsp_i2c1", 2},
-	{"blsp_i2c_sda_a2", 3},
-	{"blsp_i2c_scl_a2", 3},
-	{"blsp_i2c3", 2},
-	{"blsp_i2c4", 1},
-};
-
-static const char *qcs404_get_function_name(struct udevice *dev,
-					    unsigned int selector)
-{
-	return msm_pinctrl_functions[selector].name;
-}
-
-static const char *qcs404_get_pin_name(struct udevice *dev,
-				       unsigned int selector)
-{
-	if (selector < 120) {
-		snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
-		return pin_name;
-	} else {
-		return msm_pinctrl_pins[selector - 120];
-	}
-}
-
-static unsigned int qcs404_get_function_mux(unsigned int selector)
-{
-	return msm_pinctrl_functions[selector].val;
-}
-
-struct msm_pinctrl_data qcs404_data = {
-	.pin_count = 126,
-	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
-	.get_function_name = qcs404_get_function_name,
-	.get_function_mux = qcs404_get_function_mux,
-	.get_pin_name = qcs404_get_pin_name,
-};
diff --git a/arch/arm/mach-snapdragon/pinctrl-sdm845.c b/arch/arm/mach-snapdragon/pinctrl-sdm845.c
deleted file mode 100644
index 40f2f012fa0..00000000000
--- a/arch/arm/mach-snapdragon/pinctrl-sdm845.c
+++ /dev/null
@@ -1,44 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Qualcomm SDM845 pinctrl
- *
- * (C) Copyright 2021 Dzmitry Sankouski <[email protected]>
- *
- */
-
-#include "pinctrl-snapdragon.h"
-#include <common.h>
-
-#define MAX_PIN_NAME_LEN 32
-static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
-
-static const struct pinctrl_function msm_pinctrl_functions[] = {
-	{"qup9", 1},
-	{"gpio", 0},
-};
-
-static const char *sdm845_get_function_name(struct udevice *dev,
-					     unsigned int selector)
-{
-	return msm_pinctrl_functions[selector].name;
-}
-
-static const char *sdm845_get_pin_name(struct udevice *dev,
-					unsigned int selector)
-{
-	snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
-	return pin_name;
-}
-
-static unsigned int sdm845_get_function_mux(unsigned int selector)
-{
-	return msm_pinctrl_functions[selector].val;
-}
-
-struct msm_pinctrl_data sdm845_data = {
-	.pin_count = 150,
-	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
-	.get_function_name = sdm845_get_function_name,
-	.get_function_mux = sdm845_get_function_mux,
-	.get_pin_name = sdm845_get_pin_name,
-};
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
deleted file mode 100644
index 826dc514866..00000000000
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
+++ /dev/null
@@ -1,166 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * TLMM driver for Qualcomm APQ8016, APQ8096
- *
- * (C) Copyright 2018 Ramon Fried <[email protected]>
- *
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <dm/device_compat.h>
-#include <dm/lists.h>
-#include <dm/pinctrl.h>
-#include <linux/bitops.h>
-#include "pinctrl-snapdragon.h"
-
-struct msm_pinctrl_priv {
-	phys_addr_t base;
-	struct msm_pinctrl_data *data;
-};
-
-#define GPIO_CONFIG_OFFSET(x)         ((x) * 0x1000)
-#define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
-#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
-#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
-#define TLMM_GPIO_DISABLE BIT(9)
-
-static const struct pinconf_param msm_conf_params[] = {
-	{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 },
-	{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
-	{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 3 },
-};
-
-static int msm_get_functions_count(struct udevice *dev)
-{
-	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
-	return priv->data->functions_count;
-}
-
-static int msm_get_pins_count(struct udevice *dev)
-{
-	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
-	return priv->data->pin_count;
-}
-
-static const char *msm_get_function_name(struct udevice *dev,
-					 unsigned int selector)
-{
-	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
-	return priv->data->get_function_name(dev, selector);
-}
-
-static int msm_pinctrl_probe(struct udevice *dev)
-{
-	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
-	priv->base = dev_read_addr(dev);
-	priv->data = (struct msm_pinctrl_data *)dev->driver_data;
-
-	return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
-}
-
-static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector)
-{
-	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
-	return priv->data->get_pin_name(dev, selector);
-}
-
-static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
-			  unsigned int func_selector)
-{
-	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
-	clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
-			TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
-			priv->data->get_function_mux(func_selector) << 2);
-	return 0;
-}
-
-static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
-			   unsigned int param, unsigned int argument)
-{
-	struct msm_pinctrl_priv *priv = dev_get_priv(dev);
-
-	switch (param) {
-	case PIN_CONFIG_DRIVE_STRENGTH:
-		argument = (argument / 2) - 1;
-		clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
-				TLMM_DRV_STRENGTH_MASK, argument << 6);
-		break;
-	case PIN_CONFIG_BIAS_DISABLE:
-		clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
-			     TLMM_GPIO_PULL_MASK);
-		break;
-	case PIN_CONFIG_BIAS_PULL_UP:
-		clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
-				TLMM_GPIO_PULL_MASK, argument);
-		break;
-	default:
-		return 0;
-	}
-
-	return 0;
-}
-
-static struct pinctrl_ops msm_pinctrl_ops = {
-	.get_pins_count = msm_get_pins_count,
-	.get_pin_name = msm_get_pin_name,
-	.set_state = pinctrl_generic_set_state,
-	.pinmux_set = msm_pinmux_set,
-	.pinconf_num_params = ARRAY_SIZE(msm_conf_params),
-	.pinconf_params = msm_conf_params,
-	.pinconf_set = msm_pinconf_set,
-	.get_functions_count = msm_get_functions_count,
-	.get_function_name = msm_get_function_name,
-};
-
-static int msm_pinctrl_bind(struct udevice *dev)
-{
-	ofnode node = dev_ofnode(dev);
-	const char *name;
-	int ret;
-
-	ofnode_get_property(node, "gpio-controller", &ret);
-	if (ret < 0)
-		return 0;
-
-	/* Get the name of gpio node */
-	name = ofnode_get_name(node);
-	if (!name)
-		return -EINVAL;
-
-	/* Bind gpio node */
-	ret = device_bind_driver_to_node(dev, "gpio_msm",
-					 name, node, NULL);
-	if (ret)
-		return ret;
-
-	dev_dbg(dev, "bind %s\n", name);
-
-	return 0;
-}
-
-static const struct udevice_id msm_pinctrl_ids[] = {
-	{ .compatible = "qcom,msm8916-pinctrl", .data = (ulong)&apq8016_data },
-	{ .compatible = "qcom,msm8996-pinctrl", .data = (ulong)&apq8096_data },
-	{ .compatible = "qcom,sdm845-pinctrl", .data = (ulong)&sdm845_data },
-	{ .compatible = "qcom,qcs404-pinctrl", .data = (ulong)&qcs404_data },
-	{ }
-};
-
-U_BOOT_DRIVER(pinctrl_snapdraon) = {
-	.name		= "pinctrl_msm",
-	.id		= UCLASS_PINCTRL,
-	.of_match	= msm_pinctrl_ids,
-	.priv_auto	= sizeof(struct msm_pinctrl_priv),
-	.ops		= &msm_pinctrl_ops,
-	.probe		= msm_pinctrl_probe,
-	.bind		= msm_pinctrl_bind,
-};
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
deleted file mode 100644
index 178ee01a41f..00000000000
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Qualcomm Pin control
- *
- * (C) Copyright 2018 Ramon Fried <[email protected]>
- *
- */
-#ifndef _PINCTRL_SNAPDRAGON_H
-#define _PINCTRL_SNAPDRAGON_H
-
-struct udevice;
-
-struct msm_pinctrl_data {
-	int pin_count;
-	int functions_count;
-	const char *(*get_function_name)(struct udevice *dev,
-					 unsigned int selector);
-	unsigned int (*get_function_mux)(unsigned int selector);
-	const char *(*get_pin_name)(struct udevice *dev,
-				    unsigned int selector);
-};
-
-struct pinctrl_function {
-	const char *name;
-	int val;
-};
-
-extern struct msm_pinctrl_data apq8016_data;
-extern struct msm_pinctrl_data apq8096_data;
-extern struct msm_pinctrl_data sdm845_data;
-extern struct msm_pinctrl_data qcs404_data;
-
-#endif
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 4fe72664c4b..e264b29554c 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -1544,10 +1544,10 @@
 			spmi_gpios: gpios@c000 {
 				compatible = "qcom,pm8916-gpio";
 				reg = <0xc000 0x400>;
+				gpio-ranges = <&spmi_gpios 0 0 4>;
 				gpio-controller;
 				gpio-count = <4>;
 				#gpio-cells = <2>;
-				gpio-bank-name="spmi";
 			};
 		};
 	};