diff options
| author | Siu Ming Tong <[email protected]> | 2026-05-27 19:38:36 -0700 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-06-10 14:52:25 -0600 |
| commit | 7a06f03e575df25d34cf4085000e21ea97082ab6 (patch) | |
| tree | 92375de6829c605167e307631a0d782efba51864 /contrib/apps/httpserver | |
| parent | 052988aa29bfd506d7ce207fbb3f5374a5dbecbb (diff) | |
arm64: dts: axiado: Add AX3005 SCM3005 device tree
Add device tree source files for the Axiado AX3005 SCM3005 board.
The AX3005 is a quad-core 64-bit ARMv8 Cortex-A53 SoC.
The DTSI describes the SoC-level nodes: GIC-v3 interrupt controller,
Cadence/Zynq UART, fixed reference clock, and spin-table secondary
CPU boot. A /memreserve/ directive protects the spin-table release
address at 0x80002fa0 from being overwritten during boot.
The SCM3005 DTS sets the console to uart3 at 115200 baud and declares
2 GB of DRAM starting at 0x80000000.
Tested-by: Siu Ming Tong <[email protected]>
Signed-off-by: Karthikeyan Mitran <[email protected]>
Signed-off-by: Siu Ming Tong <[email protected]>
Diffstat (limited to 'contrib/apps/httpserver')
0 files changed, 0 insertions, 0 deletions