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-rw-r--r--drivers/clk/qcom/clock-qcs615.c2
-rw-r--r--drivers/phy/qcom/phy-qcom-qusb2.c38
-rw-r--r--drivers/power/regulator/Kconfig2
-rw-r--r--drivers/serial/serial_msm_geni.c15
-rw-r--r--drivers/soc/qcom/rpmh-rsc.c8
-rw-r--r--drivers/soc/qcom/rpmh.c4
-rw-r--r--drivers/watchdog/Kconfig1
-rw-r--r--drivers/watchdog/qcom-wdt.c2
8 files changed, 55 insertions, 17 deletions
diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c
index 4700baba8c9..2087fc38f63 100644
--- a/drivers/clk/qcom/clock-qcs615.c
+++ b/drivers/clk/qcom/clock-qcs615.c
@@ -66,6 +66,8 @@ static const struct gate_clk qcs615_clks[] = {
GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf050, BIT(0)),
GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf054, BIT(0)),
GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf058, BIT(0)),
+ GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x8c014, BIT(0)),
+ GATE_CLK(GCC_AHB2PHY_WEST_CLK, 0x6a004, BIT(0)),
GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT),
GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT),
GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT),
diff --git a/drivers/phy/qcom/phy-qcom-qusb2.c b/drivers/phy/qcom/phy-qcom-qusb2.c
index 9e821365c15..6278171b100 100644
--- a/drivers/phy/qcom/phy-qcom-qusb2.c
+++ b/drivers/phy/qcom/phy-qcom-qusb2.c
@@ -176,6 +176,19 @@ static const unsigned int sm6115_regs_layout[] = {
[QUSB2PHY_PORT_POWERDOWN] = 0xb4, [QUSB2PHY_INTR_CTRL] = 0xbc,
};
+static const unsigned int ipq6018_regs_layout[] = {
+ [QUSB2PHY_PLL_STATUS] = 0x38,
+ [QUSB2PHY_PORT_TUNE1] = 0x80,
+ [QUSB2PHY_PORT_TUNE2] = 0x84,
+ [QUSB2PHY_PORT_TUNE3] = 0x88,
+ [QUSB2PHY_PORT_TUNE4] = 0x8C,
+ [QUSB2PHY_PORT_TUNE5] = 0x90,
+ [QUSB2PHY_PORT_TEST1] = 0x98,
+ [QUSB2PHY_PORT_TEST2] = 0x9C,
+ [QUSB2PHY_PORT_POWERDOWN] = 0xB4,
+ [QUSB2PHY_INTR_CTRL] = 0xBC,
+};
+
static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
@@ -189,6 +202,19 @@ static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
};
+static const struct qusb2_phy_init_tbl qcs615_init_tbl[] = {
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xc8),
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0),
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
+};
+
static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = {
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03),
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
@@ -260,6 +286,16 @@ static const struct qusb2_phy_cfg sdm660_phy_cfg = {
.autoresume_en = BIT(3),
};
+static const struct qusb2_phy_cfg qcs615_phy_cfg = {
+ .tbl = qcs615_init_tbl,
+ .tbl_num = ARRAY_SIZE(qcs615_init_tbl),
+ .regs = ipq6018_regs_layout,
+
+ .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
+ .mask_core_ready = PLL_LOCKED,
+ .autoresume_en = BIT(0),
+};
+
static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
.tbl = qusb2_v2_init_tbl,
.tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl),
@@ -467,6 +503,8 @@ static const struct udevice_id qusb2phy_ids[] = {
{ .compatible = "qcom,qusb2-phy" },
{ .compatible = "qcom,qcm2290-qusb2-phy",
.data = (ulong)&sm6115_phy_cfg },
+ { .compatible = "qcom,qcs615-qusb2-phy",
+ .data = (ulong)&qcs615_phy_cfg },
{ .compatible = "qcom,sdm660-qusb2-phy",
.data = (ulong)&sdm660_phy_cfg },
{ .compatible = "qcom,sm6115-qusb2-phy",
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index bd9ccd26981..d8b3e0f62e6 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -236,7 +236,7 @@ config DM_REGULATOR_QCOM_RPMH
config DM_REGULATOR_QCOM_USB_VBUS
bool "Enable driver model for Qualcomm USB vbus regulator"
- depends on DM_REGULATOR
+ depends on DM_REGULATOR && DM_PMIC
---help---
Enable support for the Qualcomm USB Vbus regulator. The driver
implements get/set api for the regulator to be used by u-boot.
diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
index bb5a2cb4d2c..3dca581f68f 100644
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -212,7 +212,7 @@ static int msm_serial_setbrg(struct udevice *dev, int baud)
ret = clk_set_rate(priv->se, clk_rate);
if (ret < 0) {
pr_err("%s: Couldn't set clock rate: %d\n", __func__, ret);
- return ret;
+ return 0;
}
geni_serial_baud(priv->base, clk_div, baud);
@@ -517,13 +517,14 @@ static int msm_serial_probe(struct udevice *dev)
u32 proto;
struct clk *clk;
- clk = devm_clk_get(dev, NULL);
+ clk = devm_clk_get_optional(dev, NULL);
if (IS_ERR(clk))
- return PTR_ERR(clk);
- priv->se = clk;
+ dev_dbg(dev, "Couldn't find UART clock: %ld", PTR_ERR(clk));
+ else
+ priv->se = clk;
/* Try enable clock */
- ret = clk_enable(clk);
+ clk_enable(clk);
/* Check if firmware loading is needed (BT UART) */
proto = readl(priv->base + GENI_FW_REVISION_RO);
@@ -547,10 +548,6 @@ static int msm_serial_probe(struct udevice *dev)
if (ofnode_device_is_compatible(dev_ofnode(dev), "qcom,geni-uart"))
return -ENOENT;
- /* Now handle clock enable return value */
- if (ret)
- return ret;
-
ret = geni_set_oversampling(dev);
if (ret < 0)
return ret;
diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c
index dce61f26229..0b821cc6f9d 100644
--- a/drivers/soc/qcom/rpmh-rsc.c
+++ b/drivers/soc/qcom/rpmh-rsc.c
@@ -261,8 +261,8 @@ static struct tcs_group *get_tcs_for_msg(struct rsc_drv *drv,
* just always used the first active TCS.
*/
if (msg->state != RPMH_ACTIVE_ONLY_STATE) {
- log_err("WARN: only ACTIVE_ONLY state supported\n");
- return ERR_PTR(-EINVAL);
+ log_debug("WARN: only ACTIVE_ONLY state supported\n");
+ return NULL;
}
return &drv->tcs[ACTIVE_TCS];
@@ -390,8 +390,8 @@ int rpmh_rsc_send_data(struct rsc_drv *drv, const struct tcs_request *msg)
u32 val;
tcs = get_tcs_for_msg(drv, msg);
- if (IS_ERR(tcs))
- return PTR_ERR(tcs);
+ if (IS_ERR_OR_NULL(tcs))
+ return 0;
/* U-Boot is single-threaded, always use the first TCS as we'll never conflict */
tcs_id = tcs->offset;
diff --git a/drivers/soc/qcom/rpmh.c b/drivers/soc/qcom/rpmh.c
index 8c222324c66..b55e23c4417 100644
--- a/drivers/soc/qcom/rpmh.c
+++ b/drivers/soc/qcom/rpmh.c
@@ -60,8 +60,8 @@ static int __rpmh_write(const struct udevice *dev, enum rpmh_state state,
struct rpmh_ctrlr *ctrlr = get_rpmh_ctrlr(dev);
if (state != RPMH_ACTIVE_ONLY_STATE) {
- log_err("only ACTIVE_ONLY state supported\n");
- return -EINVAL;
+ log_debug("WARN: Only ACTIVE_ONLY state supported\n");
+ return 0;
}
return rpmh_rsc_send_data(ctrlr_to_drv(ctrlr), &rpm_msg->msg);
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 35ae7d106b1..416d29d256a 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -16,6 +16,7 @@ config WATCHDOG_AUTOSTART
depends on WDT
default n if ARCH_SUNXI
default n if ARCH_STM32MP
+ default n if ARCH_SNAPDRAGON
default y
help
Automatically start watchdog timer and start servicing it during
diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c
index e4ebb1f31d4..a8d7e7a7950 100644
--- a/drivers/watchdog/qcom-wdt.c
+++ b/drivers/watchdog/qcom-wdt.c
@@ -129,7 +129,7 @@ static int qcom_wdt_probe(struct udevice *dev)
wdt->clk_rate = (ulong)rate;
- return 0;
+ return qcom_wdt_stop(dev);
}
static const struct wdt_ops qcom_wdt_ops = {
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-11 16:05:24 +0000