diff options
97 files changed, 3716 insertions, 4320 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 4d168349ae6..f88a3500d86 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1859,10 +1859,14 @@ F: drivers/tpm/ F: include/tpm* F: lib/tpm* -TQ GROUP -#M: Martin Krause <[email protected]> -S: Orphaned (Since 2016-02) -T: git git://git.denx.de/u-boot-tq-group.git +TQ-SYSTEMS +S: Maintained +W: https://www.tq-group.com/en/products/tq-embedded/ +F: board/tq/* +F: doc/board/tq/* +F: include/configs/tq*.h +F: include/env/tq/* TEE M: Jens Wiklander <[email protected]> diff --git a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi index cf2a87a9b90..13e1070c28e 100644 --- a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi @@ -22,6 +22,18 @@ bootph-pre-ram; }; +&pca9450 { + bootph-all; +}; + +&pinctrl_i2c1 { + bootph-all; +}; + +&pinctrl_pmic { + bootph-all; +}; + &pinctrl_uart2 { bootph-pre-ram; }; @@ -63,7 +75,7 @@ }; &i2c1 { - bootph-pre-ram; + bootph-all; }; &i2c2 { @@ -118,3 +130,7 @@ phy-reset-duration = <15>; phy-reset-post-delay = <100>; }; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + bootph-all; +}; diff --git a/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi b/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi index 1320f1540ed..f917b71be90 100644 --- a/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi @@ -33,6 +33,18 @@ }; }; +&pinctrl_i2c1 { + bootph-all; +}; + +&pinctrl_pmic { + bootph-all; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + bootph-all; +}; + ®_usdhc2_vmmc { bootph-pre-ram; }; @@ -78,11 +90,11 @@ }; &i2c1 { - bootph-pre-ram; + bootph-all; }; &pmic { - bootph-pre-ram; + bootph-all; }; /* USB1 Type-C */ @@ -120,6 +132,12 @@ &usdhc2 { bootph-pre-ram; + /* + * LDO5 output depends on SD2_VSEL, but no way to read back SD2_VSEL + * when using SDHC controller VSELECT to control SD2_VSEL. So drop + * vqmmc-supply to avoid fsl_esdhc_imx read back wrong voltage. + */ + /delete-property/ vqmmc-supply; }; &usdhc3 { diff --git a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi index 4804a204e92..e9403d9ea82 100644 --- a/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi @@ -34,6 +34,18 @@ }; }; +&pinctrl_i2c1 { + bootph-all; +}; + +&pinctrl_pmic { + bootph-all; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + bootph-all; +}; + ®_usdhc2_vmmc { bootph-pre-ram; }; @@ -83,11 +95,11 @@ }; &i2c1 { - bootph-pre-ram; + bootph-all; }; &pmic { - bootph-pre-ram; + bootph-all; }; &usb_dwc3_0 { @@ -96,6 +108,12 @@ &usdhc2 { bootph-pre-ram; + /* + * LDO5 output depends on SD2_VSEL, but no way to read back SD2_VSEL + * when using SDHC controller VSELECT to control SD2_VSEL. So drop + * vqmmc-supply to avoid fsl_esdhc_imx read back wrong voltage. + */ + /delete-property/ vqmmc-supply; }; &usdhc3 { diff --git a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi index 7b45a87450b..3b0af5bc0a0 100644 --- a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi @@ -70,7 +70,7 @@ }; &i2c1 { - bootph-pre-ram; + bootph-all; eeprom_module: eeprom@50 { compatible = "i2c-eeprom"; @@ -104,7 +104,7 @@ }; &pca9450 { - bootph-pre-ram; + bootph-all; }; &pinctrl_ctrl_sleep_moci { @@ -112,7 +112,11 @@ }; &pinctrl_i2c1 { - bootph-pre-ram; + bootph-all; +}; + +&pinctrl_pmic { + bootph-all; }; &pinctrl_usdhc2_pwr_en { @@ -159,6 +163,12 @@ sd-uhs-ddr50; sd-uhs-sdr104; bootph-pre-ram; + /* + * LDO5 output depends on SD2_VSEL, but no way to read back SD2_VSEL + * when using SDHC controller VSELECT to control SD2_VSEL. So drop + * vqmmc-supply to avoid fsl_esdhc_imx read back wrong voltage. + */ + /delete-property/ vqmmc-supply; }; &usdhc3 { @@ -173,3 +183,7 @@ &wdog1 { bootph-pre-ram; }; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + bootph-all; +}; diff --git a/arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi b/arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi new file mode 100644 index 00000000000..64ed7af9946 --- /dev/null +++ b/arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2026 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser <[email protected]> + * + */ + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog3>; + bootph-pre-ram; + bootph-some-ram; + }; + + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + }; + + bootstd { + bootph-verify; + compatible = "u-boot,boot-std"; + + filename-prefixes = "/", "/boot/"; + bootdev-order = "mmc0", "mmc1", "ethernet"; + + rauc { + compatible = "u-boot,distro-rauc"; + }; + + script { + compatible = "u-boot,script"; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + bootph-all; + bootph-pre-ram; +}; + +&aips1 { + bootph-pre-ram; + bootph-all; +}; + +&aips2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&aips3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&iomuxc { + bootph-pre-ram; + bootph-some-ram; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_lpi2c3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_pmic { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_reg_usdhc2_vmmc { + bootph-pre-ram; +}; + +&pinctrl_uart1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc1_100mhz { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_cd { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_default { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_100mhz { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_200mhz { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio4 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpuart1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&usdhc1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&usdhc2 { + bootph-pre-ram; + bootph-some-ram; + fsl,signal-voltage-switch-extra-delay-ms = <8>; +}; + +&lpi2c1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpi2c2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpi2c3 { + bootph-pre-ram; + bootph-some-ram; + + pmic@25 { + bootph-pre-ram; + bootph-some-ram; + + regulators { + bootph-pre-ram; + bootph-some-ram; + }; + }; + + eeprom@50 { + bootph-pre-ram; + bootph-some-ram; + }; +}; + +&s4muap { + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&clk { + bootph-all; + bootph-pre-ram; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-rates; + /delete-property/ assigned-clock-parents; +}; + +&osc_32k { + bootph-all; + bootph-pre-ram; +}; + +&osc_24m { + bootph-all; + bootph-pre-ram; +}; + +&clk_ext1 { + bootph-all; + bootph-pre-ram; +}; + +&wdog3 { + bootph-all; + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi new file mode 100644 index 00000000000..5d788854de5 --- /dev/null +++ b/arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2026 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser <[email protected]> + * + */ + +#include "imx91-u-boot.dtsi" +#include "imx91-93-phyboard-segin-common-u-boot.dtsi" + +/ { + /* + * The phyCORE-i.MX91 u-boot uses the imx91-phyboard-segin.dts as + * reference, but does only make use of its SoM (phyCORE) contained + * periphery. + */ + model = "PHYTEC phyCORE-i.MX91"; +}; diff --git a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi index 646b617949d..b80ce20e942 100644 --- a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi +++ b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi @@ -9,6 +9,7 @@ */ #include "imx93-u-boot.dtsi" +#include "imx91-93-phyboard-segin-common-u-boot.dtsi" / { /* @@ -17,224 +18,4 @@ * periphery. */ model = "PHYTEC phyCORE-i.MX93"; - - wdt-reboot { - compatible = "wdt-reboot"; - wdt = <&wdog3>; - bootph-pre-ram; - bootph-some-ram; - }; - - aliases { - ethernet0 = &fec; - ethernet1 = &eqos; - }; - - bootstd { - bootph-verify; - compatible = "u-boot,boot-std"; - - filename-prefixes = "/", "/boot/"; - bootdev-order = "mmc0", "mmc1", "ethernet"; - - rauc { - compatible = "u-boot,distro-rauc"; - }; - - script { - compatible = "u-boot,script"; - }; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; -}; - -&{/soc@0} { - bootph-all; - bootph-pre-ram; -}; - -&aips1 { - bootph-pre-ram; - bootph-all; -}; - -&aips2 { - bootph-pre-ram; - bootph-some-ram; -}; - -&aips3 { - bootph-pre-ram; - bootph-some-ram; -}; - -&iomuxc { - bootph-pre-ram; - bootph-some-ram; -}; - -®_usdhc2_vmmc { - u-boot,off-on-delay-us = <20000>; - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_lpi2c3 { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_pmic { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_reg_usdhc2_vmmc { - bootph-pre-ram; -}; - -&pinctrl_uart1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc1_100mhz { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc1_200mhz { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc2_cd { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc2_default { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc2_100mhz { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc2_200mhz { - bootph-pre-ram; - bootph-some-ram; -}; - -&gpio1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&gpio2 { - bootph-pre-ram; - bootph-some-ram; -}; - -&gpio3 { - bootph-pre-ram; - bootph-some-ram; -}; - -&gpio4 { - bootph-pre-ram; - bootph-some-ram; -}; - -&lpuart1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&usdhc1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&usdhc2 { - bootph-pre-ram; - bootph-some-ram; - fsl,signal-voltage-switch-extra-delay-ms = <8>; -}; - -&lpi2c1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&lpi2c2 { - bootph-pre-ram; - bootph-some-ram; -}; - -&lpi2c3 { - bootph-pre-ram; - bootph-some-ram; - - pmic@25 { - bootph-pre-ram; - bootph-some-ram; - - regulators { - bootph-pre-ram; - bootph-some-ram; - }; - }; - - eeprom@50 { - bootph-pre-ram; - bootph-some-ram; - }; -}; - -&s4muap { - bootph-pre-ram; - bootph-some-ram; - status = "okay"; -}; - -&clk { - bootph-all; - bootph-pre-ram; - /delete-property/ assigned-clocks; - /delete-property/ assigned-clock-rates; - /delete-property/ assigned-clock-parents; -}; - -&osc_32k { - bootph-all; - bootph-pre-ram; -}; - -&osc_24m { - bootph-all; - bootph-pre-ram; -}; - -&clk_ext1 { - bootph-all; - bootph-pre-ram; -}; - -&wdog3 { - bootph-all; - bootph-pre-ram; }; diff --git a/arch/arm/dts/imx95-toradex-smarc-dev.dts b/arch/arm/dts/imx95-toradex-smarc-dev.dts deleted file mode 100644 index 5b05f256fd5..00000000000 --- a/arch/arm/dts/imx95-toradex-smarc-dev.dts +++ /dev/null @@ -1,277 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2025 Toradex - * - * https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx95 - * https://www.toradex.com/products/carrier-board/smarc-development-board-kit - */ - -/dts-v1/; - -#include <dt-bindings/pwm/pwm.h> -#include "imx95-toradex-smarc.dtsi" - -/ { - model = "Toradex SMARC iMX95 on Toradex SMARC Development Board"; - compatible = "toradex,smarc-imx95-dev", - "toradex,smarc-imx95", - "fsl,imx95"; - - reg_carrier_1p8v: regulator-carrier-1p8v { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "On-carrier 1V8"; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,bitclock-master = <&codec_dai>; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&codec_dai>; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "tdx-smarc-wm8904"; - simple-audio-card,routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "IN2L", "Line In Jack", - "IN2R", "Line In Jack", - "Microphone Jack", "MICBIAS", - "IN1L", "Microphone Jack"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Line", "Line In Jack"; - - codec_dai: simple-audio-card,codec { - clocks = <&scmi_clk IMX95_CLK_SAI3>; - sound-dai = <&wm8904_1a>; - }; - - simple-audio-card,cpu { - sound-dai = <&sai3>; - }; - }; -}; - -/* SMARC GBE0 */ -&enetc_port0 { - status = "okay"; -}; - -/* SMARC GBE1 */ -&enetc_port1 { - status = "okay"; -}; - -/* SMARC CAN0 */ -&flexcan1 { - status = "okay"; -}; - -/* SMARC CAN1 */ -&flexcan2 { - status = "okay"; -}; - -&gpio2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio12>, <&pinctrl_gpio13>; -}; - -&gpio4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio10>, <&pinctrl_gpio11>; -}; - -&gpio5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio2>, - <&pinctrl_gpio3>, - <&pinctrl_gpio4>, - <&pinctrl_gpio6>, - <&pinctrl_gpio8>, - <&pinctrl_gpio9>; -}; - -/* SMARC I2C_CAM0 */ -&i2c_cam0 { - status = "okay"; -}; - -/* SMARC I2C_CAM1 */ -&i2c_cam1 { - status = "okay"; -}; - -/* SMARC I2C_GP */ -&lpi2c2 { - status = "okay"; - - wm8904_1a: audio-codec@1a { - compatible = "wlf,wm8904"; - reg = <0x1a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>, <&pinctrl_sai3_mclk>; - #sound-dai-cells = <0>; - clocks = <&scmi_clk IMX95_CLK_SAI3>; - clock-names = "mclk"; - AVDD-supply = <®_carrier_1p8v>; - CPVDD-supply = <®_carrier_1p8v>; - DBVDD-supply = <®_carrier_1p8v>; - DCVDD-supply = <®_carrier_1p8v>; - MICVDD-supply = <®_carrier_1p8v>; - }; - - temperature-sensor@4f { - compatible = "ti,tmp1075"; - reg = <0x4f>; - }; - - eeprom@57 { - compatible = "st,24c02", "atmel,24c02"; - reg = <0x57>; - pagesize = <16>; - }; - -}; - -/* SMARC I2C_PM */ -&lpi2c3 { - clock-frequency = <100000>; - status = "okay"; - - fan_controller: fan@18 { - compatible = "ti,amc6821"; - reg = <0x18>; - #pwm-cells = <2>; - - fan { - cooling-levels = <255>; - pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>; - }; - }; - - /* Current measurement into module VCC */ - hwmon@40 { - compatible = "ti,ina226"; - reg = <0x40>; - shunt-resistor = <5000>; - }; -}; - -/* SMARC I2C_LCD */ -&lpi2c5 { - status = "okay"; - - i2c-mux@70 { - compatible = "nxp,pca9543"; - reg = <0x70>; - i2c-mux-idle-disconnect; - #address-cells = <1>; - #size-cells = <0>; - - /* I2C on DSI Connector Pins 4/6 */ - i2c_dsi_0: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - /* I2C on DSI Connector Pins 52/54 */ - i2c_dsi_1: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -/* SMARC SPI0 */ -&lpspi6 { - status = "okay"; -}; - -/* SMARC SER1, used as the Linux Console */ -&lpuart1 { - status = "okay"; -}; - -/* SMARC SER0, RS485 */ -&lpuart2 { - linux,rs485-enabled-at-boot-time; - rs485-rts-active-low; - rs485-rx-during-tx; - status = "okay"; -}; - -/* SMARC SER3, RS232 */ -&lpuart3 { - status = "okay"; -}; - -/* SMARC MDIO, shared between all ethernet ports */ -&netc_emdio { - status = "okay"; - - ethphy3: ethernet-phy@4 { - reg = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio7>; - interrupt-parent = <&gpio5>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -/* SMARC PCIE_A / M2 Key B */ -&pcie0 { - status = "okay"; -}; - -/* SMARC PCIE_B / M2 Key E */ -&pcie1 { - status = "okay"; -}; - -/* SMARC I2S0 */ -&sai3 { - status = "okay"; -}; - -/* SMARC LCD0_BKLT_PWM */ -&tpm3 { - status = "okay"; -}; - -/* SMARC LCD1_BKLT_PWM */ -&tpm4 { - status = "okay"; -}; - -/* SMARC GPIO5 as PWM */ -&tpm5 { - status = "okay"; -}; - -/* SMARC USB0 */ -&usb2 { - status = "okay"; -}; - -/* SMARC USB1..4 */ -&usb3 { - status = "okay"; -}; - -&usb3_dwc3 { - status = "okay"; -}; - -&usb3_phy { - status = "okay"; -}; - -/* SMARC SDIO */ -&usdhc2 { - status = "okay"; -}; diff --git a/arch/arm/dts/imx95-toradex-smarc.dtsi b/arch/arm/dts/imx95-toradex-smarc.dtsi deleted file mode 100644 index e99f1a57af8..00000000000 --- a/arch/arm/dts/imx95-toradex-smarc.dtsi +++ /dev/null @@ -1,1153 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2025 Toradex - * - * https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx95 - */ - -#include <dt-bindings/input/input.h> -#include <dt-bindings/net/ti-dp83867.h> -#include "imx95.dtsi" - -/ { - aliases { - can0 = &flexcan1; - can1 = &flexcan2; - ethernet0 = &enetc_port0; - ethernet1 = &enetc_port1; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - rtc0 = &rtc_i2c; - rtc1 = &scmi_bbm; - serial0 = &lpuart2; - serial1 = &lpuart1; - serial3 = &lpuart3; - }; - - chosen { - stdout-path = "serial1:115200n8"; - }; - - clk_dsi2dp_bridge: clock-dsi2dp-bridge { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; - - clk_serdes_eth_ref: clock-eth-ref { - compatible = "gpio-gate-clock"; - #clock-cells = <0>; - /* CTRL_ETH_REF_CLK_STBY# */ - enable-gpios = <&som_gpio_expander_1 13 GPIO_ACTIVE_HIGH>; - }; - - connector { - compatible = "gpio-usb-b-connector", "usb-b-connector"; - /* SMARC P64 - USB0_OTG_ID */ - id-gpios = <&som_gpio_expander_0 3 GPIO_ACTIVE_HIGH>; - label = "USB0"; - self-powered; - type = "micro"; - vbus-supply = <®_usb0_vbus>; - - port { - usb_dr_connector: endpoint { - remote-endpoint = <&usb0_otg_id>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - smarc_key_sleep: key-sleep { - gpios = <&som_ec_gpio_expander 4 GPIO_ACTIVE_LOW>; - label = "SMARC_SLEEP#"; - wakeup-source; - linux,code = <KEY_SLEEP>; - }; - - smarc_switch_lid: switch-lid { - gpios = <&som_ec_gpio_expander 2 GPIO_ACTIVE_LOW>; - label = "SMARC_LID#"; - linux,code = <SW_LID>; - linux,input-type = <EV_SW>; - }; - }; - - reg_module_1p8v: regulator-module-1p8v { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "On-module +V1.8"; - }; - - /* Non PMIC On-module Supplies */ - reg_module_dp_1p2v: regulator-module-dp-1p2v { - compatible = "regulator-fixed"; - regulator-max-microvolt = <1200000>; - regulator-min-microvolt = <1200000>; - regulator-name = "On-module +V1.2_DP"; - vin-supply = <®_module_1p8v>; - }; - - reg_usb0_vbus: regulator-usb0-vbus { - compatible = "regulator-fixed"; - /* SMARC P62 - USB0_EN_OC# */ - gpios = <&som_gpio_expander_0 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-name = "USB0_EN_OC#"; - }; - - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - /* CTRL_V_BUS_USB_HUB or SMARC P71 - USB2_EN_OC# */ - gpios = <&som_gpio_expander_0 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-name = "CTRL_V_BUS_USB_HUB"; - }; - - reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; - enable-active-high; - gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; - off-on-delay-us = <100000>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "SDIO_PWR_EN"; - startup-delay-us = <20000>; - }; - - reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { - compatible = "regulator-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_vsel>; - gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; - states = <1800000 0x1>, - <3300000 0x0>; - regulator-name = "PMIC_SD2_VSEL"; - }; - - reg_wifi_en: regulator-wifi-en { - compatible = "regulator-fixed"; - /* CTRL_EN_WIFI */ - gpios = <&som_gpio_expander_1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "CTRL_EN_WIFI"; - startup-delay-us = <2000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - linux_cma: linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0 0x3c000000>; - alloc-ranges = <0 0x80000000 0 0x7F000000>; - linux,cma-default; - }; - }; -}; - -/* SMARC GBE0 */ -&enetc_port0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enetc0>, <&pinctrl_enetc0_1588_tmr>; - phy-handle = <ðphy1>; - phy-mode = "rgmii-id"; -}; - -/* SMARC GBE1 */ -&enetc_port1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enetc1>, <&pinctrl_enetc1_1588_tmr>; - phy-handle = <ðphy2>; - phy-mode = "rgmii-id"; -}; - -/* SMARC CAN0 */ -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; -}; - -/* SMARC CAN1 */ -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; -}; - -&gpio1 { - gpio-line-names = "", /* 0 */ - "", - "SMARC_I2C_GP_CK", - "SMARC_I2C_GP_DAT", - "", - "", - "", - "", - "", - "", - "", /* 10 */ - "", - "", - "", - "CTRL_IO_EXP_INT_B"; - status = "okay"; -}; - -&gpio2 { - gpio-line-names = "SMARC_SPI0_CS0#", /* 0 */ - "", - "", - "", - "", - "", - "SMARC_GPIO5", - "", - "I2C_CAM_DAT", - "I2C_CAM_CK", - "SMARC_GPIO12", /* 10 */ - "SMARC_GPIO13", - "", - "", - "", - "", - "", - "", - "SMARC_SPI1_CS0#", - "", - "", /* 20 */ - "", - "SMARC_I2C_LCD_DAT", - "SMARC_I2C_LCD_CK", - "SMARC_SPI0_CS1#", - "", - "", - "", - "SMARC_I2C_PM_DAT", - "SMARC_I2C_PM_CK", - "I2C_SOM_DAT", /* 30 */ - "I2C_SOM_CK"; - status = "okay"; -}; - -&gpio3 { - gpio-line-names = "SMARC_SDIO_CD#", /* 0 */ - "", - "", - "", - "", - "", - "", - "SMARC_SDIO_PWR_EN", - "", - "", - "", /* 10 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "PMIC_SD2_VSEL"; - status = "okay"; -}; - -&gpio4 { - gpio-line-names = "", /* 0 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 10 */ - "", - "", - "", - "SMARC_GPIO11", - "SMARC_GPIO10", - "", - "", - "", - "", - "", /* 20 */ - "", - "", - "", - "", - "", - "", - "", - "SMARC_SMB_ALERT#"; - status = "okay"; -}; - -&gpio5 { - gpio-line-names = "SMARC_GPIO2", /* 0 */ - "SMARC_GPIO3", - "SMARC_GPIO4", - "SMARC_GPIO6", - "", - "", - "", - "", - "SMARC_GPIO9", - "SMARC_GPIO7", - "SMARC_GPIO8", /* 10 */ - "SMARC_SPI1_CS1#", - "", - "SPI1_TPM_CS#"; - status = "okay"; -}; - -/* SMARC I2C_GP */ -&lpi2c2 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_lpi2c2>; - pinctrl-1 = <&pinctrl_lpi2c2_gpio>; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - eeprom@50 { - compatible = "st,24c32", "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -/* SMARC I2C_PM */ -&lpi2c3 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_lpi2c3>; - pinctrl-1 = <&pinctrl_lpi2c3_gpio>; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -}; - -/* I2C_SOM */ -&lpi2c4 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_lpi2c4>, <&pinctrl_ctrl_io_exp_int_b>; - pinctrl-1 = <&pinctrl_lpi2c4_gpio>, <&pinctrl_ctrl_io_exp_int_b>; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - som_gpio_expander_0: gpio@20 { - compatible = "nxp,pcal6408"; - reg = <0x20>; - #interrupt-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio1>; - interrupts = <14 IRQ_TYPE_LEVEL_LOW>; - #gpio-cells = <2>; - gpio-controller; - gpio-line-names = - "SMARC_PCIE_WAKE#", /* 0 */ - "SMARC_PCIE_B_RST#", - "SMARC_PCIE_A_RST#", - "SMARC_USB0_OTG_ID", - "SMARC_USB0_EN", /* SMARC USB0_EN_OC# - Open Drain Output */ - "SMARC_USB0_OC#", /* SMARC USB0_EN_OC# - Over-Current Sense Input */ - "", - "SMARC_PCIE_C_RST#"; - }; - - som_gpio_expander_1: gpio@21 { - compatible = "nxp,pcal6416"; - reg = <0x21>; - #interrupt-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio1>; - interrupts = <14 IRQ_TYPE_LEVEL_LOW>; - #gpio-cells = <2>; - gpio-controller; - gpio-line-names = - "SMARC_GPIO0", /* 0 */ - "SMARC_GPIO1", - "SMARC_LCD0_VDD_EN", - "SMARC_LCD0_BKLT_EN", - "SMARC_LCD1_VDD_EN", - "SMARC_LCD1_BKLT_EN", - "", - "", - "", - "", - "", /* 10 */ - "", - "", - "", - "", - "", - "", - "SMARC_SDIO_WP"; - }; - - embedded-controller@28 { - compatible = "toradex,smarc-imx95-ec", "toradex,smarc-ec"; - reg = <0x28>; - }; - - som_ec_gpio_expander: gpio@29 { - compatible = "toradex,ecgpiol16", "nxp,pcal6416"; - reg = <0x29>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ec_int>; - #interrupt-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio1>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - #gpio-cells = <2>; - gpio-controller; - gpio-line-names = - "SMARC_CHARGER_PRSNT#", - "SMARC_CHARGING#", - "SMARC_LID#", - "SMARC_BATLOW#", - "SMARC_SLEEP#"; - }; - - /* SMARC DP0 */ - som_dsi2dp_bridge: bridge@2c { - compatible = "ti,sn65dsi86"; - reg = <0x2c>; - clocks = <&clk_dsi2dp_bridge>; - clock-names = "refclk"; - vcc-supply = <®_module_dp_1p2v>; - vcca-supply = <®_module_dp_1p2v>; - vccio-supply = <®_module_1p8v>; - vpll-supply = <®_module_1p8v>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - sn65dsi86_in: endpoint { - }; - }; - - port@1 { - reg = <1>; - sn65dsi86_out: endpoint { - data-lanes = <3 2 1 0>; - }; - }; - }; - }; - - rtc_i2c: rtc@32 { - compatible = "epson,rx8130"; - reg = <0x32>; - }; - - temperature-sensor@48 { - compatible = "ti,tmp1075"; - reg = <0x48>; - }; - - eeprom@50 { - compatible = "st,24c02", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -/* SMARC I2C_LCD */ -&lpi2c5 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_lpi2c5>; - pinctrl-1 = <&pinctrl_lpi2c5_gpio>; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -}; - -/* I2C_CAM */ -&lpi2c7 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_lpi2c7>; - pinctrl-1 = <&pinctrl_lpi2c7_gpio>; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - scl-gpios = <&gpio2 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio2 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; - - i2c-mux@70 { - compatible = "nxp,pca9543"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - /* SMARC I2C_CAM0 */ - i2c_cam0: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - /* SMARC I2C_CAM1 */ - i2c_cam1: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -/* SMARC SPI1 */ -&lpspi4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpspi4>; - cs-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>, - <&gpio5 11 GPIO_ACTIVE_LOW>, - <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; - - som_tpm: tpm@2 { - compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; - reg = <0x2>; - spi-max-frequency = <18500000>; - }; -}; - -/* SMARC SPI0 */ -&lpspi6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpspi6>; - cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>, - <&gpio2 24 GPIO_ACTIVE_LOW>; -}; - -/* SMARC SER1, used as the Linux Console */ -&lpuart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -}; - -/* SMARC SER0 */ -&lpuart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; -}; - -/* SMARC SER3 */ -&lpuart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; -}; - -/* SMARC MDIO, shared between all ethernet ports */ -&netc_emdio { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_emdio>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - interrupt-parent = <&som_gpio_expander_1>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - }; - - ethphy2: ethernet-phy@2 { - reg = <2>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - }; -}; - -&netcmix_blk_ctrl { - status = "okay"; -}; - -&netc_blk_ctrl { - status = "okay"; -}; - -&netc_timer { - status = "okay"; -}; - -/* SMARC PCIE_A */ -&pcie0 { - pinctrl-0 = <&pinctrl_pcie0>; - pinctrl-names = "default"; - reset-gpios = <&som_gpio_expander_0 2 GPIO_ACTIVE_LOW>; -}; - -/* SMARC PCIE_B */ -&pcie1 { - pinctrl-0 = <&pinctrl_pcie1>; - pinctrl-names = "default"; - reset-gpios = <&som_gpio_expander_0 1 GPIO_ACTIVE_LOW>; -}; - -/* SMARC I2S0 */ -&sai3 { - #sound-dai-cells = <0>; - assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, - <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, - <&scmi_clk IMX95_CLK_AUDIOPLL1>, - <&scmi_clk IMX95_CLK_AUDIOPLL2>, - <&scmi_clk IMX95_CLK_SAI3>; - assigned-clock-parents = <0>, <0>, <0>, <0>, - <&scmi_clk IMX95_CLK_AUDIOPLL1>; - assigned-clock-rates = <3932160000>, - <3612672000>, <393216000>, - <361267200>, <12288000>; - fsl,sai-mclk-direction-output; -}; - -&thermal_zones { - /* PF09 Main PMIC */ - pf09-thermal { - polling-delay = <2000>; - polling-delay-passive = <250>; - thermal-sensors = <&scmi_sensor 2>; - - trips { - trip0 { - hysteresis = <2000>; - temperature = <155000>; - type = "critical"; - }; - }; - }; - - /* PF53 VDD_ARM PMIC */ - pf53-arm-thermal { - polling-delay = <2000>; - polling-delay-passive = <250>; - thermal-sensors = <&scmi_sensor 4>; - - trips { - trip0 { - hysteresis = <2000>; - temperature = <155000>; - type = "critical"; - }; - }; - }; - - /* PF53 VDD_SOC PMIC */ - pf53-soc-thermal { - polling-delay = <2000>; - polling-delay-passive = <250>; - thermal-sensors = <&scmi_sensor 3>; - - trips { - trip0 { - hysteresis = <2000>; - temperature = <155000>; - type = "critical"; - }; - }; - }; -}; - -/* SMARC LCD0_BKLT_PWM */ -&tpm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd0_bklt_pwm>; -}; - -/* SMARC LCD1_BKLT_PWM */ -&tpm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd1_bklt_pwm>; -}; - -/* SMARC GPIO5 as PWM */ -&tpm5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio5_pwm>; -}; - -/* SMARC USB0 */ -&usb2 { - adp-disable; - dr_mode = "otg"; - hnp-disable; - srp-disable; - usb-role-switch; - vbus-supply = <®_usb0_vbus>; - - port { - usb0_otg_id: endpoint { - remote-endpoint = <&usb_dr_connector>; - }; - }; -}; - -&usb3 { - fsl,disable-port-power-control; -}; - -/* SMARC USB1..4 */ -&usb3_dwc3 { - dr_mode = "host"; -}; - -&usb3_phy { - vbus-supply = <®_usb1_vbus>; -}; - -/* On-module eMMC */ -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - non-removable; - no-sdio; - no-sd; - status = "okay"; -}; - -/* SMARC SDIO */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; - pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_usdhc2_cd>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd>; - cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - vqmmc-supply = <®_usdhc2_vqmmc>; - wp-gpios = <&som_gpio_expander_1 15 GPIO_ACTIVE_HIGH>; -}; - -/* On-module Wi-Fi */ -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - keep-power-in-suspend; - non-removable; - vmmc-supply = <®_wifi_en>; -}; - -&scmi_bbm { - linux,code = <KEY_POWER>; -}; - -&wdog3 { - fsl,ext-reset-output; - status = "okay"; -}; - -&scmi_iomuxc { - /* SMARC CAM_MCK */ - pinctrl_cam_mck: cammckgrp { - fsl,pins = <IMX95_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1 0x51e>; /* SMARC S6 - CAM_MCK */ - }; - - pinctrl_ec_int: ecintgrp { - fsl,pins = <IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x31e>; /* SAI1_TXFS - EC_MCU_INT# */ - }; - - /* SMARC MDIO, shared between all ethernet ports */ - pinctrl_emdio: emdiogrp { - fsl,pins = <IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x50e>, /* SMARC S45 - MDIO_CLK */ - <IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e>; /* SMARC S46 - MDIO_DAT */ - }; - - /* SMARC GBE0 */ - pinctrl_enetc0: enetc0grp { - fsl,pins = <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e>, /* ENET1_TX_CTL */ - <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e>, /* ENET1_TXC */ - <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e>, /* ENET1_TDO */ - <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e>, /* ENET1_TD1 */ - <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e>, /* ENET1_TD2 */ - <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e>, /* ENET1_TD3 */ - <IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e>, /* ENET1_RX_CTL */ - <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e>, /* ENET1_RXC */ - <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e>, /* ENET1_RD0 */ - <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e>, /* ENET1_RD1 */ - <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e>, /* ENET1_RD2 */ - <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e>; /* ENET1_RD3 */ - }; - - /* SMARC GBE0_SDP */ - pinctrl_enetc0_1588_tmr: enetc01588tmrgrp { - fsl,pins = <IMX95_PAD_CCM_CLKO2__NETCMIX_TOP_NETC_TMR_1588_PP1 0x51e>; /* SMARC P6 - GBE0_SDP */ - }; - - /* SMARC GBE1 */ - pinctrl_enetc1: enetc1grp { - fsl,pins = <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e>, /* ENET2_TX_CTL */ - <IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e>, /* ENET2_TXC */ - <IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x50e>, /* ENET2_TD0 */ - <IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x50e>, /* ENET2_TD1 */ - <IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x50e>, /* ENET2_TD2 */ - <IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x50e>, /* ENET2_TD3 */ - <IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e>, /* ENET2_RX_CTL */ - <IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e>, /* ENET2_RXC */ - <IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e>, /* ENET2_RD0 */ - <IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e>, /* ENET2_RD1 */ - <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e>, /* ENET2_RD2 */ - <IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e>; /* ENET2_RD3 */ - }; - - /* SMARC GBE1_SDP */ - pinctrl_enetc1_1588_tmr: enetc11588tmrgrp { - fsl,pins = <IMX95_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2 0x51e>; /* SMARC P5 - GBE1_SDP */ - }; - - /* SMARC CAN0 */ - pinctrl_flexcan1: flexcan1grp { - fsl,pins = <IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e>, /* SMARC P143 - CAN0_TX */ - <IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e>; /* SMARC P144 - CAN0_RX */ - }; - - /* SMARC CAN1 */ - pinctrl_flexcan2: flexcan2grp { - fsl,pins = <IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e>, /* SMARC P145 - CAN1_TX */ - <IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e>; /* SMARC P146 - CAN1_RX */ - }; - - /* SMARC GPIO2 */ - pinctrl_gpio2: gpio2grp { - fsl,pins = <IMX95_PAD_XSPI1_DATA0__GPIO5_IO_BIT0 0x31e>; /* SMARC P110 - GPIO2 */ - }; - - /* SMARC GPIO3 */ - pinctrl_gpio3: gpio3grp { - fsl,pins = <IMX95_PAD_XSPI1_DATA1__GPIO5_IO_BIT1 0x31e>; /* SMARC P111 - GPIO3 */ - }; - - /* SMARC GPIO4 */ - pinctrl_gpio4: gpio4grp { - fsl,pins = <IMX95_PAD_XSPI1_DATA2__GPIO5_IO_BIT2 0x31e>; /* SMARC P112 - GPIO4 */ - }; - - /* SMARC GPIO5 */ - pinctrl_gpio5: gpio5grp { - fsl,pins = <IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6 0x31e>; /* SMARC P113 - GPIO5 */ - }; - - /* SMARC GPIO5 as PWM */ - pinctrl_gpio5_pwm: gpio5pwmgrp { - fsl,pins = <IMX95_PAD_GPIO_IO06__TPM5_CH0 0x11e>; /* SMARC P113 - PWM_OUT */ - }; - - /* SMARC GPIO6 */ - pinctrl_gpio6: gpio6grp { - fsl,pins = <IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 0x31e>; /* SMARC P114 - GPIO6 */ - }; - - /* SMARC GPIO7 */ - pinctrl_gpio7: gpio7grp { - fsl,pins = <IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x31e>; /* SMARC P115 - GPIO7 */ - }; - - /* SMARC GPIO8 */ - pinctrl_gpio8: gpio8grp { - fsl,pins = <IMX95_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10 0x31e>; /* SMARC P116 - GPIO8 */ - }; - - /* SMARC GPIO9 */ - pinctrl_gpio9: gpio9grp { - fsl,pins = <IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8 0x31e>; /* SMARC P117 - GPIO9 */ - }; - - /* SMARC GPIO10 */ - pinctrl_gpio10: gpio10grp { - fsl,pins = <IMX95_PAD_ENET2_MDIO__GPIO4_IO_BIT15 0x31e>; /* SMARC P118 - GPIO10 */ - }; - - /* SMARC GPIO11 */ - pinctrl_gpio11: gpio11grp { - fsl,pins = <IMX95_PAD_ENET2_MDC__GPIO4_IO_BIT14 0x31e>; /* SMARC P119 - GPIO11 */ - }; - - /* SMARC GPIO12 */ - pinctrl_gpio12: gpio12grp { - fsl,pins = <IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10 0x31e>; /* SMARC S142 - GPIO12 */ - }; - - /* SMARC GPIO13 */ - pinctrl_gpio13: gpio13grp { - fsl,pins = <IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x31e>; /* SMARC S123 - GPIO13 */ - }; - - pinctrl_ctrl_io_exp_int_b: ioexpintgrp { - fsl,pins = <IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x31e>; /* CTRL_IO_EXP_INT_B */ - }; - - /* SMARC LCD0_BKLT_PWM */ - pinctrl_lcd0_bklt_pwm: lcd0bkltpwmgrp { - fsl,pins = <IMX95_PAD_GPIO_IO12__TPM3_CH2 0x51e>; /* SMARC S141 - LCD0_BKLT_PWM */ - }; - - /* SMARC LCD1_BKLT_PWM */ - pinctrl_lcd1_bklt_pwm: lcd1bkltpwmgrp { - fsl,pins = <IMX95_PAD_GPIO_IO13__TPM4_CH2 0x51e>; /* SMARC S122 - LCD1_BKLT_PWM */ - }; - - /* SMARC I2C_GP */ - pinctrl_lpi2c2: lpi2c2grp { - fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40001b9e>, /* SMARC S48 - I2C_GP_CK */ - <IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40001b9e>; /* SMARC S49 - I2C_GP_DAT */ - }; - - /* SMARC I2C_GP as GPIOs */ - pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { - fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2 0x40001b9e>, /* SMARC S48 - I2C_GP_CK */ - <IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3 0x40001b9e>; /* SMARC S49 - I2C_GP_DAT */ - }; - - /* SMARC I2C_PM */ - pinctrl_lpi2c3: lpi2c3grp { - fsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40001b9e>, /* SMARC P122 - I2C_PM_DAT */ - <IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40001b9e>; /* SMARC P121 - I2C_PM_CK */ - }; - - /* SMARC I2C_PM as GPIOs */ - pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { - fsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x40001b9e>, /* SMARC P122 - I2C_PM_DAT */ - <IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x40001b9e>; /* SMARC P121 - I2C_PM_CK */ - }; - - /* I2C_SOM */ - pinctrl_lpi2c4: lpi2c4grp { - fsl,pins = <IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40001b9e>, /* I2C_SOM_CK */ - <IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40001b9e>; /* I2C_SOM_DAT */ - }; - - /* I2C_SOM as GPIOs */ - pinctrl_lpi2c4_gpio: lpi2c4gpiogrp { - fsl,pins = <IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x40001b9e>, /* I2C_SOM_CK */ - <IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x40001b9e>; /* I2C_SOM_DAT */ - }; - - /* SMARC I2C_LCD */ - pinctrl_lpi2c5: lpi2c5grp { - fsl,pins = <IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40001b9e>, /* SMARC S140 - I2C_LCD_DAT */ - <IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40001b9e>; /* SMARC S139 - I2C_LCD_CK */ - }; - - /* SMARC I2C_LCD as GPIOs */ - pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { - fsl,pins = <IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x40001b9e>, /* SMARC S140 - I2C_LCD_DAT */ - <IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x40001b9e>; /* SMARC S139 - I2C_LCD_CK */ - }; - - /* I2C_CAM */ - pinctrl_lpi2c7: lpi2c7grp { - fsl,pins = <IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x40001b9e>, /* I2C_CAM_DAT */ - <IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x40001b9e>; /* I2C_CAM_CK */ - }; - - /* I2C_CAM as GPIOs */ - pinctrl_lpi2c7_gpio: lpi2c7gpiogrp { - fsl,pins = <IMX95_PAD_GPIO_IO08__GPIO2_IO_BIT8 0x40001b9e>, /* I2C_CAM_DAT */ - <IMX95_PAD_GPIO_IO09__GPIO2_IO_BIT9 0x40001b9e>; /* I2C_CAM_CK */ - }; - - /* SMARC SPI1 */ - pinctrl_lpspi4: lpspi4grp { - fsl,pins = <IMX95_PAD_GPIO_IO37__LPSPI4_SCK 0x3fe>, /* SMARC P56 - SPI1_CK */ - <IMX95_PAD_GPIO_IO36__LPSPI4_SOUT 0x3fe>, /* SMARC P58 - SPI1_DO */ - <IMX95_PAD_GPIO_IO19__LPSPI4_SIN 0x3fe>, /* SMARC P57 - SPI1_DIN */ - <IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x3fe>, /* SPI1_TPM_CS# */ - <IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x3fe>, /* SMARC P54 - SPI1_CS0# */ - <IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x3fe>; /* SMARC P55 - SPI1_CS1# */ - }; - - /* SMARC SPI0 */ - pinctrl_lpspi6: lpspi6grp { - fsl,pins = <IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0 0x3fe>, /* SMARC P43 - SPI0_CS0# */ - <IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x3fe>, /* SMARC P31 - SPI0_CS1# */ - <IMX95_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe>, /* SMARC P45 - SPI0_DIN */ - <IMX95_PAD_GPIO_IO02__LPSPI6_SOUT 0x3fe>, /* SMARC P46 - SPI0_DO */ - <IMX95_PAD_GPIO_IO03__LPSPI6_SCK 0x3fe>; /* SMARC P44 - SPI0_CK */ - }; - - /* SMARC PCIE_A */ - pinctrl_pcie0: pcie0grp { - fsl,pins = <IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x40001b1e>; /* SMARC P78 - PCIE_A_CKREQ# */ - }; - - /* SMARC PCIE_B */ - pinctrl_pcie1: pcie1grp { - fsl,pins = <IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x40001b1e>; /* SMARC P77 - PCIE_B_CKREQ# */ - }; - - /* SMARC I2S0 */ - pinctrl_sai3: sai3grp { - fsl,pins = <IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x11e>, /* SMARC S38 - I2S0_CK */ - <IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x11e>, /* SMARC S41 - I2S0_SDIN */ - <IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x11e>, /* SMARC S40 - I2S0_SDOUT */ - <IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x11e>; /* SMARC S39 - I2S0_LRCK */ - }; - - /* SMARC AUDIO_MCK */ - pinctrl_sai3_mclk: sai3mclkgrp { - fsl,pins = <IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e>; /* SMARC S42 - AUDIO_MCK */ - }; - - /* SMARC I2S2 */ - pinctrl_sai5: sai5grp { - fsl,pins = <IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x11e>, /* SMARC S53 - I2S2_CK */ - <IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x11e>, /* SMARC S51 - I2S2_SDOUT */ - <IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x11e>, /* SMARC S52 - I2S2_SDIN */ - <IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x11e>; /* SMARC S50 - I2S2_LRCK */ - }; - - /* SMARC SMB_ALERT# */ - pinctrl_smb_alert_gpio: smbalertgrp { - fsl,pins = <IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x31e>; /* SMARC P1 - SMB_ALERT# */ - }; - - /* SMARC SER1, used as the Linux Console */ - pinctrl_uart1: uart1grp { - fsl,pins = <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e>, /* SMARC P134 - SER1_TX */ - <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e>; /* SMARC P135 - SER1_RX */ - }; - - /* SMARC SER0 */ - pinctrl_uart2: uart2grp { - fsl,pins = <IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART2_CTS_B 0x31e>, /* SMARC P132 - SER0_CTS# */ - <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART2_RTS_B 0x31e>, /* SMARC P131 - SER0_RTS# */ - <IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x31e>, /* SMARC P130 - SER0_RX */ - <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x31e>; /* SMARC P129 - SER0_TX */ - }; - - /* SMARC SER3 */ - pinctrl_uart3: uart3grp { - fsl,pins = <IMX95_PAD_GPIO_IO14__LPUART3_TX 0x31e>, /* SMARC P140 - SER3_TX */ - <IMX95_PAD_GPIO_IO15__LPUART3_RX 0x31e>; /* SMARC P141 - SER3_RX */ - }; - - /* On-module eMMC */ - pinctrl_usdhc1: usdhc1grp { - fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>, /* SD1_CLK */ - <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>, /* SD1_CMD */ - <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>, /* SD1_DATA0 */ - <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>, /* SD1_DATA1 */ - <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>, /* SD1_DATA2 */ - <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>, /* SD1_DATA3 */ - <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>, /* SD1_DATA4 */ - <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>, /* SD1_DATA5 */ - <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>, /* SD1_DATA6 */ - <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>, /* SD1_DATA7 */ - <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>; /* SD1_STROBE */ - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe>, /* SD1_CLK */ - <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe>, /* SD1_CMD */ - <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe>, /* SD1_DATA0 */ - <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe>, /* SD1_DATA1 */ - <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe>, /* SD1_DATA2 */ - <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe>, /* SD1_DATA3 */ - <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe>, /* SD1_DATA4 */ - <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe>, /* SD1_DATA5 */ - <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe>, /* SD1_DATA6 */ - <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe>, /* SD1_DATA7 */ - <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe>; /* SD1_STROBE */ - }; - - /* SMARC SDIO */ - pinctrl_usdhc2: usdhc2grp { - fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e>, /* SMARC P36 - SDIO_CK */ - <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e>, /* SMARC P34 - SDIO_CMD */ - <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>, /* SMARC P39 - SDIO_D0 */ - <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>, /* SMARC P40 - SDIO_D1 */ - <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>, /* SMARC P41 - SDIO_D2 */ - <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>; /* SMARC P42 - SDIO_D3 */ - }; - - /* SMARC SDIO */ - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe>, /* SMARC P36 - SDIO_CK */ - <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe>, /* SMARC P34 - SDIO_CMD */ - <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe>, /* SMARC P39 - SDIO_D0 */ - <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe>, /* SMARC P40 - SDIO_D1 */ - <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe>, /* SMARC P41 - SDIO_D2 */ - <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe>; /* SMARC P42 - SDIO_D3 */ - }; - - /* SMARC SDIO */ - pinctrl_usdhc2_sleep: usdhc2-sleepgrp { - fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x400>, /* SMARC P36 - SDIO_CK */ - <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x400>, /* SMARC P34 - SDIO_CMD */ - <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x400>, /* SMARC P39 - SDIO_D0 */ - <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x400>, /* SMARC P40 - SDIO_D1 */ - <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x400>, /* SMARC P41 - SDIO_D2 */ - <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x400>; /* SMARC P42 - SDIO_D3 */ - }; - - /* SMARC SDIO_CD# */ - pinctrl_usdhc2_cd: usdhc2-cdgrp { - fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>; /* SMARC P35 - SDIO_CD# */ - }; - - /* SMARC SDIO_PWR_EN */ - pinctrl_usdhc2_pwr_en: usdhc2-pwrengrp { - fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x11e>; /* SMARC P37 - SDIO_PWR_EN */ - }; - - pinctrl_usdhc2_vsel: usdhc2-vselgrp { - fsl,pins = <IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19 0x4>; /* PMIC_SD2_VSEL */ - }; - - /* On-module Wi-Fi */ - pinctrl_usdhc3: usdhc3grp { - fsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e>, /* SD3_CLK */ - <IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e>, /* SD3_CMD */ - <IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e>, /* SD3_DATA0 */ - <IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e>, /* SD3_DATA1 */ - <IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e>, /* SD3_DATA2 */ - <IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e>; /* SD3_DATA3 */ - }; - - /* On-module Wi-Fi */ - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe>, /* SD3_CLK */ - <IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe>, /* SD3_CMD */ - <IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe>, /* SD3_DATA1 */ - <IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe>, /* SD3_DATA2 */ - <IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe>, /* SD3_DATA3 */ - <IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe>; /* SD3_DATA4 */ - }; -}; diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 6e0958c0842..2308457df23 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -129,6 +129,14 @@ config TARGET_KONTRON_MX93 Kontron Electronics BL i.MX93 using SoM module conformant to OSM standard 1.1 size S. +config TARGET_PHYCORE_IMX91 + bool "phycore_imx91" + select IMX91 + select IMX9_LPDDR4X + imply OF_UPSTREAM + select OF_BOARD_FIXUP + select OF_BOARD_SETUP + config TARGET_PHYCORE_IMX93 bool "phycore_imx93" select IMX93 @@ -161,6 +169,7 @@ config TARGET_IMX943_EVK config TARGET_TORADEX_SMARC_IMX95 bool "Support Toradex SMARC iMX95" select IMX95 + imply OF_UPSTREAM config TARGET_IMX952_EVK bool "imx952_evk" @@ -181,7 +190,7 @@ source "board/nxp/imx93_evk/Kconfig" source "board/nxp/imx93_frdm/Kconfig" source "board/nxp/imx93_qsb/Kconfig" source "board/kontron/osm-s-mx93/Kconfig" -source "board/phytec/phycore_imx93/Kconfig" +source "board/phytec/phycore_imx91_93/Kconfig" source "board/variscite/imx93_var_som/Kconfig" source "board/nxp/imx94_evk/Kconfig" source "board/nxp/imx95_evk/Kconfig" diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 583c3a5a464..44b3e0f5310 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -664,7 +664,8 @@ int low_drive_freq_update(void *blob) return 0; } -#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_TARGET_PHYCORE_IMX93) +#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_TARGET_PHYCORE_IMX93) && \ + !defined(CONFIG_TARGET_PHYCORE_IMX91) #ifndef CONFIG_XPL_BUILD int board_fix_fdt(void *fdt) { diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index f64bebfc14b..1eda90ad9b7 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -419,7 +419,6 @@ config TARGET_MX6SXSABRESD config TARGET_MX6SXSABREAUTO bool "mx6sxsabreauto" depends on MX6SX - select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select DM select DM_THERMAL diff --git a/board/dhelectronics/dh_imx8mp/Makefile b/board/dhelectronics/dh_imx8mp/Makefile index 7bc8dc21e64..12fb7b71ab6 100644 --- a/board/dhelectronics/dh_imx8mp/Makefile +++ b/board/dhelectronics/dh_imx8mp/Makefile @@ -5,7 +5,7 @@ # ifdef CONFIG_XPL_BUILD -obj-y += spl.o lpddr4_timing_2G_32.o lpddr4_timing_4G_32.o +obj-y += spl.o lpddr4_timing_2G_32.o else obj-y += imx8mp_dhcom_pdk2.o endif diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c index 3fe98d36f5b..3424be10936 100644 --- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c +++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c @@ -28,12 +28,11 @@ int mach_cpu_init(void) int board_phys_sdram_size(phys_size_t *size) { - const u16 memsz[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 }; const u8 ecc = readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK; u8 memcfg = dh_get_memcfg(); /* 896 kiB, i.e. 1 MiB without 12.5% reserved for in-band ECC */ - *size = (u64)memsz[memcfg] * (SZ_1M - (ecc ? (SZ_1M / 8) : 0)); + *size = (u64)dh_imx8mp_dhcom_dram_size[memcfg] * (SZ_1M - (ecc ? (SZ_1M / 8) : 0)); return 0; } diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing.h b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h index c4d51174a33..5dc841a7f5a 100644 --- a/board/dhelectronics/dh_imx8mp/lpddr4_timing.h +++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h @@ -6,12 +6,16 @@ #ifndef __LPDDR4_TIMING_H__ #define __LPDDR4_TIMING_H__ -extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32; -extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32; +static const u16 dh_imx8mp_dhcom_dram_size[] = { + 4096, 1024, 1536, 2048, 3072, 4096, 6144, 8192 +}; -typedef void (*scrub_func_t)(void); -extern void dh_imx8mp_dhcom_dram_scrub_16g_x32(void); -extern void dh_imx8mp_dhcom_dram_scrub_32g_x32(void); +extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32; +static __maybe_unused struct dram_timing_info *dh_imx8mp_dhcom_dram_timing = + &dh_imx8mp_dhcom_dram_timing_16g_x32; +void dh_imx8mp_dhcom_dram_patch_16g_x32_to_16g_x32(void); +void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_2r(void); +void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_1r(void); u8 dh_get_memcfg(void); diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c b/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c index add7a0bf23b..9574e920352 100644 --- a/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c +++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c @@ -1854,16 +1854,197 @@ struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32 = { .fsp_table = { 3600, 400, 100, }, }; -#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) -void dh_imx8mp_dhcom_dram_scrub_16g_x32(void) +/* + * Convert 2 GiB DRAM settings to 2 GiB DRAM settings. + * This does nothing and is only a placeholder to indicate + * that the 2 GiB DRAM settings are valid themselves. + */ +void dh_imx8mp_dhcom_dram_patch_16g_x32_to_16g_x32(void) { - ddrc_inline_ecc_scrub(0x0,0x3ffffff); - ddrc_inline_ecc_scrub(0x4000000,0x7ffffff); - ddrc_inline_ecc_scrub(0x8000000,0xbffffff); - ddrc_inline_ecc_scrub(0xc000000,0xfffffff); - ddrc_inline_ecc_scrub(0x10000000,0x13ffffff); - ddrc_inline_ecc_scrub(0x14000000,0x17ffffff); - ddrc_inline_ecc_scrub(0x18000000,0x1bffffff); - ddrc_inline_ecc_scrub_end(0x0,0x1fffffff); } + +/* Convert 2 GiB DRAM settings to 4 GiB 2-rank DRAM settings. */ +void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_2r(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(ddr_ddrc_cfg); i++) { + if (ddr_ddrc_cfg[i].reg == 0x3d400000) + ddr_ddrc_cfg[i].val = 0xa3080020; +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) + if (ddr_ddrc_cfg[i].reg == 0x3d400200) + ddr_ddrc_cfg[i].val = 0x14; + if (ddr_ddrc_cfg[i].reg == 0x3d40020c) + ddr_ddrc_cfg[i].val = 0x14141400; +#else + if (ddr_ddrc_cfg[i].reg == 0x3d400200) + ddr_ddrc_cfg[i].val = 0x17; +#endif + } + + for (i = 0; i < ARRAY_SIZE(ddr_fsp0_cfg); i++) { + if (ddr_fsp0_cfg[i].reg == 0x54012) + ddr_fsp0_cfg[i].val = 0x310; + if (ddr_fsp0_cfg[i].reg == 0x5402c) + ddr_fsp0_cfg[i].val = 0x3; + } + + for (i = 0; i < ARRAY_SIZE(ddr_fsp1_cfg); i++) { + if (ddr_fsp1_cfg[i].reg == 0x54012) + ddr_fsp1_cfg[i].val = 0x310; + if (ddr_fsp1_cfg[i].reg == 0x5402c) + ddr_fsp1_cfg[i].val = 0x3; + } + + for (i = 0; i < ARRAY_SIZE(ddr_fsp2_cfg); i++) { + if (ddr_fsp2_cfg[i].reg == 0x54012) + ddr_fsp2_cfg[i].val = 0x310; + if (ddr_fsp2_cfg[i].reg == 0x5402c) + ddr_fsp2_cfg[i].val = 0x3; + } + + for (i = 0; i < ARRAY_SIZE(ddr_fsp0_2d_cfg); i++) { + if (ddr_fsp0_2d_cfg[i].reg == 0x54012) + ddr_fsp0_2d_cfg[i].val = 0x310; + if (ddr_fsp0_2d_cfg[i].reg == 0x5402c) + ddr_fsp0_2d_cfg[i].val = 0x3; + } +}; + +/* Convert 2 GiB DRAM settings to 4 GiB 1-rank DRAM settings. */ +void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_1r(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(ddr_ddrc_cfg); i++) { + if (ddr_ddrc_cfg[i].reg == 0x3d400064) + ddr_ddrc_cfg[i].val = 0x6d0156; + if (ddr_ddrc_cfg[i].reg == 0x3d400138) + ddr_ddrc_cfg[i].val = 0x15d; +#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) + if (ddr_ddrc_cfg[i].reg == 0x3d400200) + ddr_ddrc_cfg[i].val = 0x1f; + if (ddr_ddrc_cfg[i].reg == 0x3d40020c) + ddr_ddrc_cfg[i].val = 0x14141400; +#else + if (ddr_ddrc_cfg[i].reg == 0x3d400200) + ddr_ddrc_cfg[i].val = 0x17; #endif + if (ddr_ddrc_cfg[i].reg == 0x3d40021c) + ddr_ddrc_cfg[i].val = 0xf04; + if (ddr_ddrc_cfg[i].reg == 0x3d402024) + ddr_ddrc_cfg[i].val = 0x61a800; + if (ddr_ddrc_cfg[i].reg == 0x3d402064) + ddr_ddrc_cfg[i].val = 0x18004c; + if (ddr_ddrc_cfg[i].reg == 0x3d4020dc) + ddr_ddrc_cfg[i].val = 0x940009; + if (ddr_ddrc_cfg[i].reg == 0x3d402100) + ddr_ddrc_cfg[i].val = 0xc080609; + if (ddr_ddrc_cfg[i].reg == 0x3d402104) + ddr_ddrc_cfg[i].val = 0x3040d; + if (ddr_ddrc_cfg[i].reg == 0x3d402108) + ddr_ddrc_cfg[i].val = 0x3060a0c; + if (ddr_ddrc_cfg[i].reg == 0x3d402110) + ddr_ddrc_cfg[i].val = 0x4040204; + if (ddr_ddrc_cfg[i].reg == 0x3d402114) + ddr_ddrc_cfg[i].val = 0x2030303; + if (ddr_ddrc_cfg[i].reg == 0x3d402138) + ddr_ddrc_cfg[i].val = 0x4e; + if (ddr_ddrc_cfg[i].reg == 0x3d402144) + ddr_ddrc_cfg[i].val = 0x280014; + if (ddr_ddrc_cfg[i].reg == 0x3d402180) + ddr_ddrc_cfg[i].val = 0xc80006; + if (ddr_ddrc_cfg[i].reg == 0x3d402190) + ddr_ddrc_cfg[i].val = 0x3878202; + if (ddr_ddrc_cfg[i].reg == 0x3d4021b4) + ddr_ddrc_cfg[i].val = 0x702; + if (ddr_ddrc_cfg[i].reg == 0x3d403024) + ddr_ddrc_cfg[i].val = 0x493fe1; + if (ddr_ddrc_cfg[i].reg == 0x3d403064) + ddr_ddrc_cfg[i].val = 0x12003a; + if (ddr_ddrc_cfg[i].reg == 0x3d403100) + ddr_ddrc_cfg[i].val = 0xa070507; + if (ddr_ddrc_cfg[i].reg == 0x3d403104) + ddr_ddrc_cfg[i].val = 0x3040a; + if (ddr_ddrc_cfg[i].reg == 0x3d403108) + ddr_ddrc_cfg[i].val = 0x203070b; + if (ddr_ddrc_cfg[i].reg == 0x3d403110) + ddr_ddrc_cfg[i].val = 0x3040203; + if (ddr_ddrc_cfg[i].reg == 0x3d403114) + ddr_ddrc_cfg[i].val = 0x2030303; + if (ddr_ddrc_cfg[i].reg == 0x3d403138) + ddr_ddrc_cfg[i].val = 0x3b; + if (ddr_ddrc_cfg[i].reg == 0x3d403144) + ddr_ddrc_cfg[i].val = 0x1f0010; + if (ddr_ddrc_cfg[i].reg == 0x3d403180) + ddr_ddrc_cfg[i].val = 0x970005; + } + + for (i = 0; i < ARRAY_SIZE(ddr_ddrphy_cfg); i++) { + if (ddr_ddrphy_cfg[i].reg == 0x12002e) + ddr_ddrphy_cfg[i].val = 0x1; + if (ddr_ddrphy_cfg[i].reg == 0x22002e) + ddr_ddrphy_cfg[i].val = 0x1; + if (ddr_ddrphy_cfg[i].reg == 0x120008) + ddr_ddrphy_cfg[i].val = 0xc8; + if (ddr_ddrphy_cfg[i].reg == 0x220008) + ddr_ddrphy_cfg[i].val = 0x96; + if (ddr_ddrphy_cfg[i].reg == 0x200f0) + ddr_ddrphy_cfg[i].val = 0x500; + if (ddr_ddrphy_cfg[i].reg == 0x200f4) + ddr_ddrphy_cfg[i].val = 0x5555; + } + + for (i = 0; i < ARRAY_SIZE(ddr_fsp1_cfg); i++) { + if (ddr_fsp1_cfg[i].reg == 0x54002) + ddr_fsp1_cfg[i].val = 0x1; + if (ddr_fsp1_cfg[i].reg == 0x54003) + ddr_fsp1_cfg[i].val = 0x320; + if (ddr_fsp1_cfg[i].reg == 0x54019) + ddr_fsp1_cfg[i].val = 0x994; + if (ddr_fsp1_cfg[i].reg == 0x5401f) + ddr_fsp1_cfg[i].val = 0x994; + if (ddr_fsp1_cfg[i].reg == 0x54032) + ddr_fsp1_cfg[i].val = 0x9400; + if (ddr_fsp1_cfg[i].reg == 0x54033) + ddr_fsp1_cfg[i].val = 0xf309; + if (ddr_fsp1_cfg[i].reg == 0x54038) + ddr_fsp1_cfg[i].val = 0x9400; + if (ddr_fsp1_cfg[i].reg == 0x54039) + ddr_fsp1_cfg[i].val = 0xf309; + } + + for (i = 0; i < ARRAY_SIZE(ddr_fsp2_cfg); i++) { + if (ddr_fsp2_cfg[i].reg == 0x54002) + ddr_fsp2_cfg[i].val = 0x2; + if (ddr_fsp2_cfg[i].reg == 0x54003) + ddr_fsp2_cfg[i].val = 0x258; + if (ddr_fsp2_cfg[i].reg == 0x54019) + ddr_fsp2_cfg[i].val = 0x994; + if (ddr_fsp2_cfg[i].reg == 0x5401f) + ddr_fsp2_cfg[i].val = 0x994; + if (ddr_fsp2_cfg[i].reg == 0x54032) + ddr_fsp2_cfg[i].val = 0x9400; + if (ddr_fsp2_cfg[i].reg == 0x54033) + ddr_fsp2_cfg[i].val = 0xf309; + if (ddr_fsp2_cfg[i].reg == 0x54038) + ddr_fsp2_cfg[i].val = 0x9400; + if (ddr_fsp2_cfg[i].reg == 0x54039) + ddr_fsp2_cfg[i].val = 0xf309; + } + + for (i = 0; i < ARRAY_SIZE(ddr_phy_pie); i++) { + if (ddr_phy_pie[i].reg == 0x12000b) + ddr_phy_pie[i].val = 0xe1; + if (ddr_phy_pie[i].reg == 0x12000c) + ddr_phy_pie[i].val = 0x32; + if (ddr_phy_pie[i].reg == 0x12000d) + ddr_phy_pie[i].val = 0x1f4; + if (ddr_phy_pie[i].reg == 0x22000b) + ddr_phy_pie[i].val = 0xa8; + if (ddr_phy_pie[i].reg == 0x22000c) + ddr_phy_pie[i].val = 0x25; + if (ddr_phy_pie[i].reg == 0x22000d) + ddr_phy_pie[i].val = 0x177; + } +}; diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c b/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c deleted file mode 100644 index 41b078f6e9f..00000000000 --- a/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c +++ /dev/null @@ -1,1873 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2022 Marek Vasut <[email protected]> - * - * Generated code from MX8M_DDR_tool - */ - -#include <linux/kernel.h> -#include <asm/arch/ddr.h> - -static struct dram_cfg_param ddr_ddrc_cfg[] = { - /** Initialize DDRC registers **/ - { 0x3d400304, 0x1 }, - { 0x3d400030, 0x1 }, - { 0x3d400000, 0xa3080020 }, - { 0x3d400020, 0x1323 }, - { 0x3d400024, 0x1b77400 }, - { 0x3d400064, 0x6d00fc }, -#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) - { 0x3d400070, 0x7027fd4 }, -#else - { 0x3d400070, 0x7027f90 }, -#endif - { 0x3d400074, 0x790 }, - { 0x3d4000d0, 0xc00306df }, - { 0x3d4000d4, 0xb10000 }, - { 0x3d4000dc, 0xe40036 }, - { 0x3d4000e0, 0xf30000 }, - { 0x3d4000e8, 0x660048 }, - { 0x3d4000ec, 0x160048 }, - { 0x3d400100, 0x1d241e26 }, - { 0x3d400104, 0x70739 }, - { 0x3d40010c, 0xd0d000 }, - { 0x3d400110, 0x11040911 }, - { 0x3d400114, 0x2050e0e }, - { 0x3d400118, 0x1010008 }, - { 0x3d40011c, 0x502 }, - { 0x3d400130, 0x20700 }, - { 0x3d400134, 0xd100002 }, - { 0x3d400138, 0x103 }, - { 0x3d400144, 0xb4005a }, - { 0x3d400180, 0x384001b }, - { 0x3d400184, 0x2d06ddd }, - { 0x3d400188, 0x0 }, - { 0x3d400190, 0x49f820c }, - { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x1f0c }, - { 0x3d4001a0, 0xe0400018 }, - { 0x3d4001a4, 0xdf00e4 }, - { 0x3d4001a8, 0x80000000 }, - { 0x3d4001b0, 0x11 }, - { 0x3d4001c0, 0x7 }, - { 0x3d4001c4, 0x1 }, - { 0x3d4000f4, 0x799 }, - { 0x3d400108, 0x8121b1a }, -#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) - { 0x3d400200, 0x14 }, -#else - { 0x3d400200, 0x17 }, -#endif - { 0x3d400208, 0x0 }, -#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) - { 0x3d40020c, 0x14141400 }, -#else - { 0x3d40020c, 0x0 }, -#endif - { 0x3d400210, 0x1f1f }, -#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) - { 0x3d400204, 0x50505 }, - { 0x3d400214, 0x4040404 }, - { 0x3d400218, 0x4040404 }, -#else - { 0x3d400204, 0x80808 }, - { 0x3d400214, 0x7070707 }, - { 0x3d400218, 0x7070707 }, -#endif - { 0x3d40021c, 0xf0f }, - { 0x3d400250, 0x1705 }, - { 0x3d400254, 0x2c }, - { 0x3d40025c, 0x4000030 }, - { 0x3d400264, 0x900093e7 }, - { 0x3d40026c, 0x2005574 }, - { 0x3d400400, 0x111 }, - { 0x3d400404, 0x72ff }, - { 0x3d400408, 0x72ff }, - { 0x3d400494, 0x2100e07 }, - { 0x3d400498, 0x620096 }, - { 0x3d40049c, 0x1100e07 }, - { 0x3d4004a0, 0xc8012c }, - { 0x3d402020, 0x1021 }, - { 0x3d402024, 0x30d400 }, - { 0x3d402050, 0x20d000 }, - { 0x3d402064, 0xc001c }, - { 0x3d4020dc, 0x840000 }, - { 0x3d4020e0, 0xf30000 }, - { 0x3d4020e8, 0x660048 }, - { 0x3d4020ec, 0x160048 }, - { 0x3d402100, 0xa040305 }, - { 0x3d402104, 0x30407 }, - { 0x3d402108, 0x203060b }, - { 0x3d40210c, 0x505000 }, - { 0x3d402110, 0x2040202 }, - { 0x3d402114, 0x2030202 }, - { 0x3d402118, 0x1010004 }, - { 0x3d40211c, 0x302 }, - { 0x3d402130, 0x20300 }, - { 0x3d402134, 0xa100002 }, - { 0x3d402138, 0x1d }, - { 0x3d402144, 0x14000a }, - { 0x3d402180, 0x640004 }, - { 0x3d402190, 0x3818200 }, - { 0x3d402194, 0x80303 }, - { 0x3d4021b4, 0x100 }, - { 0x3d4020f4, 0x599 }, - { 0x3d403020, 0x1021 }, - { 0x3d403024, 0xc3500 }, - { 0x3d403050, 0x20d000 }, - { 0x3d403064, 0x30007 }, - { 0x3d4030dc, 0x840000 }, - { 0x3d4030e0, 0xf30000 }, - { 0x3d4030e8, 0x660048 }, - { 0x3d4030ec, 0x160048 }, - { 0x3d403100, 0xa010102 }, - { 0x3d403104, 0x30404 }, - { 0x3d403108, 0x203060b }, - { 0x3d40310c, 0x505000 }, - { 0x3d403110, 0x2040202 }, - { 0x3d403114, 0x2030202 }, - { 0x3d403118, 0x1010004 }, - { 0x3d40311c, 0x302 }, - { 0x3d403130, 0x20300 }, - { 0x3d403134, 0xa100002 }, - { 0x3d403138, 0x8 }, - { 0x3d403144, 0x50003 }, - { 0x3d403180, 0x190004 }, - { 0x3d403190, 0x3818200 }, - { 0x3d403194, 0x80303 }, - { 0x3d4031b4, 0x100 }, - { 0x3d4030f4, 0x599 }, - { 0x3d400028, 0x0 }, -}; - -/* PHY Initialize Configuration */ -static struct dram_cfg_param ddr_ddrphy_cfg[] = { - { 0x100a0, 0x0 }, - { 0x100a1, 0x1 }, - { 0x100a2, 0x2 }, - { 0x100a3, 0x3 }, - { 0x100a4, 0x4 }, - { 0x100a5, 0x5 }, - { 0x100a6, 0x6 }, - { 0x100a7, 0x7 }, - { 0x110a0, 0x0 }, - { 0x110a1, 0x1 }, - { 0x110a2, 0x3 }, - { 0x110a3, 0x4 }, - { 0x110a4, 0x5 }, - { 0x110a5, 0x2 }, - { 0x110a6, 0x7 }, - { 0x110a7, 0x6 }, - { 0x120a0, 0x0 }, - { 0x120a1, 0x1 }, - { 0x120a2, 0x3 }, - { 0x120a3, 0x2 }, - { 0x120a4, 0x5 }, - { 0x120a5, 0x4 }, - { 0x120a6, 0x7 }, - { 0x120a7, 0x6 }, - { 0x130a0, 0x0 }, - { 0x130a1, 0x1 }, - { 0x130a2, 0x2 }, - { 0x130a3, 0x3 }, - { 0x130a4, 0x4 }, - { 0x130a5, 0x5 }, - { 0x130a6, 0x6 }, - { 0x130a7, 0x7 }, - { 0x1005f, 0x1ff }, - { 0x1015f, 0x1ff }, - { 0x1105f, 0x1ff }, - { 0x1115f, 0x1ff }, - { 0x1205f, 0x1ff }, - { 0x1215f, 0x1ff }, - { 0x1305f, 0x1ff }, - { 0x1315f, 0x1ff }, - { 0x11005f, 0x1ff }, - { 0x11015f, 0x1ff }, - { 0x11105f, 0x1ff }, - { 0x11115f, 0x1ff }, - { 0x11205f, 0x1ff }, - { 0x11215f, 0x1ff }, - { 0x11305f, 0x1ff }, - { 0x11315f, 0x1ff }, - { 0x21005f, 0x1ff }, - { 0x21015f, 0x1ff }, - { 0x21105f, 0x1ff }, - { 0x21115f, 0x1ff }, - { 0x21205f, 0x1ff }, - { 0x21215f, 0x1ff }, - { 0x21305f, 0x1ff }, - { 0x21315f, 0x1ff }, - { 0x55, 0x1ff }, - { 0x1055, 0x1ff }, - { 0x2055, 0x1ff }, - { 0x3055, 0x1ff }, - { 0x4055, 0x1ff }, - { 0x5055, 0x1ff }, - { 0x6055, 0x1ff }, - { 0x7055, 0x1ff }, - { 0x8055, 0x1ff }, - { 0x9055, 0x1ff }, - { 0x200c5, 0x19 }, - { 0x1200c5, 0x7 }, - { 0x2200c5, 0x7 }, - { 0x2002e, 0x2 }, - { 0x12002e, 0x2 }, - { 0x22002e, 0x2 }, - { 0x90204, 0x0 }, - { 0x190204, 0x0 }, - { 0x290204, 0x0 }, - { 0x20024, 0x1e3 }, - { 0x2003a, 0x2 }, - { 0x120024, 0x1e3 }, - { 0x2003a, 0x2 }, - { 0x220024, 0x1e3 }, - { 0x2003a, 0x2 }, - { 0x20056, 0x3 }, - { 0x120056, 0x3 }, - { 0x220056, 0x3 }, - { 0x1004d, 0xe00 }, - { 0x1014d, 0xe00 }, - { 0x1104d, 0xe00 }, - { 0x1114d, 0xe00 }, - { 0x1204d, 0xe00 }, - { 0x1214d, 0xe00 }, - { 0x1304d, 0xe00 }, - { 0x1314d, 0xe00 }, - { 0x11004d, 0xe00 }, - { 0x11014d, 0xe00 }, - { 0x11104d, 0xe00 }, - { 0x11114d, 0xe00 }, - { 0x11204d, 0xe00 }, - { 0x11214d, 0xe00 }, - { 0x11304d, 0xe00 }, - { 0x11314d, 0xe00 }, - { 0x21004d, 0xe00 }, - { 0x21014d, 0xe00 }, - { 0x21104d, 0xe00 }, - { 0x21114d, 0xe00 }, - { 0x21204d, 0xe00 }, - { 0x21214d, 0xe00 }, - { 0x21304d, 0xe00 }, - { 0x21314d, 0xe00 }, - { 0x10049, 0xeba }, - { 0x10149, 0xeba }, - { 0x11049, 0xeba }, - { 0x11149, 0xeba }, - { 0x12049, 0xeba }, - { 0x12149, 0xeba }, - { 0x13049, 0xeba }, - { 0x13149, 0xeba }, - { 0x110049, 0xeba }, - { 0x110149, 0xeba }, - { 0x111049, 0xeba }, - { 0x111149, 0xeba }, - { 0x112049, 0xeba }, - { 0x112149, 0xeba }, - { 0x113049, 0xeba }, - { 0x113149, 0xeba }, - { 0x210049, 0xeba }, - { 0x210149, 0xeba }, - { 0x211049, 0xeba }, - { 0x211149, 0xeba }, - { 0x212049, 0xeba }, - { 0x212149, 0xeba }, - { 0x213049, 0xeba }, - { 0x213149, 0xeba }, - { 0x43, 0x63 }, - { 0x1043, 0x63 }, - { 0x2043, 0x63 }, - { 0x3043, 0x63 }, - { 0x4043, 0x63 }, - { 0x5043, 0x63 }, - { 0x6043, 0x63 }, - { 0x7043, 0x63 }, - { 0x8043, 0x63 }, - { 0x9043, 0x63 }, - { 0x20018, 0x3 }, - { 0x20075, 0x4 }, - { 0x20050, 0x0 }, - { 0x20008, 0x384 }, - { 0x120008, 0x64 }, - { 0x220008, 0x19 }, - { 0x20088, 0x9 }, - { 0x200b2, 0x104 }, - { 0x10043, 0x5a1 }, - { 0x10143, 0x5a1 }, - { 0x11043, 0x5a1 }, - { 0x11143, 0x5a1 }, - { 0x12043, 0x5a1 }, - { 0x12143, 0x5a1 }, - { 0x13043, 0x5a1 }, - { 0x13143, 0x5a1 }, - { 0x1200b2, 0x104 }, - { 0x110043, 0x5a1 }, - { 0x110143, 0x5a1 }, - { 0x111043, 0x5a1 }, - { 0x111143, 0x5a1 }, - { 0x112043, 0x5a1 }, - { 0x112143, 0x5a1 }, - { 0x113043, 0x5a1 }, - { 0x113143, 0x5a1 }, - { 0x2200b2, 0x104 }, - { 0x210043, 0x5a1 }, - { 0x210143, 0x5a1 }, - { 0x211043, 0x5a1 }, - { 0x211143, 0x5a1 }, - { 0x212043, 0x5a1 }, - { 0x212143, 0x5a1 }, - { 0x213043, 0x5a1 }, - { 0x213143, 0x5a1 }, - { 0x200fa, 0x1 }, - { 0x1200fa, 0x1 }, - { 0x2200fa, 0x1 }, - { 0x20019, 0x1 }, - { 0x120019, 0x1 }, - { 0x220019, 0x1 }, - { 0x200f0, 0x660 }, - { 0x200f1, 0x0 }, - { 0x200f2, 0x4444 }, - { 0x200f3, 0x8888 }, - { 0x200f4, 0x5665 }, - { 0x200f5, 0x0 }, - { 0x200f6, 0x0 }, - { 0x200f7, 0xf000 }, - { 0x20025, 0x0 }, - { 0x2002d, 0x1 }, - { 0x12002d, 0x1 }, - { 0x22002d, 0x1 }, - { 0x2007d, 0x212 }, - { 0x12007d, 0x212 }, - { 0x22007d, 0x212 }, - { 0x2007c, 0x61 }, - { 0x12007c, 0x61 }, - { 0x22007c, 0x61 }, - { 0x2002c, 0x0 }, -}; - -/* ddr phy trained csr */ -static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - { 0x200b2, 0x0 }, - { 0x1200b2, 0x0 }, - { 0x2200b2, 0x0 }, - { 0x200cb, 0x0 }, - { 0x10043, 0x0 }, - { 0x110043, 0x0 }, - { 0x210043, 0x0 }, - { 0x10143, 0x0 }, - { 0x110143, 0x0 }, - { 0x210143, 0x0 }, - { 0x11043, 0x0 }, - { 0x111043, 0x0 }, - { 0x211043, 0x0 }, - { 0x11143, 0x0 }, - { 0x111143, 0x0 }, - { 0x211143, 0x0 }, - { 0x12043, 0x0 }, - { 0x112043, 0x0 }, - { 0x212043, 0x0 }, - { 0x12143, 0x0 }, - { 0x112143, 0x0 }, - { 0x212143, 0x0 }, - { 0x13043, 0x0 }, - { 0x113043, 0x0 }, - { 0x213043, 0x0 }, - { 0x13143, 0x0 }, - { 0x113143, 0x0 }, - { 0x213143, 0x0 }, - { 0x80, 0x0 }, - { 0x100080, 0x0 }, - { 0x200080, 0x0 }, - { 0x1080, 0x0 }, - { 0x101080, 0x0 }, - { 0x201080, 0x0 }, - { 0x2080, 0x0 }, - { 0x102080, 0x0 }, - { 0x202080, 0x0 }, - { 0x3080, 0x0 }, - { 0x103080, 0x0 }, - { 0x203080, 0x0 }, - { 0x4080, 0x0 }, - { 0x104080, 0x0 }, - { 0x204080, 0x0 }, - { 0x5080, 0x0 }, - { 0x105080, 0x0 }, - { 0x205080, 0x0 }, - { 0x6080, 0x0 }, - { 0x106080, 0x0 }, - { 0x206080, 0x0 }, - { 0x7080, 0x0 }, - { 0x107080, 0x0 }, - { 0x207080, 0x0 }, - { 0x8080, 0x0 }, - { 0x108080, 0x0 }, - { 0x208080, 0x0 }, - { 0x9080, 0x0 }, - { 0x109080, 0x0 }, - { 0x209080, 0x0 }, - { 0x10080, 0x0 }, - { 0x110080, 0x0 }, - { 0x210080, 0x0 }, - { 0x10180, 0x0 }, - { 0x110180, 0x0 }, - { 0x210180, 0x0 }, - { 0x11080, 0x0 }, - { 0x111080, 0x0 }, - { 0x211080, 0x0 }, - { 0x11180, 0x0 }, - { 0x111180, 0x0 }, - { 0x211180, 0x0 }, - { 0x12080, 0x0 }, - { 0x112080, 0x0 }, - { 0x212080, 0x0 }, - { 0x12180, 0x0 }, - { 0x112180, 0x0 }, - { 0x212180, 0x0 }, - { 0x13080, 0x0 }, - { 0x113080, 0x0 }, - { 0x213080, 0x0 }, - { 0x13180, 0x0 }, - { 0x113180, 0x0 }, - { 0x213180, 0x0 }, - { 0x10081, 0x0 }, - { 0x110081, 0x0 }, - { 0x210081, 0x0 }, - { 0x10181, 0x0 }, - { 0x110181, 0x0 }, - { 0x210181, 0x0 }, - { 0x11081, 0x0 }, - { 0x111081, 0x0 }, - { 0x211081, 0x0 }, - { 0x11181, 0x0 }, - { 0x111181, 0x0 }, - { 0x211181, 0x0 }, - { 0x12081, 0x0 }, - { 0x112081, 0x0 }, - { 0x212081, 0x0 }, - { 0x12181, 0x0 }, - { 0x112181, 0x0 }, - { 0x212181, 0x0 }, - { 0x13081, 0x0 }, - { 0x113081, 0x0 }, - { 0x213081, 0x0 }, - { 0x13181, 0x0 }, - { 0x113181, 0x0 }, - { 0x213181, 0x0 }, - { 0x100d0, 0x0 }, - { 0x1100d0, 0x0 }, - { 0x2100d0, 0x0 }, - { 0x101d0, 0x0 }, - { 0x1101d0, 0x0 }, - { 0x2101d0, 0x0 }, - { 0x110d0, 0x0 }, - { 0x1110d0, 0x0 }, - { 0x2110d0, 0x0 }, - { 0x111d0, 0x0 }, - { 0x1111d0, 0x0 }, - { 0x2111d0, 0x0 }, - { 0x120d0, 0x0 }, - { 0x1120d0, 0x0 }, - { 0x2120d0, 0x0 }, - { 0x121d0, 0x0 }, - { 0x1121d0, 0x0 }, - { 0x2121d0, 0x0 }, - { 0x130d0, 0x0 }, - { 0x1130d0, 0x0 }, - { 0x2130d0, 0x0 }, - { 0x131d0, 0x0 }, - { 0x1131d0, 0x0 }, - { 0x2131d0, 0x0 }, - { 0x100d1, 0x0 }, - { 0x1100d1, 0x0 }, - { 0x2100d1, 0x0 }, - { 0x101d1, 0x0 }, - { 0x1101d1, 0x0 }, - { 0x2101d1, 0x0 }, - { 0x110d1, 0x0 }, - { 0x1110d1, 0x0 }, - { 0x2110d1, 0x0 }, - { 0x111d1, 0x0 }, - { 0x1111d1, 0x0 }, - { 0x2111d1, 0x0 }, - { 0x120d1, 0x0 }, - { 0x1120d1, 0x0 }, - { 0x2120d1, 0x0 }, - { 0x121d1, 0x0 }, - { 0x1121d1, 0x0 }, - { 0x2121d1, 0x0 }, - { 0x130d1, 0x0 }, - { 0x1130d1, 0x0 }, - { 0x2130d1, 0x0 }, - { 0x131d1, 0x0 }, - { 0x1131d1, 0x0 }, - { 0x2131d1, 0x0 }, - { 0x10068, 0x0 }, - { 0x10168, 0x0 }, - { 0x10268, 0x0 }, - { 0x10368, 0x0 }, - { 0x10468, 0x0 }, - { 0x10568, 0x0 }, - { 0x10668, 0x0 }, - { 0x10768, 0x0 }, - { 0x10868, 0x0 }, - { 0x11068, 0x0 }, - { 0x11168, 0x0 }, - { 0x11268, 0x0 }, - { 0x11368, 0x0 }, - { 0x11468, 0x0 }, - { 0x11568, 0x0 }, - { 0x11668, 0x0 }, - { 0x11768, 0x0 }, - { 0x11868, 0x0 }, - { 0x12068, 0x0 }, - { 0x12168, 0x0 }, - { 0x12268, 0x0 }, - { 0x12368, 0x0 }, - { 0x12468, 0x0 }, - { 0x12568, 0x0 }, - { 0x12668, 0x0 }, - { 0x12768, 0x0 }, - { 0x12868, 0x0 }, - { 0x13068, 0x0 }, - { 0x13168, 0x0 }, - { 0x13268, 0x0 }, - { 0x13368, 0x0 }, - { 0x13468, 0x0 }, - { 0x13568, 0x0 }, - { 0x13668, 0x0 }, - { 0x13768, 0x0 }, - { 0x13868, 0x0 }, - { 0x10069, 0x0 }, - { 0x10169, 0x0 }, - { 0x10269, 0x0 }, - { 0x10369, 0x0 }, - { 0x10469, 0x0 }, - { 0x10569, 0x0 }, - { 0x10669, 0x0 }, - { 0x10769, 0x0 }, - { 0x10869, 0x0 }, - { 0x11069, 0x0 }, - { 0x11169, 0x0 }, - { 0x11269, 0x0 }, - { 0x11369, 0x0 }, - { 0x11469, 0x0 }, - { 0x11569, 0x0 }, - { 0x11669, 0x0 }, - { 0x11769, 0x0 }, - { 0x11869, 0x0 }, - { 0x12069, 0x0 }, - { 0x12169, 0x0 }, - { 0x12269, 0x0 }, - { 0x12369, 0x0 }, - { 0x12469, 0x0 }, - { 0x12569, 0x0 }, - { 0x12669, 0x0 }, - { 0x12769, 0x0 }, - { 0x12869, 0x0 }, - { 0x13069, 0x0 }, - { 0x13169, 0x0 }, - { 0x13269, 0x0 }, - { 0x13369, 0x0 }, - { 0x13469, 0x0 }, - { 0x13569, 0x0 }, - { 0x13669, 0x0 }, - { 0x13769, 0x0 }, - { 0x13869, 0x0 }, - { 0x1008c, 0x0 }, - { 0x11008c, 0x0 }, - { 0x21008c, 0x0 }, - { 0x1018c, 0x0 }, - { 0x11018c, 0x0 }, - { 0x21018c, 0x0 }, - { 0x1108c, 0x0 }, - { 0x11108c, 0x0 }, - { 0x21108c, 0x0 }, - { 0x1118c, 0x0 }, - { 0x11118c, 0x0 }, - { 0x21118c, 0x0 }, - { 0x1208c, 0x0 }, - { 0x11208c, 0x0 }, - { 0x21208c, 0x0 }, - { 0x1218c, 0x0 }, - { 0x11218c, 0x0 }, - { 0x21218c, 0x0 }, - { 0x1308c, 0x0 }, - { 0x11308c, 0x0 }, - { 0x21308c, 0x0 }, - { 0x1318c, 0x0 }, - { 0x11318c, 0x0 }, - { 0x21318c, 0x0 }, - { 0x1008d, 0x0 }, - { 0x11008d, 0x0 }, - { 0x21008d, 0x0 }, - { 0x1018d, 0x0 }, - { 0x11018d, 0x0 }, - { 0x21018d, 0x0 }, - { 0x1108d, 0x0 }, - { 0x11108d, 0x0 }, - { 0x21108d, 0x0 }, - { 0x1118d, 0x0 }, - { 0x11118d, 0x0 }, - { 0x21118d, 0x0 }, - { 0x1208d, 0x0 }, - { 0x11208d, 0x0 }, - { 0x21208d, 0x0 }, - { 0x1218d, 0x0 }, - { 0x11218d, 0x0 }, - { 0x21218d, 0x0 }, - { 0x1308d, 0x0 }, - { 0x11308d, 0x0 }, - { 0x21308d, 0x0 }, - { 0x1318d, 0x0 }, - { 0x11318d, 0x0 }, - { 0x21318d, 0x0 }, - { 0x100c0, 0x0 }, - { 0x1100c0, 0x0 }, - { 0x2100c0, 0x0 }, - { 0x101c0, 0x0 }, - { 0x1101c0, 0x0 }, - { 0x2101c0, 0x0 }, - { 0x102c0, 0x0 }, - { 0x1102c0, 0x0 }, - { 0x2102c0, 0x0 }, - { 0x103c0, 0x0 }, - { 0x1103c0, 0x0 }, - { 0x2103c0, 0x0 }, - { 0x104c0, 0x0 }, - { 0x1104c0, 0x0 }, - { 0x2104c0, 0x0 }, - { 0x105c0, 0x0 }, - { 0x1105c0, 0x0 }, - { 0x2105c0, 0x0 }, - { 0x106c0, 0x0 }, - { 0x1106c0, 0x0 }, - { 0x2106c0, 0x0 }, - { 0x107c0, 0x0 }, - { 0x1107c0, 0x0 }, - { 0x2107c0, 0x0 }, - { 0x108c0, 0x0 }, - { 0x1108c0, 0x0 }, - { 0x2108c0, 0x0 }, - { 0x110c0, 0x0 }, - { 0x1110c0, 0x0 }, - { 0x2110c0, 0x0 }, - { 0x111c0, 0x0 }, - { 0x1111c0, 0x0 }, - { 0x2111c0, 0x0 }, - { 0x112c0, 0x0 }, - { 0x1112c0, 0x0 }, - { 0x2112c0, 0x0 }, - { 0x113c0, 0x0 }, - { 0x1113c0, 0x0 }, - { 0x2113c0, 0x0 }, - { 0x114c0, 0x0 }, - { 0x1114c0, 0x0 }, - { 0x2114c0, 0x0 }, - { 0x115c0, 0x0 }, - { 0x1115c0, 0x0 }, - { 0x2115c0, 0x0 }, - { 0x116c0, 0x0 }, - { 0x1116c0, 0x0 }, - { 0x2116c0, 0x0 }, - { 0x117c0, 0x0 }, - { 0x1117c0, 0x0 }, - { 0x2117c0, 0x0 }, - { 0x118c0, 0x0 }, - { 0x1118c0, 0x0 }, - { 0x2118c0, 0x0 }, - { 0x120c0, 0x0 }, - { 0x1120c0, 0x0 }, - { 0x2120c0, 0x0 }, - { 0x121c0, 0x0 }, - { 0x1121c0, 0x0 }, - { 0x2121c0, 0x0 }, - { 0x122c0, 0x0 }, - { 0x1122c0, 0x0 }, - { 0x2122c0, 0x0 }, - { 0x123c0, 0x0 }, - { 0x1123c0, 0x0 }, - { 0x2123c0, 0x0 }, - { 0x124c0, 0x0 }, - { 0x1124c0, 0x0 }, - { 0x2124c0, 0x0 }, - { 0x125c0, 0x0 }, - { 0x1125c0, 0x0 }, - { 0x2125c0, 0x0 }, - { 0x126c0, 0x0 }, - { 0x1126c0, 0x0 }, - { 0x2126c0, 0x0 }, - { 0x127c0, 0x0 }, - { 0x1127c0, 0x0 }, - { 0x2127c0, 0x0 }, - { 0x128c0, 0x0 }, - { 0x1128c0, 0x0 }, - { 0x2128c0, 0x0 }, - { 0x130c0, 0x0 }, - { 0x1130c0, 0x0 }, - { 0x2130c0, 0x0 }, - { 0x131c0, 0x0 }, - { 0x1131c0, 0x0 }, - { 0x2131c0, 0x0 }, - { 0x132c0, 0x0 }, - { 0x1132c0, 0x0 }, - { 0x2132c0, 0x0 }, - { 0x133c0, 0x0 }, - { 0x1133c0, 0x0 }, - { 0x2133c0, 0x0 }, - { 0x134c0, 0x0 }, - { 0x1134c0, 0x0 }, - { 0x2134c0, 0x0 }, - { 0x135c0, 0x0 }, - { 0x1135c0, 0x0 }, - { 0x2135c0, 0x0 }, - { 0x136c0, 0x0 }, - { 0x1136c0, 0x0 }, - { 0x2136c0, 0x0 }, - { 0x137c0, 0x0 }, - { 0x1137c0, 0x0 }, - { 0x2137c0, 0x0 }, - { 0x138c0, 0x0 }, - { 0x1138c0, 0x0 }, - { 0x2138c0, 0x0 }, - { 0x100c1, 0x0 }, - { 0x1100c1, 0x0 }, - { 0x2100c1, 0x0 }, - { 0x101c1, 0x0 }, - { 0x1101c1, 0x0 }, - { 0x2101c1, 0x0 }, - { 0x102c1, 0x0 }, - { 0x1102c1, 0x0 }, - { 0x2102c1, 0x0 }, - { 0x103c1, 0x0 }, - { 0x1103c1, 0x0 }, - { 0x2103c1, 0x0 }, - { 0x104c1, 0x0 }, - { 0x1104c1, 0x0 }, - { 0x2104c1, 0x0 }, - { 0x105c1, 0x0 }, - { 0x1105c1, 0x0 }, - { 0x2105c1, 0x0 }, - { 0x106c1, 0x0 }, - { 0x1106c1, 0x0 }, - { 0x2106c1, 0x0 }, - { 0x107c1, 0x0 }, - { 0x1107c1, 0x0 }, - { 0x2107c1, 0x0 }, - { 0x108c1, 0x0 }, - { 0x1108c1, 0x0 }, - { 0x2108c1, 0x0 }, - { 0x110c1, 0x0 }, - { 0x1110c1, 0x0 }, - { 0x2110c1, 0x0 }, - { 0x111c1, 0x0 }, - { 0x1111c1, 0x0 }, - { 0x2111c1, 0x0 }, - { 0x112c1, 0x0 }, - { 0x1112c1, 0x0 }, - { 0x2112c1, 0x0 }, - { 0x113c1, 0x0 }, - { 0x1113c1, 0x0 }, - { 0x2113c1, 0x0 }, - { 0x114c1, 0x0 }, - { 0x1114c1, 0x0 }, - { 0x2114c1, 0x0 }, - { 0x115c1, 0x0 }, - { 0x1115c1, 0x0 }, - { 0x2115c1, 0x0 }, - { 0x116c1, 0x0 }, - { 0x1116c1, 0x0 }, - { 0x2116c1, 0x0 }, - { 0x117c1, 0x0 }, - { 0x1117c1, 0x0 }, - { 0x2117c1, 0x0 }, - { 0x118c1, 0x0 }, - { 0x1118c1, 0x0 }, - { 0x2118c1, 0x0 }, - { 0x120c1, 0x0 }, - { 0x1120c1, 0x0 }, - { 0x2120c1, 0x0 }, - { 0x121c1, 0x0 }, - { 0x1121c1, 0x0 }, - { 0x2121c1, 0x0 }, - { 0x122c1, 0x0 }, - { 0x1122c1, 0x0 }, - { 0x2122c1, 0x0 }, - { 0x123c1, 0x0 }, - { 0x1123c1, 0x0 }, - { 0x2123c1, 0x0 }, - { 0x124c1, 0x0 }, - { 0x1124c1, 0x0 }, - { 0x2124c1, 0x0 }, - { 0x125c1, 0x0 }, - { 0x1125c1, 0x0 }, - { 0x2125c1, 0x0 }, - { 0x126c1, 0x0 }, - { 0x1126c1, 0x0 }, - { 0x2126c1, 0x0 }, - { 0x127c1, 0x0 }, - { 0x1127c1, 0x0 }, - { 0x2127c1, 0x0 }, - { 0x128c1, 0x0 }, - { 0x1128c1, 0x0 }, - { 0x2128c1, 0x0 }, - { 0x130c1, 0x0 }, - { 0x1130c1, 0x0 }, - { 0x2130c1, 0x0 }, - { 0x131c1, 0x0 }, - { 0x1131c1, 0x0 }, - { 0x2131c1, 0x0 }, - { 0x132c1, 0x0 }, - { 0x1132c1, 0x0 }, - { 0x2132c1, 0x0 }, - { 0x133c1, 0x0 }, - { 0x1133c1, 0x0 }, - { 0x2133c1, 0x0 }, - { 0x134c1, 0x0 }, - { 0x1134c1, 0x0 }, - { 0x2134c1, 0x0 }, - { 0x135c1, 0x0 }, - { 0x1135c1, 0x0 }, - { 0x2135c1, 0x0 }, - { 0x136c1, 0x0 }, - { 0x1136c1, 0x0 }, - { 0x2136c1, 0x0 }, - { 0x137c1, 0x0 }, - { 0x1137c1, 0x0 }, - { 0x2137c1, 0x0 }, - { 0x138c1, 0x0 }, - { 0x1138c1, 0x0 }, - { 0x2138c1, 0x0 }, - { 0x10020, 0x0 }, - { 0x110020, 0x0 }, - { 0x210020, 0x0 }, - { 0x11020, 0x0 }, - { 0x111020, 0x0 }, - { 0x211020, 0x0 }, - { 0x12020, 0x0 }, - { 0x112020, 0x0 }, - { 0x212020, 0x0 }, - { 0x13020, 0x0 }, - { 0x113020, 0x0 }, - { 0x213020, 0x0 }, - { 0x20072, 0x0 }, - { 0x20073, 0x0 }, - { 0x20074, 0x0 }, - { 0x100aa, 0x0 }, - { 0x110aa, 0x0 }, - { 0x120aa, 0x0 }, - { 0x130aa, 0x0 }, - { 0x20010, 0x0 }, - { 0x120010, 0x0 }, - { 0x220010, 0x0 }, - { 0x20011, 0x0 }, - { 0x120011, 0x0 }, - { 0x220011, 0x0 }, - { 0x100ae, 0x0 }, - { 0x1100ae, 0x0 }, - { 0x2100ae, 0x0 }, - { 0x100af, 0x0 }, - { 0x1100af, 0x0 }, - { 0x2100af, 0x0 }, - { 0x110ae, 0x0 }, - { 0x1110ae, 0x0 }, - { 0x2110ae, 0x0 }, - { 0x110af, 0x0 }, - { 0x1110af, 0x0 }, - { 0x2110af, 0x0 }, - { 0x120ae, 0x0 }, - { 0x1120ae, 0x0 }, - { 0x2120ae, 0x0 }, - { 0x120af, 0x0 }, - { 0x1120af, 0x0 }, - { 0x2120af, 0x0 }, - { 0x130ae, 0x0 }, - { 0x1130ae, 0x0 }, - { 0x2130ae, 0x0 }, - { 0x130af, 0x0 }, - { 0x1130af, 0x0 }, - { 0x2130af, 0x0 }, - { 0x20020, 0x0 }, - { 0x120020, 0x0 }, - { 0x220020, 0x0 }, - { 0x100a0, 0x0 }, - { 0x100a1, 0x0 }, - { 0x100a2, 0x0 }, - { 0x100a3, 0x0 }, - { 0x100a4, 0x0 }, - { 0x100a5, 0x0 }, - { 0x100a6, 0x0 }, - { 0x100a7, 0x0 }, - { 0x110a0, 0x0 }, - { 0x110a1, 0x0 }, - { 0x110a2, 0x0 }, - { 0x110a3, 0x0 }, - { 0x110a4, 0x0 }, - { 0x110a5, 0x0 }, - { 0x110a6, 0x0 }, - { 0x110a7, 0x0 }, - { 0x120a0, 0x0 }, - { 0x120a1, 0x0 }, - { 0x120a2, 0x0 }, - { 0x120a3, 0x0 }, - { 0x120a4, 0x0 }, - { 0x120a5, 0x0 }, - { 0x120a6, 0x0 }, - { 0x120a7, 0x0 }, - { 0x130a0, 0x0 }, - { 0x130a1, 0x0 }, - { 0x130a2, 0x0 }, - { 0x130a3, 0x0 }, - { 0x130a4, 0x0 }, - { 0x130a5, 0x0 }, - { 0x130a6, 0x0 }, - { 0x130a7, 0x0 }, - { 0x2007c, 0x0 }, - { 0x12007c, 0x0 }, - { 0x22007c, 0x0 }, - { 0x2007d, 0x0 }, - { 0x12007d, 0x0 }, - { 0x22007d, 0x0 }, - { 0x400fd, 0x0 }, - { 0x400c0, 0x0 }, - { 0x90201, 0x0 }, - { 0x190201, 0x0 }, - { 0x290201, 0x0 }, - { 0x90202, 0x0 }, - { 0x190202, 0x0 }, - { 0x290202, 0x0 }, - { 0x90203, 0x0 }, - { 0x190203, 0x0 }, - { 0x290203, 0x0 }, - { 0x90204, 0x0 }, - { 0x190204, 0x0 }, - { 0x290204, 0x0 }, - { 0x90205, 0x0 }, - { 0x190205, 0x0 }, - { 0x290205, 0x0 }, - { 0x90206, 0x0 }, - { 0x190206, 0x0 }, - { 0x290206, 0x0 }, - { 0x90207, 0x0 }, - { 0x190207, 0x0 }, - { 0x290207, 0x0 }, - { 0x90208, 0x0 }, - { 0x190208, 0x0 }, - { 0x290208, 0x0 }, - { 0x10062, 0x0 }, - { 0x10162, 0x0 }, - { 0x10262, 0x0 }, - { 0x10362, 0x0 }, - { 0x10462, 0x0 }, - { 0x10562, 0x0 }, - { 0x10662, 0x0 }, - { 0x10762, 0x0 }, - { 0x10862, 0x0 }, - { 0x11062, 0x0 }, - { 0x11162, 0x0 }, - { 0x11262, 0x0 }, - { 0x11362, 0x0 }, - { 0x11462, 0x0 }, - { 0x11562, 0x0 }, - { 0x11662, 0x0 }, - { 0x11762, 0x0 }, - { 0x11862, 0x0 }, - { 0x12062, 0x0 }, - { 0x12162, 0x0 }, - { 0x12262, 0x0 }, - { 0x12362, 0x0 }, - { 0x12462, 0x0 }, - { 0x12562, 0x0 }, - { 0x12662, 0x0 }, - { 0x12762, 0x0 }, - { 0x12862, 0x0 }, - { 0x13062, 0x0 }, - { 0x13162, 0x0 }, - { 0x13262, 0x0 }, - { 0x13362, 0x0 }, - { 0x13462, 0x0 }, - { 0x13562, 0x0 }, - { 0x13662, 0x0 }, - { 0x13762, 0x0 }, - { 0x13862, 0x0 }, - { 0x20077, 0x0 }, - { 0x10001, 0x0 }, - { 0x11001, 0x0 }, - { 0x12001, 0x0 }, - { 0x13001, 0x0 }, - { 0x10040, 0x0 }, - { 0x10140, 0x0 }, - { 0x10240, 0x0 }, - { 0x10340, 0x0 }, - { 0x10440, 0x0 }, - { 0x10540, 0x0 }, - { 0x10640, 0x0 }, - { 0x10740, 0x0 }, - { 0x10840, 0x0 }, - { 0x10030, 0x0 }, - { 0x10130, 0x0 }, - { 0x10230, 0x0 }, - { 0x10330, 0x0 }, - { 0x10430, 0x0 }, - { 0x10530, 0x0 }, - { 0x10630, 0x0 }, - { 0x10730, 0x0 }, - { 0x10830, 0x0 }, - { 0x11040, 0x0 }, - { 0x11140, 0x0 }, - { 0x11240, 0x0 }, - { 0x11340, 0x0 }, - { 0x11440, 0x0 }, - { 0x11540, 0x0 }, - { 0x11640, 0x0 }, - { 0x11740, 0x0 }, - { 0x11840, 0x0 }, - { 0x11030, 0x0 }, - { 0x11130, 0x0 }, - { 0x11230, 0x0 }, - { 0x11330, 0x0 }, - { 0x11430, 0x0 }, - { 0x11530, 0x0 }, - { 0x11630, 0x0 }, - { 0x11730, 0x0 }, - { 0x11830, 0x0 }, - { 0x12040, 0x0 }, - { 0x12140, 0x0 }, - { 0x12240, 0x0 }, - { 0x12340, 0x0 }, - { 0x12440, 0x0 }, - { 0x12540, 0x0 }, - { 0x12640, 0x0 }, - { 0x12740, 0x0 }, - { 0x12840, 0x0 }, - { 0x12030, 0x0 }, - { 0x12130, 0x0 }, - { 0x12230, 0x0 }, - { 0x12330, 0x0 }, - { 0x12430, 0x0 }, - { 0x12530, 0x0 }, - { 0x12630, 0x0 }, - { 0x12730, 0x0 }, - { 0x12830, 0x0 }, - { 0x13040, 0x0 }, - { 0x13140, 0x0 }, - { 0x13240, 0x0 }, - { 0x13340, 0x0 }, - { 0x13440, 0x0 }, - { 0x13540, 0x0 }, - { 0x13640, 0x0 }, - { 0x13740, 0x0 }, - { 0x13840, 0x0 }, - { 0x13030, 0x0 }, - { 0x13130, 0x0 }, - { 0x13230, 0x0 }, - { 0x13330, 0x0 }, - { 0x13430, 0x0 }, - { 0x13530, 0x0 }, - { 0x13630, 0x0 }, - { 0x13730, 0x0 }, - { 0x13830, 0x0 }, -}; - -/* P0 message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp0_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54003, 0xe10 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x131f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54012, 0x310 }, - { 0x54019, 0x36e4 }, - { 0x5401a, 0xf3 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x36e4 }, - { 0x54020, 0xf3 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x54032, 0xe400 }, - { 0x54033, 0xf336 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0xe400 }, - { 0x54039, 0xf336 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P1 message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp1_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x101 }, - { 0x54003, 0x190 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x121f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54012, 0x310 }, - { 0x54019, 0x84 }, - { 0x5401a, 0xf3 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x84 }, - { 0x54020, 0xf3 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x54032, 0x8400 }, - { 0x54033, 0xf300 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0x8400 }, - { 0x54039, 0xf300 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P2 message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp2_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x102 }, - { 0x54003, 0x64 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x121f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54012, 0x310 }, - { 0x54019, 0x84 }, - { 0x5401a, 0xf3 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x84 }, - { 0x54020, 0xf3 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x54032, 0x8400 }, - { 0x54033, 0xf300 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0x8400 }, - { 0x54039, 0xf300 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* P0 2D message block paremeter for training firmware */ -static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54003, 0xe10 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x14 }, - { 0x54008, 0x61 }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400f, 0x100 }, - { 0x54010, 0x1f7f }, - { 0x54012, 0x310 }, - { 0x54019, 0x36e4 }, - { 0x5401a, 0xf3 }, - { 0x5401b, 0x4866 }, - { 0x5401c, 0x4800 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x36e4 }, - { 0x54020, 0xf3 }, - { 0x54021, 0x4866 }, - { 0x54022, 0x4800 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x54032, 0xe400 }, - { 0x54033, 0xf336 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x48 }, - { 0x54036, 0x48 }, - { 0x54037, 0x1600 }, - { 0x54038, 0xe400 }, - { 0x54039, 0xf336 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x48 }, - { 0x5403c, 0x48 }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - -/* DRAM PHY init engine image */ -static struct dram_cfg_param ddr_phy_pie[] = { - { 0xd0000, 0x0 }, - { 0x90000, 0x10 }, - { 0x90001, 0x400 }, - { 0x90002, 0x10e }, - { 0x90003, 0x0 }, - { 0x90004, 0x0 }, - { 0x90005, 0x8 }, - { 0x90029, 0xb }, - { 0x9002a, 0x480 }, - { 0x9002b, 0x109 }, - { 0x9002c, 0x8 }, - { 0x9002d, 0x448 }, - { 0x9002e, 0x139 }, - { 0x9002f, 0x8 }, - { 0x90030, 0x478 }, - { 0x90031, 0x109 }, - { 0x90032, 0x0 }, - { 0x90033, 0xe8 }, - { 0x90034, 0x109 }, - { 0x90035, 0x2 }, - { 0x90036, 0x10 }, - { 0x90037, 0x139 }, - { 0x90038, 0xb }, - { 0x90039, 0x7c0 }, - { 0x9003a, 0x139 }, - { 0x9003b, 0x44 }, - { 0x9003c, 0x633 }, - { 0x9003d, 0x159 }, - { 0x9003e, 0x14f }, - { 0x9003f, 0x630 }, - { 0x90040, 0x159 }, - { 0x90041, 0x47 }, - { 0x90042, 0x633 }, - { 0x90043, 0x149 }, - { 0x90044, 0x4f }, - { 0x90045, 0x633 }, - { 0x90046, 0x179 }, - { 0x90047, 0x8 }, - { 0x90048, 0xe0 }, - { 0x90049, 0x109 }, - { 0x9004a, 0x0 }, - { 0x9004b, 0x7c8 }, - { 0x9004c, 0x109 }, - { 0x9004d, 0x0 }, - { 0x9004e, 0x1 }, - { 0x9004f, 0x8 }, - { 0x90050, 0x0 }, - { 0x90051, 0x45a }, - { 0x90052, 0x9 }, - { 0x90053, 0x0 }, - { 0x90054, 0x448 }, - { 0x90055, 0x109 }, - { 0x90056, 0x40 }, - { 0x90057, 0x633 }, - { 0x90058, 0x179 }, - { 0x90059, 0x1 }, - { 0x9005a, 0x618 }, - { 0x9005b, 0x109 }, - { 0x9005c, 0x40c0 }, - { 0x9005d, 0x633 }, - { 0x9005e, 0x149 }, - { 0x9005f, 0x8 }, - { 0x90060, 0x4 }, - { 0x90061, 0x48 }, - { 0x90062, 0x4040 }, - { 0x90063, 0x633 }, - { 0x90064, 0x149 }, - { 0x90065, 0x0 }, - { 0x90066, 0x4 }, - { 0x90067, 0x48 }, - { 0x90068, 0x40 }, - { 0x90069, 0x633 }, - { 0x9006a, 0x149 }, - { 0x9006b, 0x10 }, - { 0x9006c, 0x4 }, - { 0x9006d, 0x18 }, - { 0x9006e, 0x0 }, - { 0x9006f, 0x4 }, - { 0x90070, 0x78 }, - { 0x90071, 0x549 }, - { 0x90072, 0x633 }, - { 0x90073, 0x159 }, - { 0x90074, 0xd49 }, - { 0x90075, 0x633 }, - { 0x90076, 0x159 }, - { 0x90077, 0x94a }, - { 0x90078, 0x633 }, - { 0x90079, 0x159 }, - { 0x9007a, 0x441 }, - { 0x9007b, 0x633 }, - { 0x9007c, 0x149 }, - { 0x9007d, 0x42 }, - { 0x9007e, 0x633 }, - { 0x9007f, 0x149 }, - { 0x90080, 0x1 }, - { 0x90081, 0x633 }, - { 0x90082, 0x149 }, - { 0x90083, 0x0 }, - { 0x90084, 0xe0 }, - { 0x90085, 0x109 }, - { 0x90086, 0xa }, - { 0x90087, 0x10 }, - { 0x90088, 0x109 }, - { 0x90089, 0x9 }, - { 0x9008a, 0x3c0 }, - { 0x9008b, 0x149 }, - { 0x9008c, 0x9 }, - { 0x9008d, 0x3c0 }, - { 0x9008e, 0x159 }, - { 0x9008f, 0x18 }, - { 0x90090, 0x10 }, - { 0x90091, 0x109 }, - { 0x90092, 0x0 }, - { 0x90093, 0x3c0 }, - { 0x90094, 0x109 }, - { 0x90095, 0x18 }, - { 0x90096, 0x4 }, - { 0x90097, 0x48 }, - { 0x90098, 0x18 }, - { 0x90099, 0x4 }, - { 0x9009a, 0x58 }, - { 0x9009b, 0xb }, - { 0x9009c, 0x10 }, - { 0x9009d, 0x109 }, - { 0x9009e, 0x1 }, - { 0x9009f, 0x10 }, - { 0x900a0, 0x109 }, - { 0x900a1, 0x5 }, - { 0x900a2, 0x7c0 }, - { 0x900a3, 0x109 }, - { 0x40000, 0x811 }, - { 0x40020, 0x880 }, - { 0x40040, 0x0 }, - { 0x40060, 0x0 }, - { 0x40001, 0x4008 }, - { 0x40021, 0x83 }, - { 0x40041, 0x4f }, - { 0x40061, 0x0 }, - { 0x40002, 0x4040 }, - { 0x40022, 0x83 }, - { 0x40042, 0x51 }, - { 0x40062, 0x0 }, - { 0x40003, 0x811 }, - { 0x40023, 0x880 }, - { 0x40043, 0x0 }, - { 0x40063, 0x0 }, - { 0x40004, 0x720 }, - { 0x40024, 0xf }, - { 0x40044, 0x1740 }, - { 0x40064, 0x0 }, - { 0x40005, 0x16 }, - { 0x40025, 0x83 }, - { 0x40045, 0x4b }, - { 0x40065, 0x0 }, - { 0x40006, 0x716 }, - { 0x40026, 0xf }, - { 0x40046, 0x2001 }, - { 0x40066, 0x0 }, - { 0x40007, 0x716 }, - { 0x40027, 0xf }, - { 0x40047, 0x2800 }, - { 0x40067, 0x0 }, - { 0x40008, 0x716 }, - { 0x40028, 0xf }, - { 0x40048, 0xf00 }, - { 0x40068, 0x0 }, - { 0x40009, 0x720 }, - { 0x40029, 0xf }, - { 0x40049, 0x1400 }, - { 0x40069, 0x0 }, - { 0x4000a, 0xe08 }, - { 0x4002a, 0xc15 }, - { 0x4004a, 0x0 }, - { 0x4006a, 0x0 }, - { 0x4000b, 0x625 }, - { 0x4002b, 0x15 }, - { 0x4004b, 0x0 }, - { 0x4006b, 0x0 }, - { 0x4000c, 0x4028 }, - { 0x4002c, 0x80 }, - { 0x4004c, 0x0 }, - { 0x4006c, 0x0 }, - { 0x4000d, 0xe08 }, - { 0x4002d, 0xc1a }, - { 0x4004d, 0x0 }, - { 0x4006d, 0x0 }, - { 0x4000e, 0x625 }, - { 0x4002e, 0x1a }, - { 0x4004e, 0x0 }, - { 0x4006e, 0x0 }, - { 0x4000f, 0x4040 }, - { 0x4002f, 0x80 }, - { 0x4004f, 0x0 }, - { 0x4006f, 0x0 }, - { 0x40010, 0x2604 }, - { 0x40030, 0x15 }, - { 0x40050, 0x0 }, - { 0x40070, 0x0 }, - { 0x40011, 0x708 }, - { 0x40031, 0x5 }, - { 0x40051, 0x0 }, - { 0x40071, 0x2002 }, - { 0x40012, 0x8 }, - { 0x40032, 0x80 }, - { 0x40052, 0x0 }, - { 0x40072, 0x0 }, - { 0x40013, 0x2604 }, - { 0x40033, 0x1a }, - { 0x40053, 0x0 }, - { 0x40073, 0x0 }, - { 0x40014, 0x708 }, - { 0x40034, 0xa }, - { 0x40054, 0x0 }, - { 0x40074, 0x2002 }, - { 0x40015, 0x4040 }, - { 0x40035, 0x80 }, - { 0x40055, 0x0 }, - { 0x40075, 0x0 }, - { 0x40016, 0x60a }, - { 0x40036, 0x15 }, - { 0x40056, 0x1200 }, - { 0x40076, 0x0 }, - { 0x40017, 0x61a }, - { 0x40037, 0x15 }, - { 0x40057, 0x1300 }, - { 0x40077, 0x0 }, - { 0x40018, 0x60a }, - { 0x40038, 0x1a }, - { 0x40058, 0x1200 }, - { 0x40078, 0x0 }, - { 0x40019, 0x642 }, - { 0x40039, 0x1a }, - { 0x40059, 0x1300 }, - { 0x40079, 0x0 }, - { 0x4001a, 0x4808 }, - { 0x4003a, 0x880 }, - { 0x4005a, 0x0 }, - { 0x4007a, 0x0 }, - { 0x900a4, 0x0 }, - { 0x900a5, 0x790 }, - { 0x900a6, 0x11a }, - { 0x900a7, 0x8 }, - { 0x900a8, 0x7aa }, - { 0x900a9, 0x2a }, - { 0x900aa, 0x10 }, - { 0x900ab, 0x7b2 }, - { 0x900ac, 0x2a }, - { 0x900ad, 0x0 }, - { 0x900ae, 0x7c8 }, - { 0x900af, 0x109 }, - { 0x900b0, 0x10 }, - { 0x900b1, 0x10 }, - { 0x900b2, 0x109 }, - { 0x900b3, 0x10 }, - { 0x900b4, 0x2a8 }, - { 0x900b5, 0x129 }, - { 0x900b6, 0x8 }, - { 0x900b7, 0x370 }, - { 0x900b8, 0x129 }, - { 0x900b9, 0xa }, - { 0x900ba, 0x3c8 }, - { 0x900bb, 0x1a9 }, - { 0x900bc, 0xc }, - { 0x900bd, 0x408 }, - { 0x900be, 0x199 }, - { 0x900bf, 0x14 }, - { 0x900c0, 0x790 }, - { 0x900c1, 0x11a }, - { 0x900c2, 0x8 }, - { 0x900c3, 0x4 }, - { 0x900c4, 0x18 }, - { 0x900c5, 0xe }, - { 0x900c6, 0x408 }, - { 0x900c7, 0x199 }, - { 0x900c8, 0x8 }, - { 0x900c9, 0x8568 }, - { 0x900ca, 0x108 }, - { 0x900cb, 0x18 }, - { 0x900cc, 0x790 }, - { 0x900cd, 0x16a }, - { 0x900ce, 0x8 }, - { 0x900cf, 0x1d8 }, - { 0x900d0, 0x169 }, - { 0x900d1, 0x10 }, - { 0x900d2, 0x8558 }, - { 0x900d3, 0x168 }, - { 0x900d4, 0x70 }, - { 0x900d5, 0x788 }, - { 0x900d6, 0x16a }, - { 0x900d7, 0x1ff8 }, - { 0x900d8, 0x85a8 }, - { 0x900d9, 0x1e8 }, - { 0x900da, 0x50 }, - { 0x900db, 0x798 }, - { 0x900dc, 0x16a }, - { 0x900dd, 0x60 }, - { 0x900de, 0x7a0 }, - { 0x900df, 0x16a }, - { 0x900e0, 0x8 }, - { 0x900e1, 0x8310 }, - { 0x900e2, 0x168 }, - { 0x900e3, 0x8 }, - { 0x900e4, 0xa310 }, - { 0x900e5, 0x168 }, - { 0x900e6, 0xa }, - { 0x900e7, 0x408 }, - { 0x900e8, 0x169 }, - { 0x900e9, 0x6e }, - { 0x900ea, 0x0 }, - { 0x900eb, 0x68 }, - { 0x900ec, 0x0 }, - { 0x900ed, 0x408 }, - { 0x900ee, 0x169 }, - { 0x900ef, 0x0 }, - { 0x900f0, 0x8310 }, - { 0x900f1, 0x168 }, - { 0x900f2, 0x0 }, - { 0x900f3, 0xa310 }, - { 0x900f4, 0x168 }, - { 0x900f5, 0x1ff8 }, - { 0x900f6, 0x85a8 }, - { 0x900f7, 0x1e8 }, - { 0x900f8, 0x68 }, - { 0x900f9, 0x798 }, - { 0x900fa, 0x16a }, - { 0x900fb, 0x78 }, - { 0x900fc, 0x7a0 }, - { 0x900fd, 0x16a }, - { 0x900fe, 0x68 }, - { 0x900ff, 0x790 }, - { 0x90100, 0x16a }, - { 0x90101, 0x8 }, - { 0x90102, 0x8b10 }, - { 0x90103, 0x168 }, - { 0x90104, 0x8 }, - { 0x90105, 0xab10 }, - { 0x90106, 0x168 }, - { 0x90107, 0xa }, - { 0x90108, 0x408 }, - { 0x90109, 0x169 }, - { 0x9010a, 0x58 }, - { 0x9010b, 0x0 }, - { 0x9010c, 0x68 }, - { 0x9010d, 0x0 }, - { 0x9010e, 0x408 }, - { 0x9010f, 0x169 }, - { 0x90110, 0x0 }, - { 0x90111, 0x8b10 }, - { 0x90112, 0x168 }, - { 0x90113, 0x1 }, - { 0x90114, 0xab10 }, - { 0x90115, 0x168 }, - { 0x90116, 0x0 }, - { 0x90117, 0x1d8 }, - { 0x90118, 0x169 }, - { 0x90119, 0x80 }, - { 0x9011a, 0x790 }, - { 0x9011b, 0x16a }, - { 0x9011c, 0x18 }, - { 0x9011d, 0x7aa }, - { 0x9011e, 0x6a }, - { 0x9011f, 0xa }, - { 0x90120, 0x0 }, - { 0x90121, 0x1e9 }, - { 0x90122, 0x8 }, - { 0x90123, 0x8080 }, - { 0x90124, 0x108 }, - { 0x90125, 0xf }, - { 0x90126, 0x408 }, - { 0x90127, 0x169 }, - { 0x90128, 0xc }, - { 0x90129, 0x0 }, - { 0x9012a, 0x68 }, - { 0x9012b, 0x9 }, - { 0x9012c, 0x0 }, - { 0x9012d, 0x1a9 }, - { 0x9012e, 0x0 }, - { 0x9012f, 0x408 }, - { 0x90130, 0x169 }, - { 0x90131, 0x0 }, - { 0x90132, 0x8080 }, - { 0x90133, 0x108 }, - { 0x90134, 0x8 }, - { 0x90135, 0x7aa }, - { 0x90136, 0x6a }, - { 0x90137, 0x0 }, - { 0x90138, 0x8568 }, - { 0x90139, 0x108 }, - { 0x9013a, 0xb7 }, - { 0x9013b, 0x790 }, - { 0x9013c, 0x16a }, - { 0x9013d, 0x1f }, - { 0x9013e, 0x0 }, - { 0x9013f, 0x68 }, - { 0x90140, 0x8 }, - { 0x90141, 0x8558 }, - { 0x90142, 0x168 }, - { 0x90143, 0xf }, - { 0x90144, 0x408 }, - { 0x90145, 0x169 }, - { 0x90146, 0xd }, - { 0x90147, 0x0 }, - { 0x90148, 0x68 }, - { 0x90149, 0x0 }, - { 0x9014a, 0x408 }, - { 0x9014b, 0x169 }, - { 0x9014c, 0x0 }, - { 0x9014d, 0x8558 }, - { 0x9014e, 0x168 }, - { 0x9014f, 0x8 }, - { 0x90150, 0x3c8 }, - { 0x90151, 0x1a9 }, - { 0x90152, 0x3 }, - { 0x90153, 0x370 }, - { 0x90154, 0x129 }, - { 0x90155, 0x20 }, - { 0x90156, 0x2aa }, - { 0x90157, 0x9 }, - { 0x90158, 0x8 }, - { 0x90159, 0xe8 }, - { 0x9015a, 0x109 }, - { 0x9015b, 0x0 }, - { 0x9015c, 0x8140 }, - { 0x9015d, 0x10c }, - { 0x9015e, 0x10 }, - { 0x9015f, 0x8138 }, - { 0x90160, 0x104 }, - { 0x90161, 0x8 }, - { 0x90162, 0x448 }, - { 0x90163, 0x109 }, - { 0x90164, 0xf }, - { 0x90165, 0x7c0 }, - { 0x90166, 0x109 }, - { 0x90167, 0x0 }, - { 0x90168, 0xe8 }, - { 0x90169, 0x109 }, - { 0x9016a, 0x47 }, - { 0x9016b, 0x630 }, - { 0x9016c, 0x109 }, - { 0x9016d, 0x8 }, - { 0x9016e, 0x618 }, - { 0x9016f, 0x109 }, - { 0x90170, 0x8 }, - { 0x90171, 0xe0 }, - { 0x90172, 0x109 }, - { 0x90173, 0x0 }, - { 0x90174, 0x7c8 }, - { 0x90175, 0x109 }, - { 0x90176, 0x8 }, - { 0x90177, 0x8140 }, - { 0x90178, 0x10c }, - { 0x90179, 0x0 }, - { 0x9017a, 0x478 }, - { 0x9017b, 0x109 }, - { 0x9017c, 0x0 }, - { 0x9017d, 0x1 }, - { 0x9017e, 0x8 }, - { 0x9017f, 0x8 }, - { 0x90180, 0x4 }, - { 0x90181, 0x0 }, - { 0x90006, 0x8 }, - { 0x90007, 0x7c8 }, - { 0x90008, 0x109 }, - { 0x90009, 0x0 }, - { 0x9000a, 0x400 }, - { 0x9000b, 0x106 }, - { 0xd00e7, 0x400 }, - { 0x90017, 0x0 }, - { 0x9001f, 0x29 }, - { 0x90026, 0x68 }, - { 0x400d0, 0x0 }, - { 0x400d1, 0x101 }, - { 0x400d2, 0x105 }, - { 0x400d3, 0x107 }, - { 0x400d4, 0x10f }, - { 0x400d5, 0x202 }, - { 0x400d6, 0x20a }, - { 0x400d7, 0x20b }, - { 0x2003a, 0x2 }, - { 0x200be, 0x3 }, - { 0x2000b, 0x3f4 }, - { 0x2000c, 0xe1 }, - { 0x2000d, 0x8ca }, - { 0x2000e, 0x2c }, - { 0x12000b, 0x70 }, - { 0x12000c, 0x19 }, - { 0x12000d, 0xfa }, - { 0x12000e, 0x10 }, - { 0x22000b, 0x1c }, - { 0x22000c, 0x6 }, - { 0x22000d, 0x3e }, - { 0x22000e, 0x10 }, - { 0x9000c, 0x0 }, - { 0x9000d, 0x173 }, - { 0x9000e, 0x60 }, - { 0x9000f, 0x6110 }, - { 0x90010, 0x2152 }, - { 0x90011, 0xdfbd }, - { 0x90012, 0x2060 }, - { 0x90013, 0x6152 }, - { 0x20010, 0x5a }, - { 0x20011, 0x3 }, - { 0x40080, 0xe0 }, - { 0x40081, 0x12 }, - { 0x40082, 0xe0 }, - { 0x40083, 0x12 }, - { 0x40084, 0xe0 }, - { 0x40085, 0x12 }, - { 0x140080, 0xe0 }, - { 0x140081, 0x12 }, - { 0x140082, 0xe0 }, - { 0x140083, 0x12 }, - { 0x140084, 0xe0 }, - { 0x140085, 0x12 }, - { 0x240080, 0xe0 }, - { 0x240081, 0x12 }, - { 0x240082, 0xe0 }, - { 0x240083, 0x12 }, - { 0x240084, 0xe0 }, - { 0x240085, 0x12 }, - { 0x400fd, 0xf }, - { 0x10011, 0x1 }, - { 0x10012, 0x1 }, - { 0x10013, 0x180 }, - { 0x10018, 0x1 }, - { 0x10002, 0x6209 }, - { 0x100b2, 0x1 }, - { 0x101b4, 0x1 }, - { 0x102b4, 0x1 }, - { 0x103b4, 0x1 }, - { 0x104b4, 0x1 }, - { 0x105b4, 0x1 }, - { 0x106b4, 0x1 }, - { 0x107b4, 0x1 }, - { 0x108b4, 0x1 }, - { 0x11011, 0x1 }, - { 0x11012, 0x1 }, - { 0x11013, 0x180 }, - { 0x11018, 0x1 }, - { 0x11002, 0x6209 }, - { 0x110b2, 0x1 }, - { 0x111b4, 0x1 }, - { 0x112b4, 0x1 }, - { 0x113b4, 0x1 }, - { 0x114b4, 0x1 }, - { 0x115b4, 0x1 }, - { 0x116b4, 0x1 }, - { 0x117b4, 0x1 }, - { 0x118b4, 0x1 }, - { 0x12011, 0x1 }, - { 0x12012, 0x1 }, - { 0x12013, 0x180 }, - { 0x12018, 0x1 }, - { 0x12002, 0x6209 }, - { 0x120b2, 0x1 }, - { 0x121b4, 0x1 }, - { 0x122b4, 0x1 }, - { 0x123b4, 0x1 }, - { 0x124b4, 0x1 }, - { 0x125b4, 0x1 }, - { 0x126b4, 0x1 }, - { 0x127b4, 0x1 }, - { 0x128b4, 0x1 }, - { 0x13011, 0x1 }, - { 0x13012, 0x1 }, - { 0x13013, 0x180 }, - { 0x13018, 0x1 }, - { 0x13002, 0x6209 }, - { 0x130b2, 0x1 }, - { 0x131b4, 0x1 }, - { 0x132b4, 0x1 }, - { 0x133b4, 0x1 }, - { 0x134b4, 0x1 }, - { 0x135b4, 0x1 }, - { 0x136b4, 0x1 }, - { 0x137b4, 0x1 }, - { 0x138b4, 0x1 }, - { 0x20089, 0x1 }, - { 0x20088, 0x19 }, - { 0xc0080, 0x2 }, - { 0xd0000, 0x1 } -}; - -static struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 3600mts 1D */ - .drate = 3600, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 400mts 1D */ - .drate = 400, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 100mts 1D */ - .drate = 100, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { - /* P0 3600mts 2D */ - .drate = 3600, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32 = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3600, 400, 100, }, -}; - -#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) -void dh_imx8mp_dhcom_dram_scrub_32g_x32(void) -{ - ddrc_inline_ecc_scrub(0x0,0x7ffffff); - ddrc_inline_ecc_scrub(0x8000000,0xfffffff); - ddrc_inline_ecc_scrub(0x10000000,0x17ffffff); - ddrc_inline_ecc_scrub(0x18000000,0x1fffffff); - ddrc_inline_ecc_scrub(0x20000000,0x27ffffff); - ddrc_inline_ecc_scrub(0x28000000,0x2fffffff); - ddrc_inline_ecc_scrub(0x30000000,0x37ffffff); - ddrc_inline_ecc_scrub_end(0x0,0x3fffffff); -} -#endif diff --git a/board/dhelectronics/dh_imx8mp/spl.c b/board/dhelectronics/dh_imx8mp/spl.c index 727e1ff3774..aab8550023e 100644 --- a/board/dhelectronics/dh_imx8mp/spl.c +++ b/board/dhelectronics/dh_imx8mp/spl.c @@ -104,34 +104,36 @@ static int dh_imx8mp_board_power_init(void) return 0; } -static struct dram_timing_info *dram_timing_info[8] = { - NULL, /* 512 MiB */ - NULL, /* 1024 MiB */ - NULL, /* 1536 MiB */ - &dh_imx8mp_dhcom_dram_timing_16g_x32, /* 2048 MiB */ - NULL, /* 3072 MiB */ - &dh_imx8mp_dhcom_dram_timing_32g_x32, /* 4096 MiB */ - NULL, /* 6144 MiB */ - NULL, /* 8192 MiB */ +typedef void (*patch_func_t)(void); + +static const patch_func_t dram_patch_fn[8] = { + dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_1r, /* 4096 MiB 1-rank */ + NULL, /* 1024 MiB */ + NULL, /* 1536 MiB */ + dh_imx8mp_dhcom_dram_patch_16g_x32_to_16g_x32, /* 2048 MiB */ + NULL, /* 3072 MiB */ + dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_2r, /* 4096 MiB 2-rank */ + NULL, /* 6144 MiB */ + NULL, /* 8192 MiB */ }; static void spl_dram_init(void) { - const u16 size[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 }; u8 memcfg = dh_get_memcfg(); int i; - printf("DDR: %d MiB [0x%x]\n", size[memcfg], memcfg); + printf("DDR: %d MiB [0x%x]\n", dh_imx8mp_dhcom_dram_size[memcfg], memcfg); - if (!dram_timing_info[memcfg]) { + if (!dram_patch_fn[memcfg]) { printf("Unsupported DRAM strapping, trying lowest supported. MEMCFG=0x%x\n", memcfg); - for (i = 0; i < ARRAY_SIZE(dram_timing_info); i++) - if (dram_timing_info[i]) /* Configuration found */ + for (i = 0; i < ARRAY_SIZE(dram_patch_fn); i++) + if (dram_patch_fn[i]) /* Configuration found */ break; } - ddr_init(dram_timing_info[memcfg]); + dram_patch_fn[memcfg](); + ddr_init(dh_imx8mp_dhcom_dram_timing); printf("DDR: Inline ECC %sabled\n", (readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK) ? @@ -139,13 +141,39 @@ static void spl_dram_init(void) } #if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC) +static void dh_imx8mp_dhcom_dram_scrub_16g_x32(void) +{ + ddrc_inline_ecc_scrub(0x0,0x3ffffff); + ddrc_inline_ecc_scrub(0x4000000,0x7ffffff); + ddrc_inline_ecc_scrub(0x8000000,0xbffffff); + ddrc_inline_ecc_scrub(0xc000000,0xfffffff); + ddrc_inline_ecc_scrub(0x10000000,0x13ffffff); + ddrc_inline_ecc_scrub(0x14000000,0x17ffffff); + ddrc_inline_ecc_scrub(0x18000000,0x1bffffff); + ddrc_inline_ecc_scrub_end(0x0,0x1fffffff); +} + +static void dh_imx8mp_dhcom_dram_scrub_32g_x32(void) +{ + ddrc_inline_ecc_scrub(0x0,0x7ffffff); + ddrc_inline_ecc_scrub(0x8000000,0xfffffff); + ddrc_inline_ecc_scrub(0x10000000,0x17ffffff); + ddrc_inline_ecc_scrub(0x18000000,0x1fffffff); + ddrc_inline_ecc_scrub(0x20000000,0x27ffffff); + ddrc_inline_ecc_scrub(0x28000000,0x2fffffff); + ddrc_inline_ecc_scrub(0x30000000,0x37ffffff); + ddrc_inline_ecc_scrub_end(0x0,0x3fffffff); +} + +typedef void (*scrub_func_t)(void); + static const scrub_func_t dram_scrub_fn[8] = { - NULL, /* 512 MiB */ + dh_imx8mp_dhcom_dram_scrub_32g_x32, /* 4096 MiB 1-rank */ NULL, /* 1024 MiB */ NULL, /* 1536 MiB */ dh_imx8mp_dhcom_dram_scrub_16g_x32, /* 2048 MiB */ NULL, /* 3072 MiB */ - dh_imx8mp_dhcom_dram_scrub_32g_x32, /* 4096 MiB */ + dh_imx8mp_dhcom_dram_scrub_32g_x32, /* 4096 MiB 2-rank */ NULL, /* 6144 MiB */ NULL, /* 8192 MiB */ }; diff --git a/board/engicam/imx8mm/spl.c b/board/engicam/imx8mm/spl.c index 5a6bcb1747a..702f0caafab 100644 --- a/board/engicam/imx8mm/spl.c +++ b/board/engicam/imx8mm/spl.c @@ -52,11 +52,6 @@ int board_fit_config_name_match(const char *name) } #endif -int board_early_init_f(void) -{ - return 0; -} - void board_init_f(ulong dummy) { int ret; @@ -65,8 +60,6 @@ void board_init_f(ulong dummy) init_uart_clk(1); - board_early_init_f(); - timer_init(); /* Clear the BSS. */ diff --git a/board/engicam/imx8mp/spl.c b/board/engicam/imx8mp/spl.c index c1aa28a17bc..46c581ea51f 100644 --- a/board/engicam/imx8mp/spl.c +++ b/board/engicam/imx8mp/spl.c @@ -16,9 +16,6 @@ #include <asm/arch/imx8mp_pins.h> #include <asm/arch/sys_proto.h> #include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/arch/ddr.h> #include <power/pmic.h> #include <power/pca9450.h> @@ -33,36 +30,22 @@ void spl_dram_init(void) ddr_init(&dram_timing); } -#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC, - .gp = IMX_GPIO_NR(5, 14), - }, - .sda = { - .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC, - .gp = IMX_GPIO_NR(5, 15), - }, -}; - -#if CONFIG_IS_ENABLED(POWER_LEGACY) -#define I2C_PMIC 0 +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) int power_init_board(void) { - struct pmic *p; + struct udevice *dev; int ret; - ret = power_pca9450_init(I2C_PMIC, 0x25); - if (ret) - printf("power init failed"); - p = pmic_get("PCA9450"); - pmic_probe(p); + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pmic@25\n"); + return 0; + } + if (ret < 0) + return ret; /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); #ifdef CONFIG_IMX8M_LPDDR4 /* @@ -73,22 +56,22 @@ int power_init_board(void) */ #ifdef CONFIG_IMX8M_VDD_SOC_850MV /* set DVS0 to 0.85v for special case*/ - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); #else - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); #endif - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); - pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); /* Kernel uses OD/OD freq for SOC */ /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ - pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); #elif defined(CONFIG_IMX8M_DDR4) /* DDR4 runs at 3200MTS, uses default ND 0.85v for VDD_SOC and VDD_ARM */ - pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); /* Set NVCC_DRAM to 1.2v for DDR4 */ - pmic_reg_write(p, PCA9450_BUCK6OUT, 0x18); + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x18); #endif return 0; @@ -136,8 +119,6 @@ void board_init_f(ulong dummy) enable_tzc380(); - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - power_init_board(); /* DDR initialization */ diff --git a/board/kontron/osm-s-mx93/osm-s-mx93.c b/board/kontron/osm-s-mx93/osm-s-mx93.c index b6feef549d1..02bee34ac66 100644 --- a/board/kontron/osm-s-mx93/osm-s-mx93.c +++ b/board/kontron/osm-s-mx93/osm-s-mx93.c @@ -22,11 +22,6 @@ #include "../common/hw-uid.h" -int board_early_init_f(void) -{ - return 0; -} - #if IS_ENABLED(CONFIG_KONTRON_HW_UID) struct uid_otp_loc uid_otp_locations[] = { { diff --git a/board/kontron/osm-s-mx93/spl.c b/board/kontron/osm-s-mx93/spl.c index 23a90e351fe..a47fc43c6aa 100644 --- a/board/kontron/osm-s-mx93/spl.c +++ b/board/kontron/osm-s-mx93/spl.c @@ -132,8 +132,6 @@ void board_init_f(ulong dummy) arch_cpu_init(); - board_early_init_f(); - spl_early_init(); preloader_console_init(); diff --git a/board/nxp/imx8ulp_evk/imx8ulp_evk.c b/board/nxp/imx8ulp_evk/imx8ulp_evk.c index cc34ecdec20..f4e85efb931 100644 --- a/board/nxp/imx8ulp_evk/imx8ulp_evk.c +++ b/board/nxp/imx8ulp_evk/imx8ulp_evk.c @@ -101,11 +101,6 @@ int board_init(void) return 0; } -int board_early_init_f(void) -{ - return 0; -} - int board_late_init(void) { ulong addr; diff --git a/board/nxp/imx8ulp_evk/spl.c b/board/nxp/imx8ulp_evk/spl.c index 162b3a1a2e0..2d52e16007d 100644 --- a/board/nxp/imx8ulp_evk/spl.c +++ b/board/nxp/imx8ulp_evk/spl.c @@ -74,8 +74,6 @@ void spl_board_init(void) if (ret) return; - board_early_init_f(); - preloader_console_init(); puts("Normal Boot\n"); diff --git a/board/nxp/imx93_frdm/imx93_frdm.c b/board/nxp/imx93_frdm/imx93_frdm.c index fb78a9bd036..e187de74a72 100644 --- a/board/nxp/imx93_frdm/imx93_frdm.c +++ b/board/nxp/imx93_frdm/imx93_frdm.c @@ -90,11 +90,6 @@ static int clear_pd_alert(void) return 0; } -int board_early_init_f(void) -{ - return 0; -} - int board_init(void) { return 0; diff --git a/board/nxp/imx93_frdm/spl.c b/board/nxp/imx93_frdm/spl.c index 006c752d071..068091ba0e9 100644 --- a/board/nxp/imx93_frdm/spl.c +++ b/board/nxp/imx93_frdm/spl.c @@ -156,8 +156,6 @@ void board_init_f(ulong dummy) arch_cpu_init(); - board_early_init_f(); - spl_early_init(); preloader_console_init(); diff --git a/board/nxp/mx6sllevk/mx6sllevk.c b/board/nxp/mx6sllevk/mx6sllevk.c index 9e39e39ac90..3d2397c52c1 100644 --- a/board/nxp/mx6sllevk/mx6sllevk.c +++ b/board/nxp/mx6sllevk/mx6sllevk.c @@ -76,11 +76,6 @@ int power_init_board(void) } #endif -int board_early_init_f(void) -{ - return 0; -} - int board_init(void) { /* Address of boot parameters */ diff --git a/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c b/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c index d80cfd4ab27..ac91da3f4f6 100644 --- a/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c @@ -199,11 +199,6 @@ int board_ehci_hcd_init(int port) } #endif -int board_early_init_f(void) -{ - return 0; -} - #ifdef CONFIG_FSL_QSPI int board_qspi_init(void) { diff --git a/board/nxp/mx6ullevk/mx6ullevk.c b/board/nxp/mx6ullevk/mx6ullevk.c index 189eddefea3..7a02b571c56 100644 --- a/board/nxp/mx6ullevk/mx6ullevk.c +++ b/board/nxp/mx6ullevk/mx6ullevk.c @@ -41,11 +41,6 @@ int mmc_map_to_kernel_blk(int devno) return devno; } -int board_early_init_f(void) -{ - return 0; -} - #ifdef CONFIG_FEC_MXC static int setup_fec(int fec_id) { diff --git a/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c b/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c index 10469aecd0b..b55e92fb051 100644 --- a/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c +++ b/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c @@ -16,11 +16,6 @@ int dram_init(void) return 0; } -int board_early_init_f(void) -{ - return 0; -} - static int setup_fec_clock(void) { if (IS_ENABLED(CONFIG_FEC_MXC) && !IS_ENABLED(CONFIG_CLK_IMX6Q)) { diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig index a72f66ee3f5..6afd03086f7 100644 --- a/board/phytec/common/Kconfig +++ b/board/phytec/common/Kconfig @@ -19,13 +19,13 @@ config PHYTEC_IMX8M_SOM_DETECTION Support of I2C EEPROM based SoM detection. Supported for PHYTEC i.MX8MM/i.MX8MP boards -config PHYTEC_IMX93_SOM_DETECTION - bool "Support SoM detection for i.MX93 PHYTEC platforms" +config PHYTEC_IMX91_93_SOM_DETECTION + bool "Support SoM detection for i.MX91/93 PHYTEC platforms" depends on ARCH_IMX9 && PHYTEC_SOM_DETECTION default y help Support of I2C EEPROM based SoM detection. Supported - for PHYTEC i.MX93 based boards + for PHYTEC i.MX91/93 based boards config PHYTEC_AM62_SOM_DETECTION bool "Support SoM detection for AM62x PHYTEC platforms" diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile index 948f9dab626..e09dea01d49 100644 --- a/board/phytec/common/Makefile +++ b/board/phytec/common/Makefile @@ -10,4 +10,4 @@ endif obj-y += phytec_som_detection.o phytec_som_detection_blocks.o obj-$(CONFIG_ARCH_K3) += am6_som_detection.o k3/ obj-$(CONFIG_ARCH_IMX8M) += imx8m_som_detection.o -obj-$(CONFIG_ARCH_IMX9) += imx93_som_detection.o +obj-$(CONFIG_ARCH_IMX9) += imx91_93_som_detection.o diff --git a/board/phytec/common/imx93_som_detection.c b/board/phytec/common/imx91_93_som_detection.c index eb9574d43b5..bcc5500ae9f 100644 --- a/board/phytec/common/imx93_som_detection.c +++ b/board/phytec/common/imx91_93_som_detection.c @@ -10,18 +10,19 @@ #include <i2c.h> #include <u-boot/crc.h> -#include "imx93_som_detection.h" +#include "imx91_93_som_detection.h" extern struct phytec_eeprom_data eeprom_data; -#if IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION) +#if IS_ENABLED(CONFIG_PHYTEC_IMX91_93_SOM_DETECTION) /* Check if the SoM is actually one of the following products: + * - i.MX91 * - i.MX93 * * Returns 0 in case it's a known SoM. Otherwise, returns 1. */ -u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data) +u8 __maybe_unused phytec_imx91_93_detect(struct phytec_eeprom_data *data) { u8 som; @@ -35,7 +36,7 @@ u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data) som = data->payload.data.data_api2.som_no; debug("%s: som id: %u\n", __func__, som); - if (som == PHYTEC_IMX93_SOM && is_imx93()) + if (som == PHYTEC_IMX91_93_SOM && (is_imx91() || is_imx93())) return 0; pr_err("%s: SoM ID does not match. Wrong EEPROM data?\n", __func__); @@ -43,15 +44,15 @@ u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data) } /* - * Filter PHYTEC i.MX93 SoM options by option index + * Filter PHYTEC i.MX91/93 SoM options by option index * * Returns: * - option value * - PHYTEC_EEPROM_INVAL when the data is invalid * */ -u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data, - enum phytec_imx93_option_index idx) +u8 __maybe_unused phytec_imx91_93_get_opt(struct phytec_eeprom_data *data, + enum phytec_imx91_93_option_index idx) { char *opt; u8 opt_id; @@ -73,39 +74,41 @@ u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data, } /* - * Filter PHYTEC i.MX93 SoM voltage + * Filter PHYTEC i.MX91/93 SoM voltage * * Returns: - * - PHYTEC_IMX93_VOLTAGE_1V8 or PHYTEC_IMX93_VOLTAGE_3V3 + * - PHYTEC_IMX91_93_VOLTAGE_1V8 or PHYTEC_IMX91_93_VOLTAGE_3V3 * - PHYTEC_EEPROM_INVAL when the data is invalid * */ -enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage(struct phytec_eeprom_data *data) +enum phytec_imx91_93_voltage __maybe_unused +phytec_imx91_93_get_voltage(struct phytec_eeprom_data *data) { - u8 option = phytec_imx93_get_opt(data, PHYTEC_IMX93_OPT_FEAT); + u8 option = phytec_imx91_93_get_opt(data, PHYTEC_IMX91_93_OPT_FEAT); if (option == PHYTEC_EEPROM_INVAL) - return PHYTEC_IMX93_VOLTAGE_INVALID; - return (option & 0x01) ? PHYTEC_IMX93_VOLTAGE_1V8 : PHYTEC_IMX93_VOLTAGE_3V3; + return PHYTEC_IMX91_93_VOLTAGE_INVALID; + return (option & 0x01) ? PHYTEC_IMX91_93_VOLTAGE_1V8 : + PHYTEC_IMX91_93_VOLTAGE_3V3; } #else -inline u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data) +inline u8 __maybe_unused phytec_imx91_93_detect(struct phytec_eeprom_data *data) { return 1; } -inline u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data, - enum phytec_imx93_option_index idx) +inline u8 __maybe_unused phytec_imx91_93_get_opt(struct phytec_eeprom_data *data, + enum phytec_imx91_93_option_index idx) { return PHYTEC_EEPROM_INVAL; } -inline enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage +inline enum phytec_imx91_93_voltage __maybe_unused phytec_imx91_93_get_voltage (struct phytec_eeprom_data *data) { return PHYTEC_EEPROM_INVAL; } -#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION) */ +#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX91_93_SOM_DETECTION) */ diff --git a/board/phytec/common/imx91_93_som_detection.h b/board/phytec/common/imx91_93_som_detection.h new file mode 100644 index 00000000000..05ea4cf0868 --- /dev/null +++ b/board/phytec/common/imx91_93_som_detection.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2026 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser <[email protected]> + */ + +#ifndef _PHYTEC_IMX91_93_SOM_DETECTION_H +#define _PHYTEC_IMX91_93_SOM_DETECTION_H + +#include "phytec_som_detection.h" + +#define PHYTEC_IMX91_93_SOM 77 + +enum phytec_imx91_93_option_index { + PHYTEC_IMX91_93_OPT_DDR = 0, + PHYTEC_IMX91_93_OPT_EMMC = 1, + PHYTEC_IMX91_93_OPT_CPU = 2, + PHYTEC_IMX91_93_OPT_FREQ = 3, + PHYTEC_IMX91_93_OPT_NPU = 4, + PHYTEC_IMX91_93_OPT_DISP = 5, + PHYTEC_IMX91_93_OPT_ETH = 6, + PHYTEC_IMX91_93_OPT_FEAT = 7, + PHYTEC_IMX91_93_OPT_TEMP = 8, + PHYTEC_IMX91_93_OPT_BOOT = 9, + PHYTEC_IMX91_93_OPT_LED = 10, + PHYTEC_IMX91_93_OPT_EEPROM = 11, +}; + +enum phytec_imx91_93_voltage { + PHYTEC_IMX91_93_VOLTAGE_INVALID = PHYTEC_EEPROM_INVAL, + PHYTEC_IMX91_93_VOLTAGE_3V3 = 0, + PHYTEC_IMX91_93_VOLTAGE_1V8 = 1, +}; + +enum phytec_imx91_93_ddr_eeprom_code { + PHYTEC_IMX91_93_DDR_INVALID = PHYTEC_EEPROM_INVAL, + PHYTEC_IMX91_93_LPDDR4X_512MB = 0, + PHYTEC_IMX91_93_LPDDR4X_1GB = 1, + PHYTEC_IMX91_93_LPDDR4X_2GB = 2, + PHYTEC_IMX91_93_LPDDR4_512MB = 3, + PHYTEC_IMX91_93_LPDDR4_1GB = 4, + PHYTEC_IMX91_93_LPDDR4_2GB = 5, +}; + +u8 __maybe_unused phytec_imx91_93_detect(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_imx91_93_get_opt(struct phytec_eeprom_data *data, + enum phytec_imx91_93_option_index idx); +enum phytec_imx91_93_voltage __maybe_unused phytec_imx91_93_get_voltage + (struct phytec_eeprom_data *data); + +#endif /* _PHYTEC_IMX91_93_SOM_DETECTION_H */ diff --git a/board/phytec/common/imx93_som_detection.h b/board/phytec/common/imx93_som_detection.h deleted file mode 100644 index a0803b47cbe..00000000000 --- a/board/phytec/common/imx93_som_detection.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2024 PHYTEC Messtechnik GmbH - * Author: Primoz Fiser <[email protected]> - */ - -#ifndef _PHYTEC_IMX93_SOM_DETECTION_H -#define _PHYTEC_IMX93_SOM_DETECTION_H - -#include "phytec_som_detection.h" - -#define PHYTEC_IMX93_SOM 77 - -enum phytec_imx93_option_index { - PHYTEC_IMX93_OPT_DDR = 0, - PHYTEC_IMX93_OPT_EMMC = 1, - PHYTEC_IMX93_OPT_CPU = 2, - PHYTEC_IMX93_OPT_FREQ = 3, - PHYTEC_IMX93_OPT_NPU = 4, - PHYTEC_IMX93_OPT_DISP = 5, - PHYTEC_IMX93_OPT_ETH = 6, - PHYTEC_IMX93_OPT_FEAT = 7, - PHYTEC_IMX93_OPT_TEMP = 8, - PHYTEC_IMX93_OPT_BOOT = 9, - PHYTEC_IMX93_OPT_LED = 10, - PHYTEC_IMX93_OPT_EEPROM = 11, -}; - -enum phytec_imx93_voltage { - PHYTEC_IMX93_VOLTAGE_INVALID = PHYTEC_EEPROM_INVAL, - PHYTEC_IMX93_VOLTAGE_3V3 = 0, - PHYTEC_IMX93_VOLTAGE_1V8 = 1, -}; - -enum phytec_imx93_ddr_eeprom_code { - PHYTEC_IMX93_DDR_INVALID = PHYTEC_EEPROM_INVAL, - PHYTEC_IMX93_LPDDR4X_512MB = 0, - PHYTEC_IMX93_LPDDR4X_1GB = 1, - PHYTEC_IMX93_LPDDR4X_2GB = 2, - PHYTEC_IMX93_LPDDR4_512MB = 3, - PHYTEC_IMX93_LPDDR4_1GB = 4, - PHYTEC_IMX93_LPDDR4_2GB = 5, -}; - -u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data); -u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data, - enum phytec_imx93_option_index idx); -enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage - (struct phytec_eeprom_data *data); - -#endif /* _PHYTEC_IMX93_SOM_DETECTION_H */ diff --git a/board/phytec/imx8mp-libra-fpsc/spl.c b/board/phytec/imx8mp-libra-fpsc/spl.c index 08111641aa6..aa22ad0030c 100644 --- a/board/phytec/imx8mp-libra-fpsc/spl.c +++ b/board/phytec/imx8mp-libra-fpsc/spl.c @@ -9,9 +9,6 @@ #include <asm/arch/imx8mp_pins.h> #include <asm/arch/sys_proto.h> #include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/gpio.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/mach-imx/iomux-v3.h> #include <hang.h> #include <init.h> #include <log.h> @@ -46,45 +43,32 @@ void spl_dram_init(void) ddr_init(&dram_timing); } -#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC, - .gp = IMX_GPIO_NR(5, 14), - }, - .sda = { - .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC, - .gp = IMX_GPIO_NR(5, 15), - }, -}; - int power_init_board(void) { - struct pmic *p; + struct udevice *dev; int ret; - ret = power_pca9450_init(0, 0x25); - if (ret) - printf("power init failed"); - p = pmic_get("PCA9450"); - pmic_probe(p); + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pmic@25\n"); + return 0; + } + if (ret < 0) + return ret; /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); /* Increase VDD_SOC and VDD_ARM to OD voltage 0.95V */ - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); - pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); /* Set BUCK1 DVS1 to suspend controlled through PMIC_STBY_REQ */ - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); - pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); /* Set WDOG_B_CFG to cold reset */ - pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); + pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); return 0; } @@ -120,8 +104,6 @@ void board_init_f(ulong dummy) enable_tzc380(); - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - power_init_board(); /* DDR initialization */ diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index fc7aefd0073..fc6f5104925 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -117,45 +117,32 @@ out: ddr_init(&dram_timing); } -#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC, - .gp = IMX_GPIO_NR(5, 14), - }, - .sda = { - .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC, - .gp = IMX_GPIO_NR(5, 15), - }, -}; - int power_init_board(void) { - struct pmic *p; + struct udevice *dev; int ret; - ret = power_pca9450_init(0, 0x25); - if (ret) - printf("power init failed"); - p = pmic_get("PCA9450"); - pmic_probe(p); + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pmic@25\n"); + return 0; + } + if (ret < 0) + return ret; /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); /* Increase VDD_SOC and VDD_ARM to OD voltage 0.95V */ - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); - pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); /* Set BUCK1 DVS1 to suspend controlled through PMIC_STBY_REQ */ - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); - pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); /* Set WDOG_B_CFG to cold reset */ - pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); + pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); return 0; } @@ -193,8 +180,6 @@ void board_init_f(ulong dummy) enable_tzc380(); - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - power_init_board(); /* DDR initialization */ diff --git a/board/phytec/phycore_imx91_93/Kconfig b/board/phytec/phycore_imx91_93/Kconfig new file mode 100644 index 00000000000..87fd915e5a8 --- /dev/null +++ b/board/phytec/phycore_imx91_93/Kconfig @@ -0,0 +1,47 @@ + +if TARGET_PHYCORE_IMX91 || TARGET_PHYCORE_IMX93 + +config SYS_BOARD + default "phycore_imx91_93" + +config SYS_VENDOR + default "phytec" + +config SYS_CONFIG_NAME + default "phycore_imx91_93" + +config PHYCORE_IMX91_93_RAM_TYPE_FIX + bool "Set phyCORE-i.MX91/93 RAM type and size fix instead of detecting" + default false + help + RAM type and size is being automatically detected with the help + of the PHYTEC EEPROM introspection data. + Set RAM type to a fix value instead. + +choice + prompt "phyCORE-i.MX91/93 RAM type" + depends on PHYCORE_IMX91_93_RAM_TYPE_FIX + default PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_1GB + +config PHYCORE_IMX91_93_RAM_TYPE_LPDDR4_1GB + bool "LPDDR4 1GB RAM" + help + Set RAM type fixed to LPDDR4 and RAM size fixed to 1GB + for phyCORE-i.MX91/93. + +config PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_1GB + bool "LPDDR4X 1GB RAM" + help + Set RAM type fixed to LPDDR4X and RAM size fixed to 1GB + for phyCORE-i.MX91/93. + +config PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_2GB + bool "LPDDR4X 2GB RAM" + help + Set RAM type fixed to LPDDR4X and RAM size fixed to 2GB + for phyCORE-i.MX91/93. + +endchoice + +source "board/phytec/common/Kconfig" +endif diff --git a/board/phytec/phycore_imx91_93/MAINTAINERS b/board/phytec/phycore_imx91_93/MAINTAINERS new file mode 100644 index 00000000000..573d1c36a5e --- /dev/null +++ b/board/phytec/phycore_imx91_93/MAINTAINERS @@ -0,0 +1,16 @@ +phyCORE-i.MX91/93 +M: Mathieu Othacehe <[email protected]> +R: Christoph Stoidner <[email protected]> +W: https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ +S: Maintained +F: arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi +F: arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi +F: arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi +F: board/phytec/phycore_imx91_93/ +F: board/phytec/common/imx91_93_som_detection.c +F: board/phytec/common/imx91_93_som_detection.h +F: configs/imx91-phycore_defconfig +F: configs/imx93-phycore_defconfig +F: include/configs/phycore_imx91_93.h +F: doc/board/phytec/imx91-93-phycore.rst diff --git a/board/phytec/phycore_imx93/Makefile b/board/phytec/phycore_imx91_93/Makefile index dd5085e160f..976ecb306f7 100644 --- a/board/phytec/phycore_imx93/Makefile +++ b/board/phytec/phycore_imx91_93/Makefile @@ -7,8 +7,13 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += phycore-imx93.o +obj-y += phycore-imx91-93.o ifdef CONFIG_XPL_BUILD -obj-y += spl.o lpddr4_timing.o +obj-y += spl.o +ifdef CONFIG_IMX91 +obj-$(CONFIG_IMX9_LPDDR4X) += lpddr4_timing_imx91.o +else +obj-$(CONFIG_IMX9_LPDDR4X) += lpddr4_timing_imx93.o +endif endif diff --git a/board/phytec/phycore_imx91_93/lpddr4_timing_imx91.c b/board/phytec/phycore_imx91_93/lpddr4_timing_imx91.c new file mode 100644 index 00000000000..ddc8094f080 --- /dev/null +++ b/board/phytec/phycore_imx91_93/lpddr4_timing_imx91.c @@ -0,0 +1,1998 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2024 NXP + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Christoph Stoidner <[email protected]> + * + * Code generated with DDR Tool v3.3.0_1.8-d1cdb7d3. + * DDR PHY FW2022.01 + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000bf}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000412}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x13542110}, + {0x4e300104, 0xF8990011}, + {0x4e300108, 0x636E88CC}, + {0x4e30010C, 0x00614070}, + {0x4e300124, 0x124E0000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x31D00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x0000001A}, + {0x4e300254, 0x00A000A0}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x1633160D}, + {0x4e300304, 0x00A0180C}, + {0x4e300308, 0x0C280927}, + }, + { + {0x01, 0xC4}, + {0x02, 0x24}, + {0x03, 0x23}, + {0x0b, 0x44}, + {0x0c, 0x49}, + {0x0e, 0x4A}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x010A1100}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0xBABA0068}, + {0x4e30010C, 0x00610158}, + {0x4e300124, 0x09270000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30400000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x0000000D}, + {0x4e300254, 0x004C004C}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xA4}, + {0x02, 0x52}, + {0x03, 0x23}, + {0x0b, 0x44}, + {0x0c, 0x49}, + {0x0e, 0x4A}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00051000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E620A48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00240024}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x23}, + {0x0b, 0x44}, + {0x0c, 0x49}, + {0x0e, 0x4A}, + {0x16, 0x04}, + }, + 1, + }, + +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x0}, + {0x100a1, 0x1}, + {0x100a2, 0x2}, + {0x100a3, 0x3}, + {0x100a4, 0x4}, + {0x100a5, 0x5}, + {0x100a6, 0x6}, + {0x100a7, 0x7}, + {0x110a0, 0x0}, + {0x110a1, 0x1}, + {0x110a2, 0x2}, + {0x110a3, 0x3}, + {0x110a4, 0x4}, + {0x110a5, 0x5}, + {0x110a6, 0x6}, + {0x110a7, 0x7}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x21005f, 0x1ff}, + {0x21015f, 0x1ff}, + {0x21105f, 0x1ff}, + {0x21115f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0xa}, + {0x1200c5, 0x2}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x1}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0x61f}, + {0x10149, 0x61f}, + {0x11049, 0x61f}, + {0x11149, 0x61f}, + {0x110049, 0x61f}, + {0x110149, 0x61f}, + {0x111049, 0x61f}, + {0x111149, 0x61f}, + {0x210049, 0x61f}, + {0x210149, 0x61f}, + {0x211049, 0x61f}, + {0x211149, 0x61f}, + {0x43, 0x7f}, + {0x1043, 0x7f}, + {0x2043, 0x7f}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x11}, + {0x2009b, 0x2}, + {0x20008, 0x258}, + {0x120008, 0x12c}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x104}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x104}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x104}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x41}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 0x0}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x0}, + {0x40030, 0x0}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x0}, + {0x40031, 0x0}, + {0x40051, 0x0}, + {0x40071, 0x0}, + {0x40012, 0x0}, + {0x40032, 0x0}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x0}, + {0x40033, 0x0}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x0}, + {0x40034, 0x0}, + {0x40054, 0x0}, + {0x40074, 0x0}, + {0x40015, 0x0}, + {0x40035, 0x0}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x0}, + {0x40036, 0x0}, + {0x40056, 0x0}, + {0x40076, 0x0}, + {0x40017, 0x0}, + {0x40037, 0x0}, + {0x40057, 0x0}, + {0x40077, 0x0}, + {0x40018, 0x0}, + {0x40038, 0x0}, + {0x40058, 0x0}, + {0x40078, 0x0}, + {0x40019, 0x0}, + {0x40039, 0x0}, + {0x40059, 0x0}, + {0x40079, 0x0}, + {0x4001a, 0x0}, + {0x4003a, 0x0}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x0}, + {0x900ac, 0x0}, + {0x900ad, 0x0}, + {0x900ae, 0x0}, + {0x900af, 0x0}, + {0x900b0, 0x0}, + {0x900b1, 0x0}, + {0x900b2, 0x0}, + {0x900b3, 0x0}, + {0x900b4, 0x0}, + {0x900b5, 0x0}, + {0x900b6, 0x0}, + {0x900b7, 0x0}, + {0x900b8, 0x0}, + {0x900b9, 0x0}, + {0x900ba, 0x0}, + {0x900bb, 0x0}, + {0x900bc, 0x0}, + {0x900bd, 0x0}, + {0x900be, 0x0}, + {0x900bf, 0x0}, + {0x900c0, 0x0}, + {0x900c1, 0x0}, + {0x900c2, 0x0}, + {0x900c3, 0x0}, + {0x900c4, 0x0}, + {0x900c5, 0x0}, + {0x900c6, 0x0}, + {0x900c7, 0x0}, + {0x900c8, 0x0}, + {0x900c9, 0x0}, + {0x900ca, 0x0}, + {0x900cb, 0x0}, + {0x900cc, 0x0}, + {0x900cd, 0x0}, + {0x900ce, 0x0}, + {0x900cf, 0x0}, + {0x900d0, 0x0}, + {0x900d1, 0x0}, + {0x900d2, 0x0}, + {0x900d3, 0x0}, + {0x900d4, 0x0}, + {0x900d5, 0x0}, + {0x900d6, 0x0}, + {0x900d7, 0x0}, + {0x900d8, 0x0}, + {0x900d9, 0x0}, + {0x900da, 0x0}, + {0x900db, 0x0}, + {0x900dc, 0x0}, + {0x900dd, 0x0}, + {0x900de, 0x0}, + {0x900df, 0x0}, + {0x900e0, 0x0}, + {0x900e1, 0x0}, + {0x900e2, 0x0}, + {0x900e3, 0x0}, + {0x900e4, 0x0}, + {0x900e5, 0x0}, + {0x900e6, 0x0}, + {0x900e7, 0x0}, + {0x900e8, 0x0}, + {0x900e9, 0x0}, + {0x900ea, 0x0}, + {0x900eb, 0x0}, + {0x900ec, 0x0}, + {0x900ed, 0x0}, + {0x900ee, 0x0}, + {0x900ef, 0x0}, + {0x900f0, 0x0}, + {0x900f1, 0x0}, + {0x900f2, 0x0}, + {0x900f3, 0x0}, + {0x900f4, 0x0}, + {0x900f5, 0x0}, + {0x900f6, 0x0}, + {0x900f7, 0x0}, + {0x900f8, 0x0}, + {0x900f9, 0x0}, + {0x900fa, 0x0}, + {0x900fb, 0x0}, + {0x900fc, 0x0}, + {0x900fd, 0x0}, + {0x900fe, 0x0}, + {0x900ff, 0x0}, + {0x90100, 0x0}, + {0x90101, 0x0}, + {0x90102, 0x0}, + {0x90103, 0x0}, + {0x90104, 0x0}, + {0x90105, 0x0}, + {0x90106, 0x0}, + {0x90107, 0x0}, + {0x90108, 0x0}, + {0x90109, 0x0}, + {0x9010a, 0x0}, + {0x9010b, 0x0}, + {0x9010c, 0x0}, + {0x9010d, 0x0}, + {0x9010e, 0x0}, + {0x9010f, 0x0}, + {0x90110, 0x0}, + {0x90111, 0x0}, + {0x90112, 0x0}, + {0x90113, 0x0}, + {0x90114, 0x0}, + {0x90115, 0x0}, + {0x90116, 0x0}, + {0x90117, 0x0}, + {0x90118, 0x0}, + {0x90119, 0x0}, + {0x9011a, 0x0}, + {0x9011b, 0x0}, + {0x9011c, 0x0}, + {0x9011d, 0x0}, + {0x9011e, 0x0}, + {0x9011f, 0x0}, + {0x90120, 0x0}, + {0x90121, 0x0}, + {0x90122, 0x0}, + {0x90123, 0x0}, + {0x90124, 0x0}, + {0x90125, 0x0}, + {0x90126, 0x0}, + {0x90127, 0x0}, + {0x90128, 0x0}, + {0x90129, 0x0}, + {0x9012a, 0x0}, + {0x9012b, 0x0}, + {0x9012c, 0x0}, + {0x9012d, 0x0}, + {0x9012e, 0x0}, + {0x9012f, 0x0}, + {0x90130, 0x0}, + {0x90131, 0x0}, + {0x90132, 0x0}, + {0x90133, 0x0}, + {0x90134, 0x0}, + {0x90135, 0x0}, + {0x90136, 0x0}, + {0x90137, 0x0}, + {0x90138, 0x0}, + {0x90139, 0x0}, + {0x9013a, 0x0}, + {0x9013b, 0x0}, + {0x9013c, 0x0}, + {0x9013d, 0x0}, + {0x9013e, 0x0}, + {0x9013f, 0x0}, + {0x90140, 0x0}, + {0x90141, 0x0}, + {0x90142, 0x0}, + {0x90143, 0x0}, + {0x90144, 0x0}, + {0x90145, 0x0}, + {0x90146, 0x0}, + {0x90147, 0x0}, + {0x90148, 0x0}, + {0x90149, 0x0}, + {0x9014a, 0x0}, + {0x9014b, 0x0}, + {0x9014c, 0x0}, + {0x9014d, 0x0}, + {0x9014e, 0x0}, + {0x9014f, 0x0}, + {0x90150, 0x0}, + {0x90151, 0x0}, + {0x90152, 0x0}, + {0x90153, 0x0}, + {0x90154, 0x0}, + {0x90155, 0x0}, + {0x90156, 0x0}, + {0x90157, 0x0}, + {0x90158, 0x0}, + {0x90159, 0x0}, + {0x9015a, 0x0}, + {0x9015b, 0x0}, + {0x9015c, 0x0}, + {0x9015d, 0x0}, + {0x9015e, 0x0}, + {0x9015f, 0x0}, + {0x90160, 0x0}, + {0x90161, 0x0}, + {0x90162, 0x0}, + {0x90163, 0x0}, + {0x90164, 0x0}, + {0x90165, 0x0}, + {0x90166, 0x0}, + {0x90167, 0x0}, + {0x90168, 0x0}, + {0x90169, 0x0}, + {0x9016a, 0x0}, + {0x9016b, 0x0}, + {0x9016c, 0x0}, + {0x9016d, 0x0}, + {0x9016e, 0x0}, + {0x9016f, 0x0}, + {0x90170, 0x0}, + {0x90171, 0x0}, + {0x90172, 0x0}, + {0x90173, 0x0}, + {0x90174, 0x0}, + {0x90175, 0x0}, + {0x90176, 0x0}, + {0x90177, 0x0}, + {0x90178, 0x0}, + {0x90179, 0x0}, + {0x9017a, 0x0}, + {0x9017b, 0x0}, + {0x9017c, 0x0}, + {0x9017d, 0x0}, + {0x9017e, 0x0}, + {0x9017f, 0x0}, + {0x90180, 0x0}, + {0x90181, 0x0}, + {0x90182, 0x0}, + {0x90183, 0x0}, + {0x90184, 0x0}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x0}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x0}, + {0x90017, 0x0}, + {0x9001f, 0x0}, + {0x90026, 0x0}, + {0x400d0, 0x0}, + {0x400d1, 0x0}, + {0x400d2, 0x0}, + {0x400d3, 0x0}, + {0x400d4, 0x0}, + {0x400d5, 0x0}, + {0x400d6, 0x0}, + {0x400d7, 0x0}, + {0x200be, 0x0}, + {0x2000b, 0x0}, + {0x2000c, 0x0}, + {0x2000d, 0x0}, + {0x2000e, 0x0}, + {0x12000b, 0x0}, + {0x12000c, 0x0}, + {0x12000d, 0x0}, + {0x12000e, 0x0}, + {0x22000b, 0x0}, + {0x22000c, 0x0}, + {0x22000d, 0x0}, + {0x22000e, 0x0}, + {0x9000c, 0x0}, + {0x9000d, 0x0}, + {0x9000e, 0x0}, + {0x9000f, 0x0}, + {0x90010, 0x0}, + {0x90011, 0x0}, + {0x90012, 0x0}, + {0x90013, 0x0}, + {0x20010, 0x0}, + {0x20011, 0x0}, + {0x120010, 0x0}, + {0x120011, 0x0}, + {0x40080, 0x0}, + {0x40081, 0x0}, + {0x40082, 0x0}, + {0x40083, 0x0}, + {0x40084, 0x0}, + {0x40085, 0x0}, + {0x140080, 0x0}, + {0x140081, 0x0}, + {0x140082, 0x0}, + {0x140083, 0x0}, + {0x140084, 0x0}, + {0x140085, 0x0}, + {0x240080, 0x0}, + {0x240081, 0x0}, + {0x240082, 0x0}, + {0x240083, 0x0}, + {0x240084, 0x0}, + {0x240085, 0x0}, + {0x400fd, 0x0}, + {0x400f1, 0x0}, + {0x10011, 0x0}, + {0x10012, 0x0}, + {0x10013, 0x0}, + {0x10018, 0x0}, + {0x10002, 0x0}, + {0x100b2, 0x0}, + {0x101b4, 0x0}, + {0x102b4, 0x0}, + {0x103b4, 0x0}, + {0x104b4, 0x0}, + {0x105b4, 0x0}, + {0x106b4, 0x0}, + {0x107b4, 0x0}, + {0x108b4, 0x0}, + {0x11011, 0x0}, + {0x11012, 0x0}, + {0x11013, 0x0}, + {0x11018, 0x0}, + {0x11002, 0x0}, + {0x110b2, 0x0}, + {0x111b4, 0x0}, + {0x112b4, 0x0}, + {0x113b4, 0x0}, + {0x114b4, 0x0}, + {0x115b4, 0x0}, + {0x116b4, 0x0}, + {0x117b4, 0x0}, + {0x118b4, 0x0}, + {0x20089, 0x0}, + {0xc0080, 0x0}, + {0x200cb, 0x0}, + {0x10068, 0x0}, + {0x10069, 0x0}, + {0x10168, 0x0}, + {0x10169, 0x0}, + {0x10268, 0x0}, + {0x10269, 0x0}, + {0x10368, 0x0}, + {0x10369, 0x0}, + {0x10468, 0x0}, + {0x10469, 0x0}, + {0x10568, 0x0}, + {0x10569, 0x0}, + {0x10668, 0x0}, + {0x10669, 0x0}, + {0x10768, 0x0}, + {0x10769, 0x0}, + {0x10868, 0x0}, + {0x10869, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x11268, 0x0}, + {0x11269, 0x0}, + {0x11368, 0x0}, + {0x11369, 0x0}, + {0x11468, 0x0}, + {0x11469, 0x0}, + {0x11568, 0x0}, + {0x11569, 0x0}, + {0x11668, 0x0}, + {0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x100080, 0x0}, + {0x101080, 0x0}, + {0x102080, 0x0}, + {0x110020, 0x0}, + {0x110080, 0x0}, + {0x110081, 0x0}, + {0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x14}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x23}, + {0x5401b, 0x4944}, + {0x5401c, 0x4a08}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x23}, + {0x54021, 0x4944}, + {0x54022, 0x4a08}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x2324}, + {0x54034, 0x4400}, + {0x54035, 0x849}, + {0x54036, 0x4a}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x2324}, + {0x5403a, 0x4400}, + {0x5403b, 0x849}, + {0x5403c, 0x4a}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x4b0}, + {0x54004, 0x4}, + {0x54006, 0x14}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x52a4}, + {0x5401a, 0x23}, + {0x5401b, 0x4944}, + {0x5401c, 0x4a08}, + {0x5401e, 0x4}, + {0x5401f, 0x52a4}, + {0x54020, 0x23}, + {0x54021, 0x4944}, + {0x54022, 0x4a08}, + {0x54024, 0x4}, + {0x54032, 0xa400}, + {0x54033, 0x2352}, + {0x54034, 0x4400}, + {0x54035, 0x849}, + {0x54036, 0x4a}, + {0x54037, 0x400}, + {0x54038, 0xa400}, + {0x54039, 0x2352}, + {0x5403a, 0x4400}, + {0x5403b, 0x849}, + {0x5403c, 0x4a}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x14}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x23}, + {0x5401b, 0x4944}, + {0x5401c, 0x4a00}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x23}, + {0x54021, 0x4944}, + {0x54022, 0x4a00}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x2309}, + {0x54034, 0x4400}, + {0x54035, 0x49}, + {0x54036, 0x4a}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x2309}, + {0x5403a, 0x4400}, + {0x5403b, 0x49}, + {0x5403c, 0x4a}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x14}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x23}, + {0x5401b, 0x4944}, + {0x5401c, 0x4a08}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x23}, + {0x54021, 0x4944}, + {0x54022, 0x4a08}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x2324}, + {0x54034, 0x4400}, + {0x54035, 0x849}, + {0x54036, 0x4a}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x2324}, + {0x5403a, 0x4400}, + {0x5403b, 0x849}, + {0x5403c, 0x4a}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x2a3}, + {0x2000c, 0x96}, + {0x2000d, 0x5dc}, + {0x2000e, 0x2c}, + {0x12000b, 0x152}, + {0x12000c, 0x4b}, + {0x12000d, 0x2ee}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1200mts 1D */ + .drate = 1200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 1200, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/phytec/phycore_imx93/lpddr4_timing.c b/board/phytec/phycore_imx91_93/lpddr4_timing_imx93.c index f1261f6a92a..f1261f6a92a 100644 --- a/board/phytec/phycore_imx93/lpddr4_timing.c +++ b/board/phytec/phycore_imx91_93/lpddr4_timing_imx93.c diff --git a/board/phytec/phycore_imx93/phycore-imx93.c b/board/phytec/phycore_imx91_93/phycore-imx91-93.c index 036c9f5de7e..2605a3bd09e 100644 --- a/board/phytec/phycore_imx93/phycore-imx93.c +++ b/board/phytec/phycore_imx91_93/phycore-imx91-93.c @@ -11,7 +11,7 @@ #include <env.h> #include <fdt_support.h> -#include "../common/imx93_som_detection.h" +#include "../common/imx91_93_som_detection.h" #define EEPROM_ADDR 0x50 @@ -55,13 +55,13 @@ int board_late_init(void) static void emmc_fixup(void *blob, struct phytec_eeprom_data *data) { - enum phytec_imx93_voltage voltage = phytec_imx93_get_voltage(data); + enum phytec_imx91_93_voltage voltage = phytec_imx91_93_get_voltage(data); int offset; - if (voltage == PHYTEC_IMX93_VOLTAGE_INVALID) + if (voltage == PHYTEC_IMX91_93_VOLTAGE_INVALID) goto err; - if (voltage == PHYTEC_IMX93_VOLTAGE_1V8) { + if (voltage == PHYTEC_IMX91_93_VOLTAGE_1V8) { offset = fdt_node_offset_by_compat_reg(blob, "fsl,imx93-usdhc", 0x42850000); if (offset) diff --git a/board/phytec/phycore_imx93/phycore_imx93.env b/board/phytec/phycore_imx91_93/phycore_imx91_93.env index c8fb3a875da..a39359869d6 100644 --- a/board/phytec/phycore_imx93/phycore_imx93.env +++ b/board/phytec/phycore_imx91_93/phycore_imx91_93.env @@ -9,6 +9,8 @@ fdtoverlay_addr_r=0x900c0000 ip_dyn=yes kernel_addr_r=0x88000000 nfsroot=/srv/nfs +#ifdef CONFIG_IMX93 prepare_mcore=setenv optargs "${optargs} clk-imx93.mcore_booted" +#endif scriptaddr=0x83500000 sd_dev=1 /* This is needed by built-in uuu flash scripts */ diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx91_93/spl.c index aa7d562911a..92441c5af32 100644 --- a/board/phytec/phycore_imx93/spl.c +++ b/board/phytec/phycore_imx91_93/spl.c @@ -19,7 +19,7 @@ #include <power/pca9450.h> #include <spl.h> -#include "../common/imx93_som_detection.h" +#include "../common/imx91_93_som_detection.h" DECLARE_GLOBAL_DATA_PTR; @@ -50,32 +50,38 @@ void spl_board_init(void) void spl_dram_init(void) { int ret; - enum phytec_imx93_ddr_eeprom_code ddr_opt = PHYTEC_IMX93_DDR_INVALID; + enum phytec_imx91_93_ddr_eeprom_code ddr_opt = PHYTEC_IMX91_93_DDR_INVALID; ret = phytec_eeprom_data_setup(NULL, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR); - if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) + if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_FIX)) goto out; - ret = phytec_imx93_detect(NULL); + ret = phytec_imx91_93_detect(NULL); if (!ret) phytec_print_som_info(NULL); - if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) { - if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB)) - ddr_opt = PHYTEC_IMX93_LPDDR4X_1GB; - else if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB)) - ddr_opt = PHYTEC_IMX93_LPDDR4X_2GB; + if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_FIX)) { + if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_LPDDR4_1GB)) + ddr_opt = PHYTEC_IMX91_93_LPDDR4_1GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_1GB)) + ddr_opt = PHYTEC_IMX91_93_LPDDR4X_1GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_2GB)) + ddr_opt = PHYTEC_IMX91_93_LPDDR4X_2GB; } else { - ddr_opt = phytec_imx93_get_opt(NULL, PHYTEC_IMX93_OPT_DDR); + ddr_opt = phytec_imx91_93_get_opt(NULL, PHYTEC_IMX91_93_OPT_DDR); } switch (ddr_opt) { - case PHYTEC_IMX93_LPDDR4X_1GB: - if (is_voltage_mode(VOLT_LOW_DRIVE)) + case PHYTEC_IMX91_93_LPDDR4_1GB: + /* Timings statically set for i.MX91 LPDDR4 1GB. */ + break; + case PHYTEC_IMX91_93_LPDDR4X_1GB: + if (IS_ENABLED(CONFIG_IMX93) && is_voltage_mode(VOLT_LOW_DRIVE)) set_dram_timings_1gb_lpddr4x_900mhz(); break; - case PHYTEC_IMX93_LPDDR4X_2GB: - set_dram_timings_2gb_lpddr4x(); + case PHYTEC_IMX91_93_LPDDR4X_2GB: + if (IS_ENABLED(CONFIG_IMX93)) + set_dram_timings_2gb_lpddr4x(); break; default: goto out; @@ -84,7 +90,7 @@ void spl_dram_init(void) return; out: puts("Could not detect correct RAM type and size. Fall back to default.\n"); - if (is_voltage_mode(VOLT_LOW_DRIVE)) + if (IS_ENABLED(CONFIG_IMX93) && is_voltage_mode(VOLT_LOW_DRIVE)) set_dram_timings_1gb_lpddr4x_900mhz(); ddr_init(&dram_timing); } @@ -185,10 +191,12 @@ void board_init_f(ulong dummy) /* DDR initialization */ spl_dram_init(); - /* Put M33 into CPUWAIT for following kick */ - ret = m33_prepare(); - if (!ret) - printf("M33 prepare ok\n"); + if (IS_ENABLED(CONFIG_IMX93)) { + /* Put M33 into CPUWAIT for following kick */ + ret = m33_prepare(); + if (!ret) + printf("M33 prepare ok\n"); + } board_init_r(NULL, 0); } diff --git a/board/phytec/phycore_imx93/Kconfig b/board/phytec/phycore_imx93/Kconfig deleted file mode 100644 index 09f26e89e33..00000000000 --- a/board/phytec/phycore_imx93/Kconfig +++ /dev/null @@ -1,41 +0,0 @@ - -if TARGET_PHYCORE_IMX93 - -config SYS_BOARD - default "phycore_imx93" - -config SYS_VENDOR - default "phytec" - -config SYS_CONFIG_NAME - default "phycore_imx93" - -config PHYCORE_IMX93_RAM_TYPE_FIX - bool "Set phyCORE-i.MX93 RAM type and size fix instead of detecting" - default false - help - RAM type and size is being automatically detected with the help - of the PHYTEC EEPROM introspection data. - Set RAM type to a fix value instead. - -choice - prompt "phyCORE-i.MX93 RAM type" - depends on PHYCORE_IMX93_RAM_TYPE_FIX - default PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB - -config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB - bool "LPDDR4X 1GB RAM" - help - Set RAM type fixed to LPDDR4X and RAM size fixed to 1GB - for phyCORE-i.MX93. - -config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB - bool "LPDDR4X 2GB RAM" - help - Set RAM type fixed to LPDDR4X and RAM size fixed to 2GB - for phyCORE-i.MX93. - -endchoice - -source "board/phytec/common/Kconfig" -endif diff --git a/board/phytec/phycore_imx93/MAINTAINERS b/board/phytec/phycore_imx93/MAINTAINERS deleted file mode 100644 index 0b087bf1ef2..00000000000 --- a/board/phytec/phycore_imx93/MAINTAINERS +++ /dev/null @@ -1,12 +0,0 @@ -phyCORE-i.MX93 -M: Mathieu Othacehe <[email protected]> -R: Christoph Stoidner <[email protected]> -W: https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ -S: Maintained -F: arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi -F: board/phytec/phycore_imx93/ -F: board/phytec/common/imx93_som_detection.c -F: board/phytec/common/imx93_som_detection.h -F: configs/imx93-phycore_defconfig -F: include/configs/phycore_imx93.h diff --git a/board/purism/librem5/librem5.c b/board/purism/librem5/librem5.c index a2bc0c08f0b..3640ef232c8 100644 --- a/board/purism/librem5/librem5.c +++ b/board/purism/librem5/librem5.c @@ -31,11 +31,6 @@ #include <usb/xhci.h> #include "librem5.h" -int board_early_init_f(void) -{ - return 0; -} - #if IS_ENABLED(CONFIG_LOAD_ENV_FROM_MMC_BOOT_PARTITION) uint board_mmc_get_env_part(struct mmc *mmc) { diff --git a/board/purism/librem5/spl.c b/board/purism/librem5/spl.c index 568224f9732..a104ee5c2aa 100644 --- a/board/purism/librem5/spl.c +++ b/board/purism/librem5/spl.c @@ -547,8 +547,6 @@ void board_init_f(ulong dummy) gpio_direction_output(WIFI_EN, 1); #endif - board_early_init_f(); - timer_init(); preloader_console_init(); diff --git a/board/toradex/smarc-imx95/MAINTAINERS b/board/toradex/smarc-imx95/MAINTAINERS index 73517d36f1f..96d349c06b2 100644 --- a/board/toradex/smarc-imx95/MAINTAINERS +++ b/board/toradex/smarc-imx95/MAINTAINERS @@ -1,6 +1,4 @@ Toradex SMARC iMX95 -F: arch/arm/dts/imx95-toradex-smarc.dtsi -F: arch/arm/dts/imx95-toradex-smarc-dev.dts F: arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi F: board/toradex/smarc-imx95/ F: configs/toradex-smarc-imx95_defconfig diff --git a/board/toradex/verdin-imx8mp/spl.c b/board/toradex/verdin-imx8mp/spl.c index b39058b1b5d..44678a976ca 100644 --- a/board/toradex/verdin-imx8mp/spl.c +++ b/board/toradex/verdin-imx8mp/spl.c @@ -8,12 +8,8 @@ #include <log.h> #include <spl.h> #include <asm/arch/clock.h> -#include <asm/arch/imx8mp_pins.h> #include <asm/arch/sys_proto.h> #include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/arch/ddr.h> #include <dm/device.h> #include <dm/uclass.h> @@ -68,36 +64,21 @@ void spl_board_init(void) puts("Normal Boot\n"); } -#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC, - .gp = IMX_GPIO_NR(5, 14), - }, - .sda = { - .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC, - .gp = IMX_GPIO_NR(5, 15), - }, -}; - -#if CONFIG_IS_ENABLED(POWER_LEGACY) -#define I2C_PMIC 0 int power_init_board(void) { - struct pmic *p; + struct udevice *dev; int ret; - ret = power_pca9450_init(I2C_PMIC, 0x25); - if (ret) - printf("power init failed\n"); - p = pmic_get("PCA9450"); - pmic_probe(p); + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pmic@25\n"); + return 0; + } + if (ret < 0) + return ret; /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); /* * increase VDD_SOC to typical value 0.95V before first @@ -107,23 +88,22 @@ int power_init_board(void) */ if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) /* set DVS0 to 0.85v for special case */ - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); else - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1c); - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); - pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1c); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); /* Kernel uses OD/OD freq for SoC */ /* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95v */ - pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1c); + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c); /* set LDO4 and CONFIG2 to enable the I2C level translator */ - pmic_reg_write(p, PCA9450_LDO4CTRL, 0x59); - pmic_reg_write(p, PCA9450_CONFIG2, 0x1); + pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59); + pmic_reg_write(dev, PCA9450_CONFIG2, 0x1); return 0; } -#endif #if IS_ENABLED(CONFIG_SPL_LOAD_FIT) int board_fit_config_name_match(const char *name) @@ -156,9 +136,6 @@ void board_init_f(ulong dummy) enable_tzc380(); - /* Adjust PMIC voltage to 1.0V for 800 MHz */ - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - /* PMIC initialization */ power_init_board(); diff --git a/board/tq/MAINTAINERS b/board/tq/MAINTAINERS new file mode 100644 index 00000000000..e6f3dc4da21 --- /dev/null +++ b/board/tq/MAINTAINERS @@ -0,0 +1,8 @@ +TQMA6 +M: Max Merchel <[email protected]> +S: Maintained +W: https://www.tq-group.com/en/products/tq-embedded/ +F: arch/arm/dts/*mba6*.dts* +F: arch/arm/dts/*tqma6*.dts* +F: configs/tqma6*config diff --git a/board/tq/common/Kconfig b/board/tq/common/Kconfig new file mode 100644 index 00000000000..a1896929ea3 --- /dev/null +++ b/board/tq/common/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2023-2026 TQ-Systems GmbH <[email protected]>, +# D-82229 Seefeld, Germany. +# Author: Markus Niebel, Max Merchel +# + +config TQ_COMMON_BB + bool + default y + +config TQ_COMMON_SDMMC + bool diff --git a/board/tq/common/Makefile b/board/tq/common/Makefile new file mode 100644 index 00000000000..ac564a713fd --- /dev/null +++ b/board/tq/common/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2016-2026 TQ-Systems GmbH <[email protected]>, +# D-82229 Seefeld, Germany. +# Author: Markus Niebel +# + +obj-$(CONFIG_TQ_COMMON_BB) += tq_bb.o +obj-$(CONFIG_TQ_COMMON_SDMMC) += tq_sdmmc.o diff --git a/board/tq/common/tq_bb.c b/board/tq/common/tq_bb.c new file mode 100644 index 00000000000..40cff6ab178 --- /dev/null +++ b/board/tq/common/tq_bb.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2022-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + */ + +#include <linux/types.h> + +#include "tq_bb.h" + +int __weak tq_bb_board_mmc_getwp(struct mmc *mmc) +{ + return 0; +} + +int __weak tq_bb_board_mmc_getcd(struct mmc *mmc) +{ + return 0; +} + +int __weak tq_bb_board_mmc_init(struct bd_info *bis) +{ + return 0; +} + +int __weak tq_bb_board_early_init_f(void) +{ + return 0; +} + +int __weak tq_bb_board_init(void) +{ + return 0; +} + +int __weak tq_bb_board_late_init(void) +{ + return 0; +} + +int __weak tq_bb_checkboard(void) +{ + return 0; +} + +void __weak tq_bb_board_quiesce_devices(void) +{ + ; +} + +const char * __weak tq_bb_get_boardname(void) +{ + return "INVALID"; +} + +#if IS_ENABLED(CONFIG_SPL_BUILD) +void __weak tq_bb_board_init_f(ulong dummy) +{ + ; +} + +void __weak tq_bb_spl_board_init(void) +{ + ; +} +#endif /* IS_ENABLED(CONFIG_SPL_BUILD) */ + +/* + * Device Tree Support + */ +#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) +int __weak tq_bb_ft_board_setup(void *blob, struct bd_info *bis) +{ + return 0; +} + +#endif /* IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) */ diff --git a/board/tq/common/tq_bb.h b/board/tq/common/tq_bb.h new file mode 100644 index 00000000000..5b1b3f62a8c --- /dev/null +++ b/board/tq/common/tq_bb.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2013-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + */ + +#ifndef __TQ_BB_H +#define __TQ_BB_H + +struct mmc; +struct bd_info; +struct node_info; + +int tq_bb_board_mmc_getwp(struct mmc *mmc); +int tq_bb_board_mmc_getcd(struct mmc *mmc); +int tq_bb_board_mmc_init(struct bd_info *bis); + +int tq_bb_board_early_init_f(void); +int tq_bb_board_init(void); +int tq_bb_board_late_init(void); +int tq_bb_checkboard(void); +void tq_bb_board_quiesce_devices(void); + +const char *tq_bb_get_boardname(void); + +#if IS_ENABLED(CONFIG_SPL_BUILD) +void tq_bb_board_init_f(ulong dummy); +void tq_bb_spl_board_init(void); +#endif + +/* + * Device Tree Support + */ +#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) +int tq_bb_ft_board_setup(void *blob, struct bd_info *bis); +#endif /* IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT) */ + +#endif /* __TQ_BB_H */ diff --git a/board/tq/common/tq_sdmmc.c b/board/tq/common/tq_sdmmc.c new file mode 100644 index 00000000000..b7336faa0c7 --- /dev/null +++ b/board/tq/common/tq_sdmmc.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright (C) 2018-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + */ + +#include <command.h> +#include <env.h> +#include <mmc.h> +#include <stdbool.h> +#include <vsprintf.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> +#include <linux/errno.h> + +#include "tq_bb.h" + +static int check_mmc_autodetect(void) +{ + /* NO or unset: 0 / YES: 1 */ + return (env_get_yesno("mmcautodetect") > 0); +} + +/* This should be defined for each board */ +__weak int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no; +} + +void board_late_mmc_env_init(void) +{ + char cmd[32]; + u32 dev_no; + + dev_no = mmc_get_env_dev(); + + if (!check_mmc_autodetect()) + return; + + env_set_ulong("mmcdev", dev_no); + env_set_ulong("mmcblkdev", mmc_map_to_kernel_blk(dev_no)); + + snprintf(cmd, ARRAY_SIZE(cmd), "mmc dev %d", dev_no); + run_command(cmd, 0); +} diff --git a/board/tq/tqma6/Kconfig b/board/tq/tqma6/Kconfig index e62228d73d0..21bcb8e0cb3 100644 --- a/board/tq/tqma6/Kconfig +++ b/board/tq/tqma6/Kconfig @@ -7,7 +7,8 @@ config SYS_VENDOR default "tq" config SYS_CONFIG_NAME - default "tqma6" + default "tqma6_mba6" if MBA6 + default "tqma6_wru4" if WRU4 choice prompt "TQMa6 SoC variant" @@ -71,6 +72,8 @@ choice config MBA6 bool "TQMa6 on MBa6 Starterkit" + select TQ_COMMON_BB + select TQ_COMMON_SDMMC select USB select CMD_USB select USB_STORAGE @@ -91,6 +94,7 @@ config MBA6 config WRU4 bool "OHB WRU-IV" + select TQ_COMMON_BB help Select the OHB Systems AG WRU-IV baseboard. @@ -106,4 +110,6 @@ config IMX_CONFIG default "board/tq/tqma6/tqma6dl.cfg" if TQMA6DL default "board/tq/tqma6/tqma6s.cfg" if TQMA6S +source "board/tq/common/Kconfig" + endif diff --git a/board/tq/tqma6/MAINTAINERS b/board/tq/tqma6/MAINTAINERS deleted file mode 100644 index 1d3f7d2cf63..00000000000 --- a/board/tq/tqma6/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -TQ-SYSTEMS TQMA6 BOARD -M: Markus Niebel <[email protected]> -L: TQ-Systems OSS Team <[email protected]> -S: Maintained -F: board/tq/tqma6/ -F: include/configs/tqma6.h -F: configs/tqma6*_defconfig diff --git a/board/tq/tqma6/Makefile b/board/tq/tqma6/Makefile index f1b39844ac6..ecebc28315d 100644 --- a/board/tq/tqma6/Makefile +++ b/board/tq/tqma6/Makefile @@ -6,6 +6,7 @@ # obj-y := tqma6.o +obj-y += tqma6_emmc.o obj-$(CONFIG_MBA6) += tqma6_mba6.o obj-$(CONFIG_WRU4) += tqma6_wru4.o diff --git a/board/tq/tqma6/tqma6.c b/board/tq/tqma6/tqma6.c index 75d36240a1e..005f08c4e5f 100644 --- a/board/tq/tqma6/tqma6.c +++ b/board/tq/tqma6/tqma6.c @@ -26,7 +26,8 @@ #include <power/pfuze100_pmic.h> #include <power/pmic.h> -#include "tqma6_bb.h" +#include "tqma6_emmc.h" +#include "../common/tq_bb.h" DECLARE_GLOBAL_DATA_PTR; @@ -37,19 +38,21 @@ int dram_init(void) return 0; } -static const uint16_t tqma6_emmc_dsr = 0x0100; - int board_early_init_f(void) { - return tqma6_bb_board_early_init_f(); + return tq_bb_board_early_init_f(); } int board_init(void) { + struct mmc *mmc = find_mmc_device(0); + /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - tqma6_bb_board_init(); + tqma6_mmc_detect_card_type(mmc); + + tq_bb_board_init(); return 0; } @@ -96,11 +99,12 @@ int board_late_init(void) { env_set("board_name", tqma6_get_boardname()); - tqma6_bb_board_late_init(); + tq_bb_board_late_init(); printf("Board: %s on a %s\n", tqma6_get_boardname(), - tqma6_bb_get_boardname()); - return 0; + tq_bb_get_boardname()); + + return tq_bb_checkboard(); } /* @@ -110,17 +114,24 @@ int board_late_init(void) #define MODELSTRLEN 32u int ft_board_setup(void *blob, struct bd_info *bd) { + struct mmc *mmc = find_mmc_device(0); char modelstr[MODELSTRLEN]; snprintf(modelstr, MODELSTRLEN, "TQ %s on %s", tqma6_get_boardname(), - tqma6_bb_get_boardname()); + tq_bb_get_boardname()); do_fixup_by_path_string(blob, "/", "model", modelstr); fdt_fixup_memory(blob, (u64)PHYS_SDRAM, (u64)gd->ram_size); - /* bring in eMMC dsr settings */ - do_fixup_by_path_u32(blob, - "/soc/aips-bus@02100000/usdhc@02198000", - "dsr", tqma6_emmc_dsr, 2); - tqma6_bb_ft_board_setup(blob, bd); + + /* bring in eMMC dsr settings if needed */ + if (mmc && (!mmc_init(mmc))) { + if (tqma6_emmc_need_dsr(mmc) > 0) { + tqma6_ft_fixup_emmc_dsr(blob, + "/soc/bus@2100000/mmc@2198000", + TQMA6_EMMC_DSR); + } + } else { + puts("eMMC: not present?\n"); + } return 0; } diff --git a/board/tq/tqma6/tqma6.env b/board/tq/tqma6/tqma6.env new file mode 100644 index 00000000000..b1d7e5cbbcf --- /dev/null +++ b/board/tq/tqma6/tqma6.env @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * TQMa6 environment + */ + +#include <env/tq/tq-imx-shared.env> + +board=tqma6 +boot_os=bootz "${kernel_addr_r}" - "${fdt_addr_r}" +emmc_bootp_start=TQMA6_MMC_UBOOT_SECTOR_START +emmc_dev=0 +fdt_addr_r=TQMA6_FDT_ADDRESS +fdtoverlay_addr_r=TQMA6_FDT_OVERLAY_ADDR +image=zImage +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +pxefile_addr_r=CONFIG_SYS_LOAD_ADDR +ramdisk_addr_r=TQMA6_INITRD_ADDRESS +mmcautodetect=yes +mmcblkdev=0 +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +netdev=eth0 +sd_dev=1 +uboot=u-boot-with-spl.imx +uboot_mmc_start=TQMA6_MMC_UBOOT_SECTOR_START +uboot_mmc_size=TQMA6_MMC_UBOOT_SECTOR_COUNT +uboot_spi_sector_size=TQMA6_SPI_FLASH_SECTOR_SIZE +uboot_spi_start=TQMA6_SPI_UBOOT_START +uboot_spi_size=TQMA6_SPI_UBOOT_SIZE + +#ifdef CONFIG_USB_FUNCTION_FASTBOOT + +/* 0=user 1=boot1 2=boot2 */ +fastboot_mmc_boot_partition = 1 + +fastboot_partition_alias_all=CONFIG_FASTBOOT_FLASH_MMC_DEV :0 + +fastboot_raw_partition_bootloader= + TQMA6_MMC_UBOOT_SECTOR_START TQMA6_MMC_UBOOT_SECTOR_COUNT mmcpart + "${fastboot_mmc_boot_partition}" + +fastbootcmd=fastboot usb 0 + +#endif /* CONFIG_USB_FUNCTION_FASTBOOT */ diff --git a/board/tq/tqma6/tqma6_bb.h b/board/tq/tqma6/tqma6_bb.h deleted file mode 100644 index e17e6ad3f57..00000000000 --- a/board/tq/tqma6/tqma6_bb.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2013-2014 TQ-Systems GmbH <[email protected]>, - * D-82229 Seefeld, Germany. - * Author: Markus Niebel - */ - -#ifndef __TQMA6_BB__ -#define __TQMA6_BB__ - -int tqma6_bb_board_mmc_getwp(struct mmc *mmc); -int tqma6_bb_board_mmc_getcd(struct mmc *mmc); -int tqma6_bb_board_mmc_init(struct bd_info *bis); - -int tqma6_bb_board_early_init_f(void); -int tqma6_bb_board_init(void); -int tqma6_bb_board_late_init(void); -int tqma6_bb_checkboard(void); - -const char *tqma6_bb_get_boardname(void); -/* - * Device Tree Support - */ -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd); -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ - -#endif diff --git a/board/tq/tqma6/tqma6_emmc.c b/board/tq/tqma6/tqma6_emmc.c new file mode 100644 index 00000000000..dd7c4d45c5c --- /dev/null +++ b/board/tq/tqma6/tqma6_emmc.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2017-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + */ + +#include <fdt_support.h> +#include <mmc.h> + +#include "tqma6_emmc.h" + +struct emmc_dsr_lookup { + uint mfgid; + char *pnm; + int dsr_needed; +}; + +static const struct emmc_dsr_lookup dsr_tbl[] = { + /* Micron, eMMC 4.41 */ + { 0xfe, "MMC02G", 1 }, + { 0xfe, "MMC04G", 1 }, + { 0xfe, "MMC08G", 1 }, + /* Micron, eMMC 5.0 4 GB*/ + { 0x13, "Q1J54A", 1 }, + { 0x13, "Q2J54A", 1 }, + /* Micron, eMMC 5.0 8 GB*/ + { 0x13, "Q2J55L", 0 }, + /* Samsung, eMMC 5.0 */ + { 0x15, "8GSD3R", 0 }, + { 0x15, "AGSD3R", 0 }, + { 0x15, "BGSD3R", 0 }, + { 0x15, "CGSD3R", 0 }, + /* SanDisk, iNAND 7250 5.1 */ + { 0x45, "DG4008", 0 }, + { 0x45, "DG4016", 0 }, + { 0x45, "DG4032", 0 }, + { 0x45, "DG4064", 0 }, + /* Kingston */ + { 0x100, "?????", 0 }, +}; + +int tqma6_emmc_need_dsr(const struct mmc *mmc) +{ + uint mfgid = mmc->cid[0] >> 24; + char name[7]; + int ret = -1; + size_t i; + + if (IS_SD(mmc)) + return 0; + + sprintf(name, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, (mmc->cid[1] >> 24), + (mmc->cid[1] >> 16) & 0xff, (mmc->cid[1] >> 8) & 0xff, + mmc->cid[1] & 0xff, (mmc->cid[2] >> 24)); + + for (i = 0; i < ARRAY_SIZE(dsr_tbl) && (ret < 0); ++i) { + if (dsr_tbl[i].mfgid == mfgid && + (!strncmp(name, dsr_tbl[i].pnm, 6))) { + ret = dsr_tbl[i].dsr_needed; + debug("MFG: %x PNM: %s\n", mfgid, name); + } + } + + if (ret < 0) { + printf("eMMC unknown: MFG: %x PNM: %s\n", mfgid, name); + /* request DSR, even if not known if supported to be safe */ + ret = 1; + } + + return ret; +} + +void tqma6_ft_fixup_emmc_dsr(void *blob, const char *path, u32 value) +{ + do_fixup_by_path_u32(blob, path, "dsr", value, 1); +} + +void tqma6_mmc_detect_card_type(struct mmc *mmc) +{ + struct mmc *emmc = find_mmc_device(0); + + if (emmc != mmc) + return; + + if (tqma6_emmc_need_dsr(mmc) > 0) + mmc_set_dsr(mmc, TQMA6_EMMC_DSR); +} diff --git a/board/tq/tqma6/tqma6_emmc.h b/board/tq/tqma6/tqma6_emmc.h new file mode 100644 index 00000000000..5ab6c3ac11d --- /dev/null +++ b/board/tq/tqma6/tqma6_emmc.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2017-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + */ + +#ifndef __TQMA6_EMMC_H__ +#define __TQMA6_EMMC_H__ + +#define TQMA6_EMMC_DSR 0x0100 + +struct mmc; + +int tqma6_emmc_need_dsr(const struct mmc *mmc); +void tqma6_ft_fixup_emmc_dsr(void *blob, const char *path, u32 value); +void tqma6_mmc_detect_card_type(struct mmc *mmc); + +#endif /* __TQMA6_EMMC_H__ */ diff --git a/board/tq/tqma6/tqma6_mba6.c b/board/tq/tqma6/tqma6_mba6.c index 46989102fec..32aeb1b07c8 100644 --- a/board/tq/tqma6/tqma6_mba6.c +++ b/board/tq/tqma6/tqma6_mba6.c @@ -31,7 +31,7 @@ #include <mmc.h> #include <netdev.h> -#include "tqma6_bb.h" +#include "../common/tq_bb.h" #if defined(CONFIG_TQMA6Q) @@ -126,34 +126,20 @@ int board_phy_config(struct phy_device *phydev) return 0; } -int tqma6_bb_board_early_init_f(void) -{ - return 0; -} - -int tqma6_bb_board_init(void) +int tq_bb_board_init(void) { mba6_setup_iomuxc_enet(); return 0; } -int tqma6_bb_board_late_init(void) -{ - return 0; -} - -const char *tqma6_bb_get_boardname(void) +const char *tq_bb_get_boardname(void) { return "MBa6x"; } -/* - * Device Tree Support - */ -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd) +int tq_bb_board_late_init(void) { - /* TBD */ + board_late_mmc_env_init(); + return 0; } -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/tq/tqma6/tqma6_wru4.c b/board/tq/tqma6/tqma6_wru4.c index 7acefc7b064..a7dc8fca109 100644 --- a/board/tq/tqma6/tqma6_wru4.c +++ b/board/tq/tqma6/tqma6_wru4.c @@ -33,7 +33,7 @@ #include <mmc.h> #include <netdev.h> -#include "tqma6_bb.h" +#include "../common/tq_bb.h" /* UART */ #define UART4_PAD_CTRL ( \ @@ -95,7 +95,7 @@ static struct fsl_esdhc_cfg usdhc2_cfg = { .max_bus_width = 4, }; -int tqma6_bb_board_mmc_getcd(struct mmc *mmc) +int tq_bb_board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; int ret = 0; @@ -106,7 +106,7 @@ int tqma6_bb_board_mmc_getcd(struct mmc *mmc) return ret; } -int tqma6_bb_board_mmc_getwp(struct mmc *mmc) +int tq_bb_board_mmc_getwp(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; int ret = 0; @@ -117,7 +117,7 @@ int tqma6_bb_board_mmc_getwp(struct mmc *mmc) return ret; } -int tqma6_bb_board_mmc_init(struct bd_info *bis) +int tq_bb_board_mmc_init(struct bd_info *bis) { int ret; @@ -256,14 +256,14 @@ static void gpio_init(void) gpio_direction_output(GPIO_UART3_PWRON, 0); } -int tqma6_bb_board_early_init_f(void) +int tq_bb_board_early_init_f(void) { setup_iomuxc_uart4(); return 0; } -int tqma6_bb_board_init(void) +int tq_bb_board_init(void) { setup_iomuxc_enet(); @@ -279,12 +279,7 @@ int tqma6_bb_board_init(void) return 0; } -int tqma6_bb_board_late_init(void) -{ - return 0; -} - -const char *tqma6_bb_get_boardname(void) +const char *tq_bb_get_boardname(void) { return "WRU-IV"; } @@ -331,13 +326,3 @@ int board_ehci_power(int port, int on) return 0; } - -/* - * Device Tree Support - */ -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd) -{ - /* TBD */ -} -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig index 0649d746907..ee55d804980 100644 --- a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig +++ b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig @@ -7,9 +7,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x400000 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mp-icore-mx8mp-edimm2.2" CONFIG_TARGET_IMX8MP_ICORE_MX8MP=y @@ -78,8 +75,6 @@ CONFIG_CLK_IMX8MP=y CONFIG_MXC_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y -# CONFIG_SPL_DM_I2C is not set -CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_SUPPORT_EMMC_BOOT=y @@ -98,12 +93,13 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y -CONFIG_SPL_POWER_LEGACY=y -CONFIG_POWER_PCA9450=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -CONFIG_SPL_POWER_I2C=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y diff --git a/configs/imx8mp-libra-fpsc_defconfig b/configs/imx8mp-libra-fpsc_defconfig index a23e604425d..4a8938d3e43 100644 --- a/configs/imx8mp-libra-fpsc_defconfig +++ b/configs/imx8mp-libra-fpsc_defconfig @@ -9,7 +9,6 @@ CONFIG_SF_DEFAULT_SPEED=80000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3C0000 CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-libra-rdk-fpsc" CONFIG_IMX8M_OPTEE_LOAD_ADDR=0x7e000000 @@ -105,8 +104,6 @@ CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_FASTBOOT_MMC_USER_NAME="mmc2" CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y -# CONFIG_SPL_DM_I2C is not set -CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x51 CONFIG_SUPPORT_EMMC_BOOT=y @@ -138,15 +135,16 @@ CONFIG_PHY_IMX8MQ_USB=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y -CONFIG_SPL_POWER_LEGACY=y CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y -CONFIG_POWER_PCA9450=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -CONFIG_SPL_POWER_I2C=y CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig index ff6cd8e6c98..41025dc1142 100644 --- a/configs/imx8ulp_evk_defconfig +++ b/configs/imx8ulp_evk_defconfig @@ -32,7 +32,6 @@ CONFIG_BOOTCOMMAND="bootflow scan -l; run bsp_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2068 -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/imx91-phycore_defconfig b/configs/imx91-phycore_defconfig new file mode 100644 index 00000000000..b1e13bade84 --- /dev/null +++ b/configs/imx91-phycore_defconfig @@ -0,0 +1,167 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SOURCE_FILE="phycore_imx91_93" +CONFIG_NR_DRAM_BANKS=2 +CONFIG_PHYTEC_SOM_DETECTION=y +CONFIG_PHYTEC_EEPROM_BUS=2 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x700000 +CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx91-phyboard-segin" +CONFIG_TARGET_PHYCORE_IMX91=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x204E0000 +CONFIG_SPL_TEXT_BASE=0x204A0000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20498000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x720000 +CONFIG_CMD_DEKBLOB=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_REMAKE_ELF=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_BOOTSTD_FULL=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_DEFAULT_FDT_FILE="oftree" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg" +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_BOOTDEV is not set +# CONFIG_CMD_BOOTMETH is not set +# CONFIG_CMD_BOOTSTD is not set +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_BUS=2 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_SIZE=4096 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth0" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_CLK_IMX93=y +CONFIG_SAVED_DRAM_TIMING_BASE=0x2049C000 +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_GPIO_HOG=y +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PHY_TI_GENERIC=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX93=y +CONFIG_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_CI_UDC=y +CONFIG_ULP_WATCHDOG=y +# CONFIG_RSA is not set +# CONFIG_SPL_SHA256 is not set +CONFIG_LZO=y +CONFIG_BZIP2=y diff --git a/configs/imx93-phycore_defconfig b/configs/imx93-phycore_defconfig index 3fb6e7b5f1d..6ae6e405fbf 100644 --- a/configs/imx93-phycore_defconfig +++ b/configs/imx93-phycore_defconfig @@ -5,7 +5,7 @@ CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x20000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SOURCE_FILE="phycore_imx93" +CONFIG_ENV_SOURCE_FILE="phycore_imx91_93" CONFIG_NR_DRAM_BANKS=2 CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_PHYTEC_EEPROM_BUS=2 diff --git a/configs/imx93_frdm_defconfig b/configs/imx93_frdm_defconfig index c35ebc3b492..adcf2125c73 100644 --- a/configs/imx93_frdm_defconfig +++ b/configs/imx93_frdm_defconfig @@ -35,7 +35,6 @@ CONFIG_BOOTCOMMAND="bootflow scan -lb; run bsp_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx93-11x11-frdm.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/librem5_defconfig b/configs/librem5_defconfig index e6ad27ed1bf..d9d32bf5a50 100644 --- a/configs/librem5_defconfig +++ b/configs/librem5_defconfig @@ -36,7 +36,6 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_CONSOLE_IS_IN_ENV=y # CONFIG_SYS_DEVICE_NULLDEV is not set -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig index f126c6e1e79..06474cb94e8 100644 --- a/configs/mx6sllevk_defconfig +++ b/configs/mx6sllevk_defconfig @@ -16,7 +16,6 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_SYS_PBSIZE=532 -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig index 134475d24d8..b340d9c9f95 100644 --- a/configs/mx6sllevk_plugin_defconfig +++ b/configs/mx6sllevk_plugin_defconfig @@ -17,7 +17,6 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_SYS_PBSIZE=532 -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig index 36c342bcfe2..983b8aeb407 100644 --- a/configs/mx6ull_14x14_evk_defconfig +++ b/configs/mx6ull_14x14_evk_defconfig @@ -16,7 +16,6 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_SYS_PBSIZE=532 -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig index 28961f5a13f..c88d18dbf9b 100644 --- a/configs/mx6ull_14x14_evk_plugin_defconfig +++ b/configs/mx6ull_14x14_evk_plugin_defconfig @@ -17,7 +17,6 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_SYS_PBSIZE=532 -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig index 9db0251a8a0..8f4a92e4a5f 100644 --- a/configs/mx6ulz_14x14_evk_defconfig +++ b/configs/mx6ulz_14x14_evk_defconfig @@ -16,7 +16,6 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" CONFIG_SYS_PBSIZE=532 -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 2fcf7db9e5c..51d9737afb3 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -10,7 +10,6 @@ CONFIG_SF_DEFAULT_SPEED=80000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3C0000 CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-phyboard-pollux-rdk" CONFIG_IMX8M_OPTEE_LOAD_ADDR=0x7e000000 @@ -113,8 +112,6 @@ CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_FASTBOOT_MMC_USER_NAME="mmc2" CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y -# CONFIG_SPL_DM_I2C is not set -CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x51 CONFIG_SUPPORT_EMMC_BOOT=y @@ -144,15 +141,16 @@ CONFIG_PHY_IMX8MQ_USB=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y -CONFIG_SPL_POWER_LEGACY=y CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y -CONFIG_POWER_PCA9450=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -CONFIG_SPL_POWER_I2C=y CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y diff --git a/configs/toradex-smarc-imx95_defconfig b/configs/toradex-smarc-imx95_defconfig index ad908949b59..61abeff1afb 100644 --- a/configs/toradex-smarc-imx95_defconfig +++ b/configs/toradex-smarc-imx95_defconfig @@ -10,7 +10,7 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx95-toradex-smarc-dev" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx95-toradex-smarc-dev" CONFIG_TARGET_TORADEX_SMARC_IMX95=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SYS_MONITOR_LEN=524288 @@ -125,6 +125,7 @@ CONFIG_SPL_FIRMWARE=y # CONFIG_SCMI_AGENT_SMCCC is not set CONFIG_IMX_SM_CPU=y CONFIG_IMX_SM_LMM=y +CONFIG_GPIO_HOG=y CONFIG_IMX_RGPIO2P=y CONFIG_DM_PCA953X=y CONFIG_SPL_DM_PCA953X=y diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index 99749c50194..455a601b07d 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -7,10 +7,6 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFDE00 -CONFIG_SYS_I2C_MXC_I2C1=y -CONFIG_SYS_I2C_MXC_I2C2=y -CONFIG_SYS_I2C_MXC_I2C3=y -CONFIG_SYS_I2C_MXC_I2C4=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-verdin-wifi-dev" CONFIG_TARGET_VERDIN_IMX8MP=y @@ -119,8 +115,6 @@ CONFIG_SPL_GPIO_HOG=y CONFIG_MXC_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y -# CONFIG_SPL_DM_I2C is not set -CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_I2C_EEPROM=y @@ -152,14 +146,15 @@ CONFIG_PHY_IMX8M_PCIE=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y -CONFIG_SPL_POWER_LEGACY=y CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y -CONFIG_POWER_PCA9450=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR_PCA9450=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -CONFIG_SPL_POWER_I2C=y CONFIG_DM_RNG=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y diff --git a/doc/board/phytec/imx93-phycore.rst b/doc/board/phytec/imx91-93-phycore.rst index bd110a3ebee..42bcda100e0 100644 --- a/doc/board/phytec/imx93-phycore.rst +++ b/doc/board/phytec/imx91-93-phycore.rst @@ -1,9 +1,11 @@ .. SPDX-License-Identifier: GPL-2.0+ -phyCORE-i.MX 93 -=============== +phyCORE-i.MX 91/93 +================== -U-Boot for the phyCORE-i.MX 93. +U-Boot for the phyCORE-i.MX 91/93. Both SoC variants, that is i.MX 91 and i.MX 93, +are supported by same board code, however each variant uses different defconfig +and ATF/ELE firmware blobs. Please follow the correct steps for the populated SoC. Quick Start ----------- @@ -18,7 +20,17 @@ Get and Build the ARM Trusted firmware Note: srctree is U-Boot source directory Get ATF from: https://github.com/nxp-imx/imx-atf/ -branch: lf_v2.8 +branch: lf_v2.12 + +For phyCORE-i.MX 91 variant: + +.. code-block:: bash + + $ unset LDFLAGS + $ make PLAT=imx91 bl31 + $ cp build/imx91/release/bl31.bin $(srctree) + +For phyCORE-i.MX 93 variant: .. code-block:: bash @@ -41,14 +53,24 @@ Get ahab-container.img .. code-block:: bash - $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-sentinel-0.11.bin - $ chmod +x firmware-sentinel-0.11.bin - $ ./firmware-sentinel-0.11.bin - $ cp firmware-sentinel-0.11/mx93a1-ahab-container.img $(srctree) + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-1.3.0-17945fc.bin + $ chmod +x firmware-ele-imx-1.3.0-17945fc.bin + $ ./firmware-ele-imx-1.3.0-17945fc.bin + $ cp firmware-ele-imx-1.3.0-17945fc/mx91a0-ahab-container.img $(srctree) + $ cp firmware-ele-imx-1.3.0-17945fc/mx93a1-ahab-container.img $(srctree) Build U-Boot ------------ +For phyCORE-i.MX 91 variant: + +.. code-block:: bash + + $ make imx91-phycore_defconfig + $ make + +For phyCORE-i.MX 93 variant: + .. code-block:: bash $ make imx93-phycore_defconfig diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst index dd9edd792f4..4519079ab3d 100644 --- a/doc/board/phytec/index.rst +++ b/doc/board/phytec/index.rst @@ -8,7 +8,7 @@ PHYTEC imx8mp-libra-fpsc imx8mm-phygate-tauri-l - imx93-phycore + imx91-93-phycore phycore-am62x phycore-am62ax phycore-am64x diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index fe694f6022c..eb01c6cf700 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -3,6 +3,7 @@ if ARM || PPC config FSL_CAAM bool "Freescale Crypto Driver Support" select SHA_HW_ACCEL + select ARCH_MISC_INIT # hw_sha1() under drivers/crypto, and needed with SHA_HW_ACCEL select MISC if DM imply SPL_CRYPTO if (ARM && SPL) diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 11c4ccbfc55..8d853ecf2c2 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -728,15 +728,31 @@ static int imx_pcie_dm_write_config(struct udevice *dev, pci_dev_t bdf, static int imx_pcie_dm_probe(struct udevice *dev) { struct imx_pcie_priv *priv = dev_get_priv(dev); + int ret; #if CONFIG_IS_ENABLED(DM_REGULATOR) device_get_supply_regulator(dev, "vpcie-supply", &priv->vpcie); #endif /* if PERST# valid from dt then assert it */ - gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio, - GPIOD_IS_OUT); - priv->reset_active_high = dev_read_bool(dev, "reset-gpio-active-high"); + ret = gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio, + GPIOD_IS_OUT); + if (!ret) { + /* + * Legacy property, invert assert logic based on + * reset-gpio-active-high. This won't work if flags are not + * matching the reset-gpio-active-high. + */ + priv->reset_active_high = dev_read_bool(dev, "reset-gpio-active-high"); + } else { + /* + * Linux kernel upstream property, assert active level based on + * GPIO flags, thus leave priv->reset_active_high=0. + */ + gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio, + GPIOD_IS_OUT); + } + if (dm_gpio_is_valid(&priv->reset_gpio)) { dm_gpio_set_value(&priv->reset_gpio, priv->reset_active_high ? 0 : 1); diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index 7ed35aa3e66..117e36376b7 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -275,7 +275,7 @@ int espi_xfer(struct fsl_spi_slave *fsl, uint cs, unsigned int bitlen, } } if (data_in) { - memcpy(data_in, buffer + 2 * cmd_len, tran_len); + memcpy(data_in, buffer + rx_offset, tran_len); if (*buffer == 0x0b) { data_in += tran_len; data_len -= tran_len; diff --git a/include/configs/phycore_imx93.h b/include/configs/phycore_imx91_93.h index 07364dff403..02fa1d9b274 100644 --- a/include/configs/phycore_imx93.h +++ b/include/configs/phycore_imx91_93.h @@ -6,8 +6,8 @@ * Copyright (C) 2024 Mathieu Othacehe <[email protected]> */ -#ifndef __PHYCORE_IMX93_H -#define __PHYCORE_IMX93_H +#ifndef __PHYCORE_IMX91_93_H +#define __PHYCORE_IMX91_93_H #include <linux/sizes.h> #include <asm/arch/imx-regs.h> @@ -25,4 +25,4 @@ /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG3_BASE_ADDR -#endif /* __PHYCORE_IMX93_H */ +#endif /* __PHYCORE_IMX91_93_H */ diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 5e89cd6937a..00610e76869 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -7,256 +7,22 @@ * Configuration settings for the TQ-Systems TQMa6<Q,D,DL,S> module. */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/stringify.h> - -/* place code in last 4 MiB of RAM */ +#ifndef __TQMA6_CONFIG_H +#define __TQMA6_CONFIG_H #include "mx6_common.h" -#if defined(CONFIG_TQMA6S) -#define PHYS_SDRAM_SIZE (512u * SZ_1M) -#elif defined(CONFIG_TQMA6DL) -#define PHYS_SDRAM_SIZE (SZ_1G) -#elif defined(CONFIG_TQMA6Q) -#define PHYS_SDRAM_SIZE (SZ_1G) -#endif - -/* SPI Flash */ - -#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K - -#if !defined(CONFIG_DM_PMIC) -#define CFG_POWER_PFUZE100_I2C_ADDR 0x08 -#define TQMA6_PFUZE100_I2C_BUS 2 -#endif - /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 -#if defined(CONFIG_TQMA6X_MMC_BOOT) - -#define TQMA6_UBOOT_OFFSET SZ_1K -#define TQMA6_UBOOT_SECTOR_START 0x2 -#define TQMA6_UBOOT_SECTOR_COUNT 0x7fe - -#define TQMA6_FDT_OFFSET (2 * SZ_1M) -#define TQMA6_FDT_SECTOR_START 0x1000 -#define TQMA6_FDT_SECTOR_COUNT 0x800 - -#define TQMA6_KERNEL_SECTOR_START 0x2000 -#define TQMA6_KERNEL_SECTOR_COUNT 0x2000 - -#define TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ - "uboot_start="__stringify(TQMA6_UBOOT_SECTOR_START)"\0" \ - "uboot_size="__stringify(TQMA6_UBOOT_SECTOR_COUNT)"\0" \ - "fdt_start="__stringify(TQMA6_FDT_SECTOR_START)"\0" \ - "fdt_size="__stringify(TQMA6_FDT_SECTOR_COUNT)"\0" \ - "kernel_start="__stringify(TQMA6_KERNEL_SECTOR_START)"\0" \ - "kernel_size="__stringify(TQMA6_KERNEL_SECTOR_COUNT)"\0" \ - "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ - "loadimage=mmc dev ${mmcdev}; " \ - "mmc read ${loadaddr} ${kernel_start} ${kernel_size};\0" \ - "loadfdt=mmc dev ${mmcdev}; " \ - "mmc read ${fdt_addr} ${fdt_start} ${fdt_size};\0" \ - "update_uboot=if tftp ${uboot}; then " \ - "if itest ${filesize} > 0; then " \ - "mmc dev ${mmcdev}; mmc rescan; " \ - "setexpr blkc ${filesize} + 0x1ff; " \ - "setexpr blkc ${blkc} / 0x200; " \ - "if itest ${blkc} <= ${uboot_size}; then " \ - "mmc write ${loadaddr} ${uboot_start} " \ - "${blkc}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize; setenv blkc \0" \ - "update_kernel=run kernel_name; " \ - "if tftp ${kernel}; then " \ - "if itest ${filesize} > 0; then " \ - "mmc dev ${mmcdev}; mmc rescan; " \ - "setexpr blkc ${filesize} + 0x1ff; " \ - "setexpr blkc ${blkc} / 0x200; " \ - "if itest ${blkc} <= ${kernel_size}; then " \ - "mmc write ${loadaddr} " \ - "${kernel_start} ${blkc}; " \ - "fi; " \ - "fi; " \ - "fi; " \ - "setenv filesize; setenv blkc \0" \ - "update_fdt=if tftp ${fdt_file}; then " \ - "if itest ${filesize} > 0; then " \ - "mmc dev ${mmcdev}; mmc rescan; " \ - "setexpr blkc ${filesize} + 0x1ff; " \ - "setexpr blkc ${blkc} / 0x200; " \ - "if itest ${blkc} <= ${fdt_size}; then " \ - "mmc write ${loadaddr} ${fdt_start} ${blkc}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize; setenv blkc \0" \ - -#elif defined(CONFIG_TQMA6X_SPI_BOOT) - -#define TQMA6_UBOOT_OFFSET 0x400 -#define TQMA6_UBOOT_SECTOR_START 0x0 -/* max u-boot size: 512k */ -#define TQMA6_UBOOT_SECTOR_SIZE TQMA6_SPI_FLASH_SECTOR_SIZE -#define TQMA6_UBOOT_SECTOR_COUNT 0x8 -#define TQMA6_UBOOT_SIZE (TQMA6_UBOOT_SECTOR_SIZE * \ - TQMA6_UBOOT_SECTOR_COUNT) - -#define TQMA6_FDT_OFFSET (CONFIG_ENV_OFFSET_REDUND + \ - CONFIG_ENV_SECT_SIZE) -#define TQMA6_FDT_SECT_SIZE (TQMA6_SPI_FLASH_SECTOR_SIZE) - -#define TQMA6_FDT_SECTOR_START 0x0a /* 8 Sector u-boot, 2 Sector env */ -#define TQMA6_FDT_SECTOR_COUNT 0x01 - -#define TQMA6_KERNEL_SECTOR_START 0x10 -#define TQMA6_KERNEL_SECTOR_COUNT 0x60 - -#define TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ - "mmcblkdev=0\0" \ - "uboot_offset="__stringify(TQMA6_UBOOT_OFFSET)"\0" \ - "uboot_sectors="__stringify(TQMA6_UBOOT_SECTOR_COUNT)"\0" \ - "fdt_start="__stringify(TQMA6_FDT_SECTOR_START)"\0" \ - "fdt_sectors="__stringify(TQMA6_FDT_SECTOR_COUNT)"\0" \ - "kernel_start="__stringify(TQMA6_KERNEL_SECTOR_START)"\0" \ - "kernel_sectors="__stringify(TQMA6_KERNEL_SECTOR_COUNT)"\0" \ - "update_uboot=if tftp ${uboot}; then " \ - "if itest ${filesize} > 0; then " \ - "setexpr blkc ${filesize} + " \ - __stringify(TQMA6_UBOOT_OFFSET) "; " \ - "setexpr size ${uboot_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "if itest ${blkc} <= ${size}; then " \ - "sf probe; " \ - "sf erase 0 ${size}; " \ - "sf write ${loadaddr} ${uboot_offset} " \ - "${filesize}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize 0; setenv blkc; setenv size \0" \ - "update_kernel=run kernel_name; if tftp ${kernel}; then " \ - "if itest ${filesize} > 0; then " \ - "setexpr size ${kernel_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "setexpr offset ${kernel_start} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "if itest ${filesize} <= ${size}; then " \ - "sf probe; " \ - "sf erase ${offset} ${size}; " \ - "sf write ${loadaddr} ${offset} " \ - "${filesize}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize 0; setenv size ; setenv offset\0" \ - "update_fdt=if tftp ${fdt_file}; then " \ - "if itest ${filesize} > 0; then " \ - "setexpr size ${fdt_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "setexpr offset ${fdt_start} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "if itest ${filesize} <= ${size}; then " \ - "sf probe; " \ - "sf erase ${offset} ${size}; " \ - "sf write ${loadaddr} ${offset} " \ - "${filesize}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize 0; setenv size ; setenv offset\0" \ - "loadimage=sf probe; " \ - "setexpr size ${kernel_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "setexpr offset ${kernel_start} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "sf read ${loadaddr} ${offset} ${size}; " \ - "setenv size ; setenv offset\0" \ - "loadfdt=sf probe; " \ - "setexpr size ${fdt_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "setexpr offset ${fdt_start} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "sf read ${fdt_addr} ${offset} ${size}; " \ - "setenv size ; setenv offset\0" -#else - -#error "need to define boot source" - -#endif - /* 128 MiB offset as in ARM related docu for linux suggested */ #define TQMA6_FDT_ADDRESS 0x18000000 -/* set to a resonable value, changeable by user */ -#define TQMA6_CMA_SIZE 160M +/* 256KiB above TQMA6_FDT_ADDRESS (TQMA6_FDT_ADDRESS + SZ_256K) */ +#define TQMA6_FDT_OVERLAY_ADDR 0x18040000 -#define CFG_EXTRA_ENV_SETTINGS \ - "board=tqma6\0" \ - "uimage=uImage\0" \ - "zimage=zImage\0" \ - "boot_type=bootz\0" \ - "kernel_name=if test \"${boot_type}\" != bootz; then " \ - "setenv kernel ${uimage}; " \ - "else setenv kernel ${zimage}; fi\0" \ - "uboot=u-boot.imx\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_addr="__stringify(TQMA6_FDT_ADDRESS)"\0" \ - "console=" CONSOLE_DEV "\0" \ - "cma_size="__stringify(TQMA6_CMA_SIZE)"\0" \ - "initrd_high=0xffffffff\0" \ - "rootfsmode=ro\0" \ - "addcma=setenv bootargs ${bootargs} cma=${cma_size}\0" \ - "addtty=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \ - "addfb=setenv bootargs ${bootargs} " \ - "imx-fbdev.legacyfb_depth=32 consoleblank=0\0" \ - "mmcpart=2\0" \ - "mmcblkdev=0\0" \ - "mmcargs=run addmmc addtty addfb addcma\0" \ - "addmmc=setenv bootargs ${bootargs} " \ - "root=/dev/mmcblk${mmcblkdev}p${mmcpart} ${rootfsmode} " \ - "rootwait\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "setenv bootargs; " \ - "run mmcargs; " \ - "run loadimage; " \ - "if run loadfdt; then " \ - "echo boot device tree kernel ...; " \ - "${boot_type} ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "${boot_type}; " \ - "fi;\0" \ - "setenv bootargs \0" \ - "netdev=eth0\0" \ - "rootpath=/srv/nfs/tqma6\0" \ - "ipmode=static\0" \ - "netargs=run addnfs addip addtty addfb addcma\0" \ - "addnfs=setenv bootargs ${bootargs} " \ - "root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath},v3,tcp;\0" \ - "addip_static=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ - "${hostname}:${netdev}:off\0" \ - "addip_dynamic=setenv bootargs ${bootargs} ip=dhcp\0" \ - "addip=if test \"${ipmode}\" != static; then " \ - "run addip_dynamic; else run addip_static; fi\0" \ - "set_getcmd=if test \"${ipmode}\" != static; then " \ - "setenv getcmd dhcp; setenv autoload yes; " \ - "else setenv getcmd tftp; setenv autoload no; fi\0" \ - "netboot=echo Booting from net ...; " \ - "run kernel_name; " \ - "run set_getcmd; " \ - "setenv bootargs; " \ - "run netargs; " \ - "if ${getcmd} ${kernel}; then " \ - "if ${getcmd} ${fdt_addr} ${fdt_file}; then " \ - "${boot_type} ${loadaddr} - ${fdt_addr}; " \ - "fi; " \ - "fi; " \ - "echo ... failed\0" \ - "panicboot=echo No boot device !!! reset\0" \ - TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ +/* 16MiB above TQMA6_FDT_ADDRESS (TQMA6_FDT_ADDRESS + SZ_16M) */ +#define TQMA6_INITRD_ADDRESS 0x19000000 /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR @@ -265,19 +31,11 @@ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* - * All the defines above are for the TQMa6 SoM - * - * Now include the baseboard specific configuration - */ -#ifdef CONFIG_MBA6 -#include "tqma6_mba6.h" -#elif CONFIG_WRU4 -#include "tqma6_wru4.h" -#else -#error "No baseboard for the TQMa6 defined!" -#endif +#define TQMA6_MMC_UBOOT_SECTOR_START 0x2 +#define TQMA6_MMC_UBOOT_SECTOR_COUNT 0x7fe -/* Support at least the sensor on TQMa6 SOM */ +#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K +#define TQMA6_SPI_UBOOT_START 0x400 +#define TQMA6_SPI_UBOOT_SIZE 0xc0000 -#endif /* __CONFIG_H */ +#endif /* __TQMA6_CONFIG_H */ diff --git a/include/configs/tqma6_mba6.h b/include/configs/tqma6_mba6.h index 9b9f4150951..c30aeae4f29 100644 --- a/include/configs/tqma6_mba6.h +++ b/include/configs/tqma6_mba6.h @@ -11,9 +11,8 @@ #ifndef __CONFIG_TQMA6_MBA6_H #define __CONFIG_TQMA6_MBA6_H -#define CFG_FEC_MXC_PHYADDR 0x03 +#include "tqma6.h" #define CFG_MXC_UART_BASE UART2_BASE -#define CONSOLE_DEV "ttymxc1" #endif /* __CONFIG_TQMA6_MBA6_H */ diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index 110bd895a8a..b35e471bd95 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_TQMA6_WRU4_H #define __CONFIG_TQMA6_WRU4_H +#include "tqma6.h" + /* Ethernet */ #define CFG_FEC_MXC_PHYADDR 0x01 diff --git a/include/env/tq/mmc.env b/include/env/tq/mmc.env new file mode 100644 index 00000000000..abf561f8467 --- /dev/null +++ b/include/env/tq/mmc.env @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * shared mmc environment for TQ boards + */ + +addmmc= + setenv bootargs "${bootargs}" + root=/dev/mmcblk"${mmcblkdev}"p"${mmcrootpart}" "${rootfsmode}" rootwait; + +get_blockcount= + setexpr blkc "${filesize}" + 0x1ff; + setexpr blkc "${blkc}" / 0x200; + +load_mmc= + mmc dev "${mmcdev}"; mmc rescan; + load mmc "${mmcdev}":"${mmcpart}" "${kernel_addr_r}" /boot/"${image}"; + load mmc "${mmcdev}":"${mmcpart}" "${fdt_addr_r}" /boot/"${fdtfile}"; + fdt address "${fdt_addr_r}"; + fdt resize 0x100000; + for overlay in "${fdt_overlays}"; do + load mmc "${mmcdev}":"${mmcpart}" "${fdtoverlay_addr_r}" + /boot/"${overlay}" && fdt apply "${fdtoverlay_addr_r}"; + done; + +mmcargs=run addtty addmmc + +mmcboot= + echo "Booting from mmc ..."; + setenv bootargs && run mmcargs && + if run load_mmc; then + run boot_os; + else + echo "ERROR: loading from mmc"; + fi; + +mmcpart=2 + +mmc_finish_update_uboot= + mmc write "${loadaddr}" "${update_start_blk}" "${blkc}"; + mmc dev "${mmcdev}" 0; + setenv update_part; + setenv update_start_blk; + setenv blkc; + +mmc_prepare_update_uboot= + echo "Write U-Boot to mmc "${mmcdev}" ..."; + mmc dev "${mmcdev}"; mmc rescan; + run get_blockcount; + setenv update_start_blk "${uboot_mmc_start}"; + setenv update_part 0; + +mmc_switch_part= + mmc partconf "${mmcdev}" update_part; + mmc dev "${mmcdev}" "${update_part}"; + +mmcrootpart=2 + +update_uboot_mmc= + run check_ipaddr; + if tftp "${uboot}"; then + run mmc_prepare_update_uboot; + if itest "${blkc}" >= "${uboot_mmc_size}"; then + echo "ERROR: size to large ..."; + exit; + fi; + if itest "${mmcdev}" == "${emmc_dev}"; then + run mmc_switch_part; + if itest "${update_part}" > 0 ; then + if env exists emmc_bootp_start; then + setenv update_start_blk "${emmc_bootp_start}"; + else + echo "ERROR: eMMC boot partition block unset"; + exit; + fi; + fi; + fi; + run mmc_finish_update_uboot; + fi; diff --git a/include/env/tq/nfs.env b/include/env/tq/nfs.env new file mode 100644 index 00000000000..53fcbd0d152 --- /dev/null +++ b/include/env/tq/nfs.env @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * shared nfs environment for TQ boards + */ + +addnfs= + setenv bootargs "${bootargs}" root=/dev/nfs rw + nfsroot="${serverip}":"${rootpath}",v3,tcp + +load_nfs= + nfs "${kernel_addr_r}" "${serverip}":"${rootpath}"/boot/"${image}"; + nfs "${fdt_addr_r}" "${serverip}":"${rootpath}"/boot/"${fdtfile}"; + fdt address "${fdt_addr_r}"; + fdt resize 0x100000; + for overlay in "${fdt_overlays}"; do + nfs "${fdtoverlay_addr_r}" + "${serverip}":"${rootpath}"/boot/"${overlay}" && + fdt apply "${fdtoverlay_addr_r}"; + done; + +load_tftp= + tftp "${kernel_addr_r}" "${image}"; + tftp "${fdt_addr_r}" "${fdtfile}"; + fdt address "${fdt_addr_r}"; + fdt resize 0x100000; + for overlay in "${fdt_overlays}"; do + if tftp "${fdtoverlay_addr_r}" "${overlay}"; then + fdt apply "${fdtoverlay_addr_r}"; + else + exit; + fi; + done; + +netargs=run addnfs addip addtty + +netloadcmd=load_tftp + +nfsboot= + echo "Booting from NFS ..."; + setenv bootargs; + run netargs; + run check_ipaddr; + if run ${netloadcmd}; then + run boot_os; + else + echo "ERROR: loading from NFS"; + fi; diff --git a/include/env/tq/spi.env b/include/env/tq/spi.env new file mode 100644 index 00000000000..47dcfea7d3f --- /dev/null +++ b/include/env/tq/spi.env @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * shared spi environment for TQ boards + */ + +update_uboot_spi= + run check_ipaddr; + if tftp ${uboot}; then + if itest "${filesize}" >= "${uboot_spi_size}"; then + echo "ERROR: size to large ..."; + exit; + fi; + echo "Write u-boot image to SPI NOR ..."; + if sf probe; then + run write_uboot_spi; + fi; + fi; + +write_uboot_spi=sf update "${loadaddr}" "${uboot_spi_start}" "${filesize}" diff --git a/include/env/tq/tq-imx-shared.env b/include/env/tq/tq-imx-shared.env new file mode 100644 index 00000000000..d4e42f8b536 --- /dev/null +++ b/include/env/tq/tq-imx-shared.env @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * shared environment for TQ imx boards + */ + +#ifdef CONFIG_CMD_SF +#include "spi.env" +#ifdef CONFIG_CMD_UBIFS +#include "ubi.env" +#endif /* CONFIG_CMD_UBIFS */ +#endif /* CONFIG_CMD_SF */ + +#ifdef CONFIG_CMD_MMC +#include "mmc.env" +#endif + +#ifdef CONFIG_CMD_NFS +#include "nfs.env" +#endif + +addip= + run check_ipaddr; + setenv bootargs "${bootargs}" + ip="${ipaddr}":"${serverip}":"${gatewayip}":"${netmask}":"${hostname}":"${netdev}":off + +addtty=setenv bootargs "${bootargs}" "${console}" + +check_ipaddr= + if test -z "${ipaddr}" || test -z "${serverip}"; then + echo "ipaddr or serverip unset, falling back to DHCP..."; + dhcp; + fi; + +rootfsmode=ro diff --git a/include/env/tq/ubi.env b/include/env/tq/ubi.env new file mode 100644 index 00000000000..01243d2eb53 --- /dev/null +++ b/include/env/tq/ubi.env @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH <[email protected]>, + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * shared ubi environment for TQ boards + */ + +addubi= + setenv bootargs "${bootargs}" rootfstype=ubifs ubi.mtd="${ubimtdname}" + root=ubi0:"${ubirootfsvol}" "${rootfsmode}" rootwait; + +load_spi= + if sf probe; then + if ubi part "${ubirootfspart}"; then + if ubifsmount ubi0:"${ubirootfsvol}"; then + ubifsload "${kernel_addr_r}" /boot/"${image}"; + ubifsload "${fdt_addr_r}" /boot/"${fdtfile}"; + fdt address "${fdt_addr_r}"; + fdt resize 0x100000; + for overlay in "${fdt_overlays}"; do + ubifsload "${fdtoverlay_addr_r}" + /boot/"${overlay}" && + fdt apply "${fdtoverlay_addr_r}"; + done; + ubifsumount; + fi; + ubi detach; + fi; + fi + +ubiargs=run addubi addtty + +ubiboot= + echo "Booting from UBI ..."; + setenv bootargs; + run ubiargs; + if run load_spi; then + run boot_os; + else + echo "ERROR: loading kernel"; + fi; + +ubimtdname=mtdname +ubirootfspart=ubi +ubirootfsvol=root |