| Age | Commit message (Collapse) | Author |
|---|
|
Update CHANEGLOG, fix minor coding style issue.
Signed-off-by: Wolfgang Denk <[email protected]>
|
|
|
|
|
|
|
|
|
|
The routine assumed 4 bank SDRAMs, enhance to configure for 4 or 8
bank SDRAMs.
Signed-off-by: Gerald Van Baren <[email protected]>
Acked-by: Dave Liu <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
|
|
This patch makes sure the correct mask is applied when setting
the encryption and I2C bus 0 clock in SCCR.
Failing to do so may lead to ENCCM being 0 in which case I2C bus 0
won't function.
Signed-off-by: Norbert van Bolhuis <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
|
|
Read and store OMAP3 die ID in U-Boot environment.
Signed-off-by: Dirk Behme <[email protected]>
|
|
Set a non-zero speed in the MII register so that MII commands will work.
Signed-off-by: Jon Smirl <[email protected]>
|
|
Signed-off-by: Yusuke Goda <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
|
|
The rtl8139 driver use pci_mem_to_phys. So it need PCI system memory
registration.
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
|
|
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
|
|
We can built 'make sh7785lcr_32bit_config'. And add new command "pmb"
for this mode. This command changes PMB for using 512MB system memory.
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
|
|
Some register value was hardcoded for System memory size 128MB and
memory offset 0x08000000. This patch fixed the problem.
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
|
|
It is necessary for some pci device driver.
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
|
|
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
|
|
Signed-off-by: Yoshihiro Shimoda <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
|
|
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
|
|
|
|
|
|
Commit af1c2b84 added a generic phy support, with an ID of zero
and a 32 bit mask; meaning that it will match on any PHY ID.
The problem is that there is a test that checked if a matching
PHY was found, and if not, it printed the non-matching ID.
But since there will always be a match (on the generic PHY,
worst case), this test will never trip.
In the case of a misconfigured PHY address, or of a PHY that
isn't explicitly supported outside of the generic support,
you will never see the ID of 0xffffffff, or the ID of the
real (but unsupported) chip. It will silently fall through
onto the generic support.
This change makes that test useful again, and ensures that
the selection of generic PHY support doesn't happen without
some sort of notice. It also makes it explicitly clear that
the generic PHY must be last in the PHY table.
Signed-off-by: Paul Gortmaker <[email protected]>
Acked-by: Andy Fleming <[email protected]>
|
|
Fix typo in makefile which broke out of tree builds.
Also use expolicit "rm" instead of "ln -sf" which is known to be
unreliable.
Signed-off-by: Wolfgang Denk <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
|
|
This adds tsec12ioovcr to include/asm-ppc/immap_85xx.h (was reserved.)
Signed-off-by: Sergey Kubushyn <[email protected]>
|
|
These were left in accidentally, and are not really useful unless the
code is as broken as it was when it was being developed.
Signed-off-by: Andy Fleming <[email protected]>
|
|
Commit e1be0d25, "32bit BUg fix for DDR2 on 8572" prevented other
sdram_cfg bits (such as ecc and self_refresh_in_sleep) from being set.
Signed-off-by: Ed Swarthout <[email protected]>
|
|
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
|
|
Fix typo in makefile which broke out of tree builds.
Also use expolicit "rm" instead of "ln -sf" which is known to be
unreliable.
Signed-off-by: Wolfgang Denk <[email protected]>
|
|
Conflicts:
lib_ppc/board.c
Signed-off-by: Wolfgang Denk <[email protected]>
|
|
add CONFIG_BOOTCOUNT_LIMIT feature for 8360 CPU.
The bootcounter uses 8 bytes from the muram,
because no other memory was found on this
CPU for the bootcount feature. So we must
correct the muram size in DTS before booting
Linux.
This feature is actual only implemented for
MPC8360, because not all 83xx CPU have qe,
and therefore no muram, which this feature
uses.
Signed-off-by: Heiko Schocher <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
|
|
old code implemented the QE_ENET10 errata only for Silicon
Revision 2.0. New code reads now the Silicon Revision
register and sets dependend on the Silicon Revision the
values as advised in the QE_ENET10 errata.
Signed-off-by: Heiko Schocher <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
|
|
- HRCW update
HRCWH_BOOTSEQ_DISABLE not HRCWH_BOOTSEQ_NORMAL
HRCWH_LALE_EARLY added
- DDR-SDRAM settings modified. This solves sporadically
problems with this memory.
- CS1 now 128 MB window size
- CS3 now 512 MB window size
- PRAM activated
- MTDPARTS_DEFAULT defined
- CONFIG_HOSTNAME added
- MONITOR_LEN now 384 KB
Signed-off-by: Heiko Schocher <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
|
|
it is possible that some board variants have different DDR II
RAM sizes. So we autodetect the size of the assembled RAM.
Signed-off-by: Heiko Schocher <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
|
|
This patch adds I2C mux support for the fsl_i2c driver. This
allows you to add "new" i2c busses, which are reached over
i2c muxes. For more infos, please look in the README and
search for CONFIG_I2C_MUX.
Signed-off-by: Heiko Schocher <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
|
|
This patch adds I2C support for the Keymile kmeter1 board.
It uses the First I2C Controller from the CPU, for
accessing 4 temperature sensors, an eeprom with IVM data
and the booteeprom over a pca9547 mux.
Signed-off-by: Heiko Schocher <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
|
|
In case where a board not uses CONFIG_POST, it is not
necessary to init the DTTs when running from flash.
Signed-off-by: Heiko Schocher <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
|
|
1. RD_TO_PRE missed to add the AL, and need min 2 clocks for
tRTP according to DDR2 JEDEC spec.
2. WRTORD - tWTR need min 2 clocks according to DDR2 JEDEC spec.
3. add the support of DDR2-533,667,800 DIMMs
4. cpo
5. make the AL to min to gain better performance.
The Micron MT9HTF6472CHY-667D1 DIMMs test passed on
MPC837xEMDS platform at 266MHz/333MHz/400MHz data rate.
items 1, 2 and 5:
Acked-by: Joakim Tjernlund <[email protected]>
Reported-by: Joakim Tjernlund <[email protected]>
Signed-off-by: Dave Liu <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
|
|
The previous version rebooted forever with DDR bigger than 256MB.
Access the DS1339 RTC chip is on I2C1 bus.
Allow DHCP.
Signed-off-by: Valeriy Glushkov <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
|
|
The SerDes initialization should be finished before negating the reset
signal according to the reference manual. This isn't an issue on real
hardware, but we'd better stick to the specifications anyway.
Suggested-by: Liu Dave <[email protected]>
Signed-off-by: Anton Vorontsov <[email protected]>
Signed-off-by: Kim Phillips <[email protected]>
|
|
it is not necessary to init the DTTs so early,
so move this init to board_init_r ().
Signed-off-by: Heiko Schocher <[email protected]>
|
|
Fix following warning while compilation for mcc200 board:
lcd.c: In function 'lcd_display_bitmap':
lcd.c:625: warning: unused variable 'cmap'
Signed-off-by: Anatolij Gustschin <[email protected]>
|
|
Fixes commit 407976185e0dda2c90e89027121a1071b9c77bfb
Signed-off-by: Graeme Russ <graeme.russ at gmail.com>
|
|
The smc911x driver has a lot of useful defines/functions which can be used
by pieces of code (such as example eeprom programmers). Rather than
forcing each place to duplicate these defines/functions, split them out
of the smdc911x driver into a local header.
Signed-off-by: Mike Frysinger <[email protected]>
Acked-by: Ben Warren <[email protected]>
CC: Sascha Hauer <[email protected]>
CC: Guennadi Liakhovetski <[email protected]>
CC: Magnus Lilja <[email protected]>
CC: Ben Warren <[email protected]>
|
|
|
|
|
|
The "eet" variant of the imx31_phycore board has an OLED display, using a
s6e63d6 display controller on the first SPI interface, using GPIO57 as a
chip-select for it. With this configuration you can display 256 colour BMP
images in 16-bit RGB (RGB565) LCD mode.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
|
|
Add a driver for the Synchronous Display Controller and the Display
Interface on i.MX31, using IPU for DMA channel setup. So far only
displaying of bitmaps is supported, no text output.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
Acked-by: Anatolij Gustschin <[email protected]>
|
|
This patch also simplifies some ifdefs in lcd.c, introduces a generic
vidinfo_t, which new drivers are encouraged to use and old drivers to switch
over to.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
Acked-by: Anatolij Gustschin <[email protected]>
|
|
This patch adds 16bpp BMP support to the common lcd code.
Use CONFIG_BMP_16BPP and set LCD_BPP to LCD_COLOR16 to enable the code.
At the moment it's only been tested on the MIMC200 AVR32 board, but extending
this to other platforms should be a simple task !!
Signed-off-by: Mark Jackson <[email protected]>
Signed-off-by: Guennadi Liakhovetski <[email protected]>
Acked-by: Anatolij Gustschin <[email protected]>
|
|
This is a driver for the S6E63D6 SPI OLED display controller from Samsung.
It only provides access to controller's registers so the client can freely
configure it.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
Acked-by: Anatolij Gustschin <[email protected]>
|
|
Some SPI devices have special requirements on chip-select handling.
With this patch we can use a GPIO as a chip-select and strictly follow
the SPI_XFER_BEGIN and SPI_XFER_END flags.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
|
