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Fix spelling errors in comments.
Reviewed-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
Signed-off-by: Igor Opaniuk <[email protected]>
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We should not use the reserved value 0x00 for the wake up type but
use 0x02 (Unknown).
Signed-off-by: Heinrich Schuchardt <[email protected]>
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Correct type 1 output
* render wake up time as string
* print family string
* remove duplicate serial number output
Signed-off-by: Heinrich Schuchardt <[email protected]>
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acpi_fill_header() is declared twice in include/acpi/acpi_table.h
Signed-off-by: Heinrich Schuchardt <[email protected]>
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Document struct acpi_gen_regaddr and struct acpi_hpet.
Sphinx requires that the __packed attribute is at the end of the structure
definitions.
Signed-off-by: Heinrich Schuchardt <[email protected]>
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Add include/acpi/ to the realm of the ACPI maintainer.
Signed-off-by: Heinrich Schuchardt <[email protected]>
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The fields Creator ID and Creator Revision contain information about the
tool that created an ACPI table. This may be the ASL compiler for some
tables but it is not for others. Naming these fields aslc_id and
aslc_revision is misleading.
It is usual to see diverse values of Creator ID. On a laptop I saw these:
'AMD ', 'INTL, 'MSFT', 'PTEC'. Obviously not all relate to the Intel
ASL compiler.
Signed-off-by: Heinrich Schuchardt <[email protected]>
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Reset GPIO handling is done in ETH PHY Class driver.
Enable DM_ETH_PHY.
We don't use Fixed PHY so disable PHY_FIXED.
Signed-off-by: Roger Quadros <[email protected]>
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If DM_ETH_PHY is enabled then try to bind and probe the
generic Ethernet PHY driver for each child of MDIO bus.
This is to ensure that GPIO reset handling is done if available
before MDIO bus driver scans for the PHYs.
Signed-off-by: Roger Quadros <[email protected]>
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Pull the PHY GPIO reset code into separate function, since
this is and will be reused multiple times. Set up default
reset assert and deassert timing to generous 20ms and 1ms
for maximum compatibility in case those DT properties are
missing.
Reviewed-by: Ramon Fried <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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This patch adds support for i225-IT in e1000 driver.
Add e1000_phy_igc.
Signed-off-by: Marjolaine Amate <[email protected]>
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From the ethernet header is not on aligned, because the length
of the ethernet header is 14 bytes.
Therefore, unaligned access must be done here.
Signed-off-by: Jacky Chou <[email protected]>
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There is no need to perform the endian twice here.
Signed-off-by: Jacky Chou <[email protected]>
Reviewed-by: Dan Carpenter <[email protected]>
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They are not required to be global, make them static.
Signed-off-by: Yang Xiwen <[email protected]>
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3 operations needed by `net stats` are implemented. New `net stats`
output some useful info.
Signed-off-by: Yang Xiwen <[email protected]>
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register internal MDIO bus device if it is a subnode.
Signed-off-by: Yang Xiwen <[email protected]>
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shrink the first argument of log_msg_ret(), add dev_xxx() functions for
error reporting.
Fixes: 9d8f78a2a79f7 ("net: add hifemac Ethernet driver for HiSilicon platform")
Signed-off-by: Yang Xiwen <[email protected]>
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The initial commit used log_msg_ret() wrongly. Fix that by moving error
report to a separate dev_err() call and shrink the first argument of
log_msg_ret() to no more than 4 chars.
Fixes: 6b5c8d98e204 ("net: add hifemac_mdio MDIO bus driver for HiSilicon platform")
Signed-off-by: Yang Xiwen <[email protected]>
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As with fixed-link phy device, the NC-SI phy devive does not
require an mdio bus. So, a condition is added to check the
NC-SI phy id to avoid accessing the bus pointer that is NULL.
Signed-off-by: Jacky Chou <[email protected]>
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Booting R-Car Gen3 arm64 U-Boot with CONFIG_UBSAN=y resulted in:
=====================================================================
UBSAN: Undefined behaviour in drivers/net/phy/phy.c:728:19
left shift of 1 by 31 places cannot be represented in type 'int'
=====================================================================
Fix it by appending the UL suffix to the numeric literal. While at it,
convert the type of "addr" variable from signed to unsigned, to protect
against shifting the numeric literal by a negative value (which would
lead to yet another undefined behavior).
Fixes: 1adb406b0141 ("phy: add phy_find_by_mask/phy_connect_dev")
Signed-off-by: Eugeniu Rosca <[email protected]>
* Using U-suffix for integer is sufficient.
* ffs() of non-zero value cannot be 0. But addr being unsigned is
* preferable.
Signed-off-by: Heinrich Schuchardt <[email protected]>
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Configure LEDs on BCM54210E so they would blink on activity
and indicate link speed. Without this the LEDs are always on
if cable is plugged in.
Signed-off-by: Marek Vasut <[email protected]>
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The issue occurs the UAF (use-after-free) to cause double free
when do the realloc function for the pointers during the
reinitialization NC-SI process, and it will cause the memory
management occurs error.
So, nullify these pointers after free.
Signed-off-by: Jacky Chou <[email protected]>
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- Fix RISC-V falcon mode booting issue
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CMU_CORE generates clocks needed for eMMC enablement, and CMU_HSI
provides clocks for SD card and USB. Most of the code is copied from the
Linux kernel counterpart driver.
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Samsung clock drivers usually define the clock indices that are unique
per one CMU, but are not unique across all CMUs. That is, clock indices
start from 1 for each CMU, as provided in CMU bindings header. The way
the clock lookup via clk_get_by_index() works at the moment is by using
clk_of_xlate_default(), which returns globally non-unique clock ids for
for clocks registered with Samsung CCF API, which leads to incorrect
clocks being obtained. One way to fix that would be to make all clock
ids defined in the bindings header unique, but it'd make it incompatible
with Linux kernel bindings header. A better way to solve this issue is
to calculate the global clock id and use it when registering a clock
with clk_dm() and when obtaining it, in a custom .of_xlate function.
This patch adds an API for such mapping calculation, introducing the
necessary modifications to CMU registering functions in Samsung CCF.
Exynos850 clock driver (the only driver that uses Samsung CCF at the
moment) is modified accordingly, as it uses the changed API. So the
clock lookup with clk-exynos850.c driver is also fixed here.
The global clock id is calculated from CMU id and local clock id in
SAMSUNG_TO_CLK_ID() macro like this:
clk_id_global = cmu_id * 256 + clk_id_local
leaving a range of up to 256 clocks for each CMU. Then this mapping
macro is used in clk_dm() to register clocks using their global ids, and
in .of_xlate() to lookup the clock by its local id correctly. Because
.of_xlate() operation has a separate function for each CMU, it "knows"
the correct way of finding the correct clk_id_global by provided
clk_id_local.
Fixes: ff3e8b8c6c22 ("clk: exynos: Add Samsung clock framework")
Fixes: a36cc5e3ef4d ("clk: exynos: Add Exynos850 clock driver")
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Samsung CCF is meant to be used from the clock drivers by calling the
CMU registration API, i.e.:
- samsung_cmu_register_one() -- for top-level CMU
- samsung_register_cmu() -- for the rest of CMUs
Functions for registering separate clocks is probably not going to be
very useful, and isn't used at the moment. Remove prototypes of those
functions to make the Samsung CCF interface more compact and clear.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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Group CMU_TOP clocks to make it easier to add the support for more CMUs.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
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When Falcon Mode is enabled on RISC-V, use CONFIG_VAL
to check PAYLOAD_ARGS_ADDR, not CONFIG_IS_ENABLED.
Fixes: 10c4ab898c25 ("spl: riscv: falcon: move fdt blob to specified address")
Signed-off-by: Randolph <[email protected]>
Tested-by: Leo Yu-Chi Liang <[email protected]>
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Prepare v2024.04-rc5
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Signed-off-by: Tom Rini <[email protected]>
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Add a device tree node to describe the DisplayPort connector, and
connect it to the DPSUB output.
The patch was tested on kv260-revB/rev2 and also kr260-revB.
Signed-off-by: Vishal Sagar <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/c8738cb9951c73c6c00a4ce8d0025fb372372346.1711036494.git.michal.simek@amd.com
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Add "rts-gpios" and "linux,rs485-enabled-at-boot-time" properties
to uartps node to support RS485 on KD240.
Signed-off-by: Manikanta Guntupalli <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/56e4e135ad796afd1370c3dfa2643c143ba758ee.1710847646.git.michal.simek@amd.com
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Since the zynqmp pinctrl driver now includes support for the
tri-state registers, ensure that the pins needing output-enable
are correctly configured for SOMs.
Currently, there is an issue with the detection of the MMC for
the SOM kv260, resulting in the following error:
ZynqMP> mmc dev 1
Card did not respond to voltage select! : -110
To address this problem, configure the SDIO pins for output-enable
to enable MMC detection.
Signed-off-by: Tejas Bhumkar <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Add "bootcmd_usb4" variable to boot through usb4 device.
Signed-off-by: Shubhangi Shrikrushna Mahalle <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/cb36fe6bd1fef540441e1d8c32636ae6f80357b4.1710933852.git.michal.simek@amd.com
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if (reg >> BOOT_MODE_ALT_SHIFT) condition rules out alternative jtag boot
mode which is 0. When 0 was used origin(HW) boot mode was used instead.
That's why directly fill reg variable with requested boot mode and don't
let code to read value back. "else" part of code remain unchanged.
Reviewed-by: Sean Anderson <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/ed51a9d51948ab939a53e0b9dc6c2d2546f97a4f.1710933505.git.michal.simek@amd.com
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https://source.denx.de/u-boot/custodians/u-boot-at91 into next
First set of u-boot-at91 features for the 2024.07 cycle:
- This feature set includes a new board named sama7g54 Curiosity.
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https://source.denx.de/u-boot/custodians/u-boot-amlogic
- fix Ethernet and random MAC's on WeTek Hub/Play2
- fix buffer overflow in serial, mac & usid read
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While meson_sm_read_efuse() doesn't overflow, the string is not
zero terminated and env_set*() will buffer overflow and add random
characters to environment.
Acked-by: Viacheslav Bocharov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
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Add a fall-back method to generate ethaddr from CPU serial on p200 boards
if the MAC cannot be read from efuse. This prevents random MAC addresses
on the WeTek Hub/Play2 boards.
Signed-off-by: Christian Hewitt <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
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Placing the snps,reset content needed for Ethernet to probe in a common
uboot.dtsi results in the content not being used and broken Ethernet. Fix
this by creating two board specific dtsi files with the right content.
Fixes: 67d5128df950 ("ARM: dts: add support for WeTek Hub and WeTek Play2")
Signed-off-by: Christian Hewitt <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Neil Armstrong <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
- Add ahab_commit command support.
- Add USB support for the imx93-phyboard-segin board.
- Add i.MX8MP PCIe support.
- Fix netboot environment on phycore_imx8mp.
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The "run netargs" command should come later in the "netboot" command
order when using dhcp since it sets the server and client ip addresses.
The previous order led to misconfigured kernel boot params and thus
kernel panic when serverip was not manually set.
Further, following Linux FHS 3.0, change the nfsroot default directory
to /srv/nfs.
Fixes: 60f64bec414e ("board: phytec: phycore_imx8mp: Add fec support")
Signed-off-by: Yannic Moog <[email protected]>
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Enable the `fastboot` command.
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Mathieu Othacehe <[email protected]>
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Add USB support by enabling `usb` command and required USB drivers.
Signed-off-by: Mathieu Othacehe <[email protected]>
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Enable both usbotg1 and usbotg2 ports. Disable over-current as OC pins are
not connected to the SoC.
This addition to imx93-phyboard-segin-u-boot.dtsi is temporary,
until USB support is added to imx93-phyboard-segin.dts in Linux.
Signed-off-by: Mathieu Othacehe <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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This message is used to commit into the fuses any new SRK revocation and
FW version information that have been found into the NXP (ELE FW) and
OEM containers.
Signed-off-by: Mathieu Othacehe <[email protected]>
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Add myself as maintainer for PCIe DWC IMX driver support.
Acked-by: Marek Vasut <[email protected]>
Signed-off-by: Sumit Garg <[email protected]>
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Enable PCIe/NVMe support. Also, enable the reset, regmap and syscon
drivers which are a prerequisite for PCIe support.
Signed-off-by: Tim Harvey <[email protected]>
[SG: rebased to next branch tip]
Signed-off-by: Sumit Garg <[email protected]>
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Enable PCIe/NVMe support. Also, enable the reset driver which
is a prerequisite for PCIe support.
Acked-by: Francesco Dolcini <[email protected]>
Tested-by: Marcel Ziswiler <[email protected]>
Signed-off-by: Sumit Garg <[email protected]>
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Since now we have the modern pcie_dw_imx.c driver for iMX SoCs,
encourage people to switch to that for any further new iMX SoC support
or even for the older iMX6 SoCs too.
Suggested-by: Peter Robinson <[email protected]>
Signed-off-by: Sumit Garg <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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