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Rework the section about includes slightly. We should not be using
common.h anywhere, so remove that from examples and ask people to send
patches removing it when found. Doing this also means we need to reword
other parts of this section. Be clearer about using alphabetical
ordering.
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Igor Opaniuk <[email protected]>
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Clarify usage of buffer argument.
Signed-off-by: Janne Grunau <[email protected]>
Reviewed-by: Heinrich Schuchardt <[email protected]>
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The error message
Adding disk for usb_mass_storage.lun0 failed (err=-9223372036854775788/0x8000000000000014)
provides a decimal and a hexadecimal notation of the EFI status code
EFI_ALREADY_STARTED which is defined as (EFI_ERROR_MASK | 20).
The decimal output does not convey the value 20 clearly.
With the patch we write
Adding block device usb_mass_storage.lun0 failed, r = 20
similar to other EFI error messages.
Fixes: 952018117ab4 ("dm: sandbox: Switch over to using the new host uclass")
Signed-off-by: Heinrich Schuchardt <[email protected]>
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The rendering of the OpenSBI logo should look like the screen output.
Signed-off-by: Heinrich Schuchardt <[email protected]>
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Add documentation for imxrt1170-evk.
Signed-off-by: Jesse Taube <[email protected]>
Reviewed-by: Giulio Benetti <[email protected]>
Add index page entry, adjust formatting.
Signed-off-by: Heinrich Schuchardt <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI:
https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/19583
- Fix the i.MX8MP SPI compatible string.
- Let the SPL clock code do the configuration on Data Modul i.MX8M Plus
eDM SBC.
- Enable secure boot on the imx93_var_som board.
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Add missing prototype to fix the below sparse warning
warning: no previous prototype for 'spl_spi_get_uboot_offs'
[-Wmissing-prototypes]
Fixes: 2c8a09219cdb ("arm64: zynqmp: Add multiboot support for SPL/SPI offset calculation")
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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When SOM dt is combined with kd240 overlay DPSUB is enabled but kd240 has
no DP wired that's why change disable it via status property.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/f6de217b3350c9d59032ef54800882e48f240398.1706791116.git.michal.simek@amd.com
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usb0 is already updated but forget to also update usb1.
Fixes: 4ff083f09bc2 ("arm64: zynqmp: Do not expose usbhub nodes")
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/862ca748670f18f25d88aa5b43c37e3dd6aa35eb.1706791116.git.michal.simek@amd.com
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Node name has to be renamed to be aligned with dt-schema and also
xlnx,zynqmp-nvmem-fw switched to fixed-layout.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/32899b20c1e282aab16c32074b1c9a3f45f6dac8.1706791116.git.michal.simek@amd.com
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There is no dt schema associated with it. Also Linux driver have been
removed in Xilinx Linux tree and never gets to upstream that's why remove
description for it.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/6685ee980d9b475f95eef6b2a74795adc4ac4619.1706791116.git.michal.simek@amd.com
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fpga-full is not aligned with the latest dt-schema. Generic name
fpga-region should be used.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/78e6e3f287f79917eb92c6c74accbaf955526aad.1706791116.git.michal.simek@amd.com
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kr260 revA/revA01 is using discrete oscilator for DP (27MHz) and si5332 for
other clocks but clocks are different compare to kv260 that's why fix it to
aligned with the latest schematics.
On the other handle kr260 revB/revA03 also contains 74.25 MHz discrete
clock chip for SLVC-EC output which is not defined.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/e87ae94979c6efc909740bb1a569505042e4f876.1706626255.git.michal.simek@amd.com
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Describe 25Mhz fixed oscilator which is providing clock for PL based
ethernet IPs. Physicially it is one chip but it is described as 2 fixed
clock to be aligned with other SOM versions which were using integrated
clock generators where clocks could be adjusted via i2c (si5332 chips).
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/c430aeacaa76d9f61ed3f874f721a33049f45eb9.1706514396.git.michal.simek@amd.com
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Board description describes the hard part of chip (PS) but programmable
logic (PL) part is not described in this file. But clocks on the board are
not only connected to PS but also wired to PL. And because two revisions
are available where revA is using one si5332 and revB multiple clock chips
using the same clock labels helping with keeping only one device tree
overlay which targets PL. That's why synchronize clock labels and use
labels from revB which are more generic.
Unfortunately if there is driver for si5332 chip split could happen again
but it is still worth to do it now and solve this issue when occurs.
Reported-by: Sagar Karmarkar <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/abac6069e6029ed4076ec7b9d6b33604b6072aa3.1706253871.git.michal.simek@amd.com
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Without 'silabs,skip-recall' property, the driver on System Controller
re-calibrates the output clock frequency at probe() time based on the NVRAM
setting. This re-calibration causes a glitch on the output clock. At
power-on, Versal is also booting and expecting a glitch-free clock for
its correct operation. System Controller should skip the re-calibration
step to prevent any clock instability for Versal.
Signed-off-by: Saeed Nowshadi <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/bbb2322c94503f0e6b369c60312b7546500fad95.1706170068.git.michal.simek@amd.com
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Enable EFI_HTTP_BOOT to be able to booting OS via http.
In case of that dhcp server is not providing dns server IP set it up via
setenv dnsip <ip addr>.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/b78a7d8b0100c724f657c0997b273e073cf31a14.1706093917.git.michal.simek@amd.com
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Adding a tiny bit more code for mini u-boot leads to a OCM
image overflow. Fix this by enabling LTO for this board, so that such
changes still can be made to the common U-Boot code.
Enable building mini u-boot image with LTO, which results in about 8KB
reduction in size.
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Adding a tiny bit more code for mini u-boot leads to a OCM
image overflow. Fix this by enabling LTO for this board, so that such
changes still can be made to the common U-Boot code.
Enable building mini u-boot image with LTO, which results in about 8KB
reduction in size.
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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ID code is added for zu67dr_SE, zu11eg_SE, zu19eg_SE and zu47dr_SE
variants. SE is the select edition of restricted devices with the
capabilities.
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-sh
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Enable AHAB support in the imx93_var_som configuration.
Signed-off-by: Mathieu Othacehe <[email protected]>
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Probing the MU is needed to prevent this error in the SPL:
ele dev is not initialized
Authenticate container hdr failed, return -19, resp 0x0
IND = INVALID
ele dev is not initialized
Error: release container failed, resp 0x0!
IND = INVALID
SPL: failed to boot from all boot devices
Signed-off-by: Mathieu Othacehe <[email protected]>
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Put imx9_probe_mu declaration in a new mu.h header file.
Signed-off-by: Mathieu Othacehe <[email protected]>
Reviewed-by: Igor Opaniuk <[email protected]>
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Recent i.MX8MP DTs use new fsl,imx6ul-ecspi compatible string instead
of the fsl,imx51-ecspi compatible string. Add the new compatible string
to fix ECSPI operation on i.MX8MP.
For details, see Linux:
48d74376fb68 ("arm64: dts: imx8mp: update ecspi compatible and clk")
8eb1252bbedf ("spi: imx: remove ERR009165 workaround on i.mx6ul")
Fixes: 451799a6ceac ("arm: dts: imx8mp: Sync the DT with kernel 6.4-rc4")
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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The SPL clock code does configure the ECSPI clock frequency, which has
to match the mxc-spi driver configuration for successful SPI NOR boot.
Drop the assigned-clock from DT ecspi1 node on this board to let the
SPL clock code do the configuration and keep it aligned with the driver
expectation.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Add board code for the Renesas R8A779H0 V4M Gray Hawk board.
Signed-off-by: Hai Pham <[email protected]>
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Initial support for the Renesas Gray Hawk CPU and BreakOut boards.
The arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi is extended version of:
https://lore.kernel.org/linux-renesas-soc/b657402113267acd57aece0b4c681b707e704455.1706194617.git.geert+renesas@glider.be/
The version currenty submitted upstream lacks functionality which is
present in this series. Once the upstream support implements that
missing functionality, these DTs will be updated to match.
Signed-off-by: Hai Pham <[email protected]>
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Add Renesas R8A779H0 V4M DT extras for U-Boot.
Until the RPC node becomes part of main DT, keep it here as
an extension so that board code can enable and use the RPC
to access SPI NOR.
Signed-off-by: Hai Pham <[email protected]>
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Add initial support for the Renesas R8A779H0 (R-Car V4M) SoC.
The current version is imported and modified from:
https://lore.kernel.org/linux-renesas-soc/4107bc3d7c31932da29e671ddf4b1564ba38a84c.1706194617.git.geert+renesas@glider.be/
The modifications contain nodes from previous version
which are useful in U-Boot and not part of the Linux
kernel DT yet. The following nodes were added:
- pfc
- gpio0..gpio7
- i2c0..i2c3
- avb0..avb2
- mmc0
Signed-off-by: Hai Pham <[email protected]>
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Support RPC SPI on R8A779H0 V4M SoC.
Reviewed-by: Paul Barker <[email protected]>
Signed-off-by: Hai Pham <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Add Kconfig entry and PRR ID to support R8A779H0 V4M SoC.
Reviewed-by: Paul Barker <[email protected]>
Signed-off-by: Hai Pham <[email protected]>
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Add pinctrl tables for R8A779H0 V4M SoC.
The current version of these PFC tables is imported and squashed from:
https://lore.kernel.org/linux-renesas-soc/[email protected]/
Signed-off-by: Hai Pham <[email protected]>
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Add PLL7 support to Gen3/Gen4 common clock driver. Add initial PLL7
multiplier and divider values into table in R8A779H0 V4M clock driver.
The PLL7 is new PLL added in R8A779H0 V4M SoC. Only integer multiplication
mode is supported by PLL7. The PLL reference clock are either 16.66 MHz or
20 MHz on R8A779H0 V4M SoC, and the output frequency must be 2000 MHz. The
multiplier values fitting this requirement are calculated to 120 or 100.
Signed-off-by: Marek Vasut <[email protected]>
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Add clock tables for R8A779H0 V4M SoC.
The current version is imported from:
https://lore.kernel.org/linux-renesas-soc/c678ef7164e3777fa91572f72e47ef385cea64b8.1706194617.git.geert+renesas@glider.be/
The current version still contains PLL7 extras from the
previous version to provide ethernet support in U-Boot.
Signed-off-by: Hai Pham <[email protected]>
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Add power domain indices for R-Car V4M (R8A779H0).
The current version is imported from:
https://lore.kernel.org/linux-renesas-soc/c5cbef71178cada761e9da7bcbb6f21334f93ef8.1706194617.git.geert+renesas@glider.be/
Signed-off-by: Duy Nguyen <[email protected]>
Signed-off-by: Hai Pham <[email protected]>
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Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
V4M (R8A779H0) SoC.
The current version is imported from:
https://lore.kernel.org/linux-renesas-soc/11acbd2a30b58607474e9c32eb798b3a00e85e73.1706194617.git.geert+renesas@glider.be/
Signed-off-by: Duy Nguyen <[email protected]>
Signed-off-by: Hai Pham <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-dfu
u-boot-dfu-20240209
- sparse error checking fix when using raw chunks
- 2 new additions (AVB, AB) of myself to the MAINTAINERS file
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The return value of write_sparse_chunk_raw is unsigned, so the existing
check has no effect. Use IS_ERR_VALUE to detect error instead, which is
what write_sparse_chunk_raw does itself.
Fixes: 62649165cb0 ("lib: sparse: Make CHUNK_TYPE_RAW buffer aligned")
Reported-by: Dan Carpenter <[email protected]>
Link: https://lore.kernel.org/u-boot/[email protected]/
Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mattijs Korpershoek <[email protected]>
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Igor has not been active for quite some time on lore:
https://lore.kernel.org/all/[email protected]
I'm interested in helping with maintaining the android_avb
command. I'm a long time android/aosp developer and my daily job is
still doing android work.
Add myself as maintainer for Android AVB.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Igor Opaniuk <[email protected]>
Acked-by: Igor Opaniuk <[email protected]>
Reviewed-by: Sam Protsenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mattijs Korpershoek <[email protected]>
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Igor has not been active for quite some time on lore:
https://lore.kernel.org/all/[email protected]
I'm interested in helping with maintaining the android_ab
command. I'm a long time android/aosp developer and my daily job is
still doing android work.
Add myself as maintainer for Android AB.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sam Protsenko <[email protected]>
Acked-by: Igor Opaniuk <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mattijs Korpershoek <[email protected]>
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These select/imply settings are common to the whole architecture not just
these boards, move these settings to the architecture config.
Signed-off-by: Andrew Davis <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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TI KS2 boards have the nfs command in their common environment boot
configuration, enable this command.
Signed-off-by: Andrew Davis <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
- Add USB support for phycore-imx8mp
- Fix environment corruption, reset on mx6sabresd
- Print reset cause on imx8
- Extend mkimage to support generating an image for i.MXRT FlexSPI
- Add new apalis and colibri variants
- Add support for phyBOARD-Segin-i.MX93 support
- Fix when FEC is primarily used instead of EQOS on i.MX93.
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https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq
Add TJA1120 driver support
fsl-layerscape/soc.c: do not destroy bootcmd environment
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add support for Serial Downloader Boot via UUU as well as flashing emmc
via UUU on USB0 Port of phyBOARD Pollux.
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Benjamin Hahn <[email protected]>
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add support for USB mass storage to USB0 port of phyBOARD Pollux.
tested with "ums 0 mmc 2"
Signed-off-by: Benjamin Hahn <[email protected]>
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The phyBOARD Pollux has two USB ports. Add support for USB host and USB
storage for the USB1 port.
Signed-off-by: Benjamin Hahn <[email protected]>
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sync devicetree with kernel v6.8-rc2.
New commits on kernel v6.8-rc2:
4a58fcdb1818 arm64: dts: imx8mp-phyboard-pollux: Add support for RS232/RS485
3bd7fdcc359e arm64: dts: imx8mp-phyboard-pollux: Add gpio-line-names
f5faa633daf8 arm64: dts: imx8mp-phyboard-pollux: Enable USB support
27c0dc128d04 arm64: dts: imx8mp-phyboard-pollux: Add flexcan support
fa2a1ec50456 arm64: dts: imx8mp-phyboard-pollux: Add missing usdhc clocks assignment
055e38c76388 arm64: dts: imx8mp-phyboard-pollux-rdk: Fix led sub-node names
Signed-off-by: Benjamin Hahn <[email protected]>
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With Ethernet DM in place, there is no longer the need for having
the board_phy_config() anymore.
Remove it.
Confirmed that TFTP transfer still works fine without board_phy_config().
Signed-off-by: Fabio Estevam <[email protected]>
Reviewed-by: Igor Opaniuk <[email protected]>
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