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Add the defines and support for SPMI arbiters version 7,
which can handle up to 1024 peripherals, and can also drive
a secondary bus which is not implemented yet.
Signed-off-by: Neil Armstrong <[email protected]>
Acked-by: Caleb Connolly <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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The cnfg registers provides the owner id for each peripheral,
so we can use this id to check if we're allowed to write register
to each peripherals.
Since the v5 can handle more peripherals, add the max_channels to
scan more starting from version 5, make the channel_map store
32bit values and introduce the SPMI_CHANNEL_READ_ONLY flag to
mark a peripheral as read-only.
Signed-off-by: Neil Armstrong <[email protected]>
Acked-by: Caleb Connolly <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Since version 2, the cmd format has changed, takes helpers
from Linux driver and use a switch/case to handle all
versions in msm_spmi_write/read() command.
Signed-off-by: Neil Armstrong <[email protected]>
Acked-by: Caleb Connolly <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Properly use ch_offset in msm_spmi_write() reg access.
Fixes: f5a2d6b4b03 ("spmi: msm: add arbiter version 5 support")
Signed-off-by: Neil Armstrong <[email protected]>
Acked-by: Caleb Connolly <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Support for Schneider Electric HMIBSC. Features:
- Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
- 2GiB RAM
- 64GiB eMMC, SD slot
- WiFi and Bluetooth
- 2x Host, 1x Device USB port
- HDMI
- Discrete TPM2 chip over SPI
Features enabled in U-Boot:
- RAUC updates
- Environment protection
- USB based ethernet adaptors
Signed-off-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Schneider HMIBSC board dts has already been reviewed upstream on the
linux-arm-msm mailing list. So once it comes through the Linux kernel
release cycle into the U-Boot dts/upstream subtree, a switch to
OF_UPSTREAM can be made. For the time being maintain the U-Boot copy.
Link: https://lore.kernel.org/linux-kernel/[email protected]/
Signed-off-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Add GPIO pinctrl function to enable driving GPIO pins as output low or
high.
Signed-off-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Add support for driving the GPIO pins as output low or high.
Signed-off-by: Sumit Garg <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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SE HMIBSC board debug console requires RS232 flow control, so enable
corresponding support if RS232 gpios are present.
Reviewed-by: Caleb Connolly <[email protected]>
Signed-off-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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SE HMIBSC board uses UART1 as the main debug console, so add
corresponding clocks and pinmux support. Along with that update
instructions to enable clocks for debug UART support.
Reviewed-by: Caleb Connolly <[email protected]>
Signed-off-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Enabling LINUX_KERNEL_IMAGE_HEADER by default doesn't allow
ENABLE_ARM_SOC_BOOT0_HOOK to work properly on db410c when U-Boot is
loaded as a first stage bootloader. It leads to secondary CPUs bringup
failure and later causing the Linux kernel to freeze.
So fix it via selectively enabling LINUX_KERNEL_IMAGE_HEADER where it's
actually required.
Fixes: 059d526af312 ("mach-snapdragon: generalise board support")
Reviewed-by: Caleb Connolly <[email protected]>
Signed-off-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Currently, IPQ4019 pinctrl driver supports only a very limited number of
pin functions and is not fully DT compatible with Linux pinctrl nodes.
IPQ40xx SoC-s sometimes use different pin function numbers for the same
function depending on the pin number, so for example I2C0 on GPIO58 uses
function number 3 while on GPIO59 it uses function number 2.
So, in order to make the driver compatible with upstream DTS to avoid the
need to patch the pinctrl nodes in U-Boot and support all of the missing
pin functions lets rework the driver based on upstream Linux IPQ4019
pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses
different function numbers pased on the exact pin number.
Signed-off-by: Robert Marko <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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If compiled with logging and debug UART support, the following is printed:
serial_msm serial@78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19
This is due to the fact that IPQ4019 pinctrl driver is not available prior
to relocation and thus MSM serial will fail probing as pinctrl provider is
not available.
So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this.
Signed-off-by: Robert Marko <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so
as a preparation update pinctrl driver to look for the upstream pin format.
Signed-off-by: Robert Marko <[email protected]>
Reviewed-by: Caleb Connolly <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Pinctrl driver was refactored and moved, but the required header that
it depends on was not included.
Fixes: 24d2908e987a ("pinctrl: qcom: move ipq4019 driver from mach-ipq40xx")
Signed-off-by: Robert Marko <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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IPQ4019 pinctrl driver was moved to the dedicated Qualcomm pinctrl
directory, but the KConfig depends on ARCH_SNAPDRAGON only and thus
PINCTRL_QCOM_IPQ4019 cannot be selected when ARCH_IPQ40XX is used.
Fixes: 24d2908e987a ("pinctrl: qcom: move ipq4019 driver from mach-ipq40xx")
Signed-off-by: Robert Marko <[email protected]>
Reviewed-by: Caleb Connolly <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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IPQ40xx SoC-s dont have proper SMEM support like more modern Qualcomm
SoC-s so there is no point in selecting the required drivers.
Signed-off-by: Robert Marko <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Give us lots of room for the appended FDT.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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These files are all identical (or older) than those in dts/upstream.
Drop them as we now use upstream DTS files with OF_UPSTREAM.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Switch to using upstream DT from dts/upstream.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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The driver currently requires the bit clock divider be hardcoded in
devicetree (or use the hardcoded default from apq8016).
The bit clock divider is used to derive the baud rate from the core
clock:
baudrate = clk_rate / csr_div
clk_rate is the actual programmed core clock rate which is returned by
clk_set_rate(), and this UART driver only supports a baudrate of 115200.
We can therefore determine the appropriate value for UARTDM_CSR by
iterating over the possible values and finding the one where the
equation above holds true for a baudrate of 115200.
Implement this logic and drop the non-standard DT bindings for this
driver.
Tested on dragonboard410c.
Tested-by: Robert Marko <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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clk_set_rate() should return the clock rate that was set. The IPQ4019
clock driver doesn't set any rates yet but it should still return the
expected value so that drivers can work properly.
For a baud rate of 115200 with an expected bit clock divisor of 16, the
clock rate should be 1843200 so return that frequency.
Signed-off-by: Caleb Connolly <[email protected]>
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The clk_init_uart() helper always returns 0, but we're meant to return a
real clock rate. Given that we hardcode 115200 baud, just return the
clock rate that we set.
Signed-off-by: Caleb Connolly <[email protected]>
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MSM serial in DEBUG UART mode is trying to set .clk_rate, but the
msm_serial_data structure does not have such property at all, so lets
remove it as otherwise it will fail compiling.
Fixes: 90023bdfe979 ("serial: msm: add debug UART")
Signed-off-by: Robert Marko <[email protected]>
Reviewed-by: Caleb Connolly <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Currently, DEBUG_UART_MSM depends on ARCH_SNAPDRAGON only, but IPQ40XX
devices also use the same UART HW so they can also use the debug UART.
So, allow selecting DEBUG_UART_MSM when using ARCH_IPQ40XX as well.
Signed-off-by: Robert Marko <[email protected]>
Reviewed-by: Caleb Connolly <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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The addresses were mistakenly swapped. Put them right.
Reported-by: Sumit Garg <[email protected]>
Fixes: a737d8962cae ("mmc: msm_sdhci: correct vendor_spec_cap0 register for v5")
Signed-off-by: Caleb Connolly <[email protected]>
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Add the newly created u-boot-qcom mailing list to keep track of Qualcomm
patches.
Additionally, link to the U-Boot Snapdragon custodian tree.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Qcom SoCs derived boards can come from various OEMs/ODMs and not just
Qcom itself. So allow CONFIG_SYS_VENDOR to be set correctly
corressponding to the actual board vendor.
Suggested-by: Stephan Gerhold <[email protected]>
Reviewed-by: Caleb Connolly <[email protected]>
Signed-off-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Enable the SM8550 & SM8650 clock driver in the Qualcomm defconfig.
Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Caleb Connolly <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Add the GCC and TCSRCC clock driver for the SM8650 SoC.
The GCC driver uses the clk-qcom infrastructure to support GDSCs,
Resets and gates. While the TCSRCC is a simpler clock driver which
only supports gates.
The GCC enable and set_rate callbacks contains some tweaks to
setup clocks for Debug UART, SDCard controller and USB.
The TCSRCC gates returns the XO frequency, which is used by the
Synopsys eUSB2 driver to determine the PHY configuration.
Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Caleb Connolly <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Add the GCC and TCSRCC clock driver for the SM8550 SoC.
The GCC driver uses the clk-qcom infrastructure to support GDSCs,
Resets and gates. While the TCSRCC is a simpler clock driver which
only supports gates.
The GCC enable and set_rate callbacks contains some tweaks to
setup clocks for Debug UART, SDCard controller and USB.
The TCSRCC gates returns the XO frequency, which is used by the
Synopsys eUSB2 driver to determine the PHY configuration.
Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Caleb Connolly <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Remove the reference to the xo clock which is on the unsupported rpmhcc
clock controller. It isn't needed for MMC functionality.
Signed-off-by: Caleb Connolly <[email protected]>
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Adjust sdm845_get_pin_name() to return the correct names for the special
pins. This fixes a non-fatal -ENOSYS error when probing MMC.
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Allow setting the clock rate for the SD card core clock. This is
required for SD card support on SDM845 devices.
Signed-off-by: Caleb Connolly <[email protected]>
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We currently default to the lowest rate but this actually doesn't work
on most platforms. Default to the HS400 speed instead which is most
common on Qualcomm platforms.
Signed-off-by: Caleb Connolly <[email protected]>
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This is useful for debugging.
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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using fdtdec_* functions is incompatible with OF_LIVE and generally
offers a less friendly interface. Update to use dev_read_* functions
instead.
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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The V4 and V5 controllers have quite varied register layouts. Inherit
the register offsets and naming from the Linux driver. More version
specific offsets can be inherited from Linux as needed.
Fixes: 364c22a ("mmc: msm_sdhci: Add SDCC version 5.0.0 support")
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Enable three new clock drivers.
Signed-off-by: Caleb Connolly <[email protected]>
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Add a clock driver for the SM8250 SoC. This driver can enable necessary
clocks for UART, UFS, USB, and MMC.
Signed-off-by: Caleb Connolly <[email protected]>
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Add a driver for the clock controller in the SM6115 SoC, this is used in
the QRB4210 RB2 board.
Signed-off-by: Caleb Connolly <[email protected]>
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Add a clock driver for the QCM2290 SoC which is used in the QRB2210 RB1
board.
Signed-off-by: Caleb Connolly <[email protected]>
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Finally add the entries for the qcom,pmk8350-pwrkey and qcom,pmk8350-resin
found on PMICs used with SM8350 and later SoCs.
Signed-off-by: Neil Armstrong <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Move node name checks to a proper data struct with all information
for the supported subnodes.
Replace the key offset defines with the Linux driver ones.
Signed-off-by: Neil Armstrong <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Add support for PM8550 GPIO controller variant, keep read-only
until the GPIO and Pinctrl setup is fixed for new PMICs.
Signed-off-by: Neil Armstrong <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Enable the clock and pinctrl drivers for qcm2290, sm6115, and sm8250.
Reviewed-by: Neil Armstrong <[email protected]>
Acked-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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This SoC features a pinctrl block with north, south, and west tiles
accessible to the AP.
Reviewed-by: Neil Armstrong <[email protected]>
Acked-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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This SoC features a pinctrl block with west, east, and south tiles.
Reviewed-by: Neil Armstrong <[email protected]>
Acked-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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This SoC has a basic pinctrl block with no tiles.
Reviewed-by: Neil Armstrong <[email protected]>
Acked-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Enable the SM8550 & SM8650 pinctrl drivers for Qualcomm defconfig.
Signed-off-by: Neil Armstrong <[email protected]>
Acked-by: Sumit Garg <[email protected]>
Reviewed-by: Caleb Connolly <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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