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Add below test cases for i2c commands:
i2c_bus - To show i2c bus info,
i2c_dev - To set or show the current bus,
i2c_probe - To probe the i2c device,
i2c_eeprom - To test i2c eeprom device,
i2c_probe_all_buses - To list down all the buses and probes it
Signed-off-by: Love Kumar <[email protected]>
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Add below test cases for mii commands:
mii_info -To display MII PHY info
mii_list - To list MII devices
mii_set_device - To set MII device
mii_read - To reads register from MII PHY address
mii_dump - To display data from MII PHY address
Signed-off-by: Love Kumar <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Add pe2201 platform code and the device tree of pe2201 platform board.
The initial support comprises the UART and PCIe.
Signed-off-by: TracyMg_Li <[email protected]>
Changes since v1:
fix space corrupt.
Changes since v2:
switch to bootstd and text environment.
Changes since v3:
add environment variables.
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next_header() and get_next_header() only differ in how the const attribute
is used. One function taking a const parameter and returning a non-const is
good enough.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
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QEMU provides SMBIOS tables with detailed information. We should not try to
replicate them in U-Boot.
If we want to inform about U-Boot, we can add a Firmware Inventory
Information (type 45) table in future.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add support for J721E HS-SE 2.0 device. Make use of the existing
templates and override the phandles for sysfw.itb so that builds do not
fail.
Signed-off-by: Neha Malcom Francis <[email protected]>
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Add documentation for PHYTEC phyCORE-AM62x SoM.
Signed-off-by: Wadim Egorov <[email protected]>
Reviewed-by: Dhruva Gole <[email protected]>
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Add basic support for PHYTEC phyCORE-AM62x SoM.
Supported features:
- 2GB DDR4 RAM
- eMMC Flash
- OSPI NOR Flash
- external uSD
- Ethernet
- debug UART
Product page SoM: https://www.phytec.com/product/phycore-am62x
Device trees were taken from Linux v6.7-rc3.
Signed-off-by: Wadim Egorov <[email protected]>
Reviewed-by: Dhruva Gole <[email protected]>
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Add below test cases for mdio commands:
mdio_list - To list MDIO buses
mdio_read - To read PHY's register at <devad>.<reg>
mdio_write - To write PHY's register at <devad>.<reg>
Signed-off-by: Love Kumar <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Abort the dhcp request in the middle by pressing ctrl + c on u-boot
prompt and validate the abort status.
Signed-off-by: Love Kumar <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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https://gitlab.denx.de/u-boot/custodians/u-boot-snapdragon
Qualcomm architecture changes:
* Move clock and pinctrl drivers out of mach-snapdragon
* Various clock driver improvements
* Convert PMIC power/reset key driver to use the button API
* Preparetory work for migrating to upstream DT
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
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sandbox_flattree enables QCOM_PMIC_GPIO which now depends on BUTTON. As
a result the button tests now get run, but fail because the ADC and GPIO
button drivers aren't enabled.
Enable them to run the tests for sandbox_flattree.
Reported-by: Neil Armstrong <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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With the recent changes to the Qualcomm PMIC GPIO driver the sandbox
tests for it no longer pass, update the DTS and tests to work with the
changes.
Signed-off-by: Caleb Connolly <[email protected]>
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Linux DTs stuff a value indicating if the USID is a USID or a GSID in the
reg property, the Linux SPMI driver then reads the two address cells
separately. U-boot's dev_read_addr() doesn't know how to handle this, so
use ofnode_read_u32_index() to get just the USID.
The Qcom pmic driver doesn't have support for GSID handling, so just
ignore the second value for now.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Tested-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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The core and chnl register ranges were swapped on SDM845. Fix it, and
fetch the register ranges by name instead of by index.
Drop the cosmetic "version" variable and clean up the debug logging.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Tested-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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This property is not part of the dt bindings and all boards use the new
gpio-ranges property instead. Drop support for this.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Tested-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Use the upstream gpio-ranges property instead of gpio-count, and drop
the bank-name property for Qualcomm boards.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Tested-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Upstream uses the gpio-ranges property to define the number of GPIOs,
support for parsing this when gpio-count is unspecified
Additionally, drop the bank-name property as it isn't used in upstream,
and we can just hardcode the bank name instead.
Reviewed-by: Sumit Garg <[email protected]>
Tested-by: Sumit Garg <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Remove the (now unused) GPIO driver for the power and resin buttons on
the PMIC.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Tested-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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The PMIC button driver is a much better representation of the hardware
here, adjust the boards to use upstream DT and the PMIC button driver
instead of exposing the buttons as GPIOs and relying on the GPIO-button
driver.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Tested-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Qualcomm PMICs include a "pon" function which handles two buttons, the
power button and "resin" button (usually volume down). Introduce a new
driver following upstream Linux DT to enable these and map them to Enter
and Down respectively to enable use in boot menus.
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Tested-by: Sumit Garg <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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priv->pid is uint32_t, but dev_read_addr() returns a uint64_t on arm64,
with the upper bits being used for error codes. Do error checking before
downcasting to u32 to prevent errors being silently ignored.
Reviewed-by: Sumit Garg <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Tested-by: Sumit Garg <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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devm_clk_get() returns an ERR_PTR on failure, not null. Fix the check to
avoid the board crashing when the clock isn't available.
Additionally, add the missing error handling for this function.
Fixes: 324df15a292e ("serial: qcom: add support for GENI serial driver")
Signed-off-by: Caleb Connolly <[email protected]>
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commit 1b15483deb3f ("misc: add Qualcomm GENI SE QUP device driver")
introduced support for platform-specific oversampling values, necessary
to configure the UART clocks on all platforms at runtime. However it
relies in probing a parent device. Despite the DM_FLAG_PRE_RELOC flag,
this is not done consistently during boot.
Instead, take another approach by relying on ofnode_ helpers to read the
serial engine base address and do the read directly. This fixes early
UART on boards with a non-default oversampling rate.
Signed-off-by: Caleb Connolly <[email protected]>
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Replaces the uses of "unsigned" with "unsigned int".
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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The pinctrl and GPIO drivers are currently heavily incompatible with
upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at
it's own address. Introduce support for these by allowing the soc driver
to specify per-pin register offsets similarly to the Linux driver.
Adjust the GPIO driver to handle these too, and finally enable support
for all pins with the same numbering as used in Linux.
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add
it to drivers/pinctrl/qcom.
Acked-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Move the Qualcomm pinctrl drivers out of mach-snapdragon and over to the
rest of the pinctrl drivers, adjust the drivers so that support for each
platform can be enabled/disabled individually and introduce platform
specific configuration options.
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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The RCG divider field takes a value of (2*h - 1) where h is the divisor.
This allows fractional dividers to be supported by calculating them at
compile time using a macro.
However, the clk_rcg_set_rate_mnd() function was also performing the
calculation. Clean this all up and consistently use the F() macro to
calculate these at compile time and properly support fractional divisors.
Additionally, improve clk_bcr_update() to timeout with a warning rather
than hanging the board, and make the freq_tbl struct and helpers common
so that they can be reused by future platforms.
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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This property is needed on some platforms to ensure that only the
relevant bits are set in the M/N/D registers.
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Currently, it isn't possible to build clock drivers for more than one
platform due to how the msm_enable() and msm_set_rate() callbacks are
implemented.
Extend qcom_clk_data to include function pointers for these and convert
all platforms to use them.
Previously, clock drivers relied on include/configs/<board.h> to include the
board specific sysmap header, however as most of the header contents are clock
driver related, import the contents directly into each clock driver and
remove the header. The only exception here is the dragonboard820c board file
which includes some pinctrl macros, those are also inlined.
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
[caleb: remove additional sysmap-sdm845.h mention]
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Many gate clocks can be enabled with a single register write, add support
for defining these simple gate clocks and add the ones found on SDM845.
While we're here, inline clk_init_uart() into msm_set_rate().
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Qualcomm's clock controller blocks actually do much more than it
says on the tin.. They provide clocks, resets and power domains.
Currently, U-Boot requires one to spawn 2 separate devices for
controlling clocks and resets, both spanning the same register space.
Refactor the code to make it work with just a single DT node, making
it compatible with upstream Linux bindings and dropping the dedicated
reset driver in favour of including it in the clock driver.
Heavily inspired by Renesas code for a similar hw block.
[caleb: moved drivers to clk/qcom, added reset driver and adjusted bind
logic. Imported qcom,gcc-ipq4019.h from Linux]
Signed-off-by: Konrad Dybcio <[email protected]>
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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This driver is just a stub, but it's necessary to support the upcoming
reset driver changes.
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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Clock drivers don't belong here, move them to the right place and
declutter mach-snapdragon a bit.
To de-couple these drivers from specific "target" platforms, add
additional config options to enable each clock driver gated behind a
common CLK_QCOM option and enable them by default for the respective
targets. This will make future work easier as we move towards a generic
Qualcomm target.
Reviewed-by: Sumit Garg <[email protected]>
Signed-off-by: Caleb Connolly <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-nand-flash
Pull request for u-boot-nand-20240115
The first patch is by Heinrich Schuchardt and fixes an integer overflow
The following two patches are by Dario Binacchi and add arguments check
to the nand_mtd_to_devnum() and nand_register() functions.
The remaining patches are by Roger Quadros and include various fixes for
the OMAP platform.
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We load two boot image source descriptor structures from last
two sectors in the SPI NOR flash and determine the boot source
for loading the kernel/DTB images, then adjust the boot order for
loading image from eMMC boot0 or boot1 partition.
Signed-off-by: Anatolij Gustschin <[email protected]>
Signed-off-by: Lukasz Majewski <[email protected]>
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The boot0/1 feature uses simple CRC8 to check (in SPL) if
SPI-NOR content is not corrupted, hence the need to enable
it.
Signed-off-by: Lukasz Majewski <[email protected]>
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The default set of environment variables from CFG_EXTRA_ENV_SETTINGS
has been moved to a separate file - board/liebherr/xea/xea.env
Adjustments done:
- fitImage support
- SPI-NOR layout re-organization
Signed-off-by: Lukasz Majewski <[email protected]>
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Commit aa7858fe5e2e ("board: phytec: som_detection: move definitions to
source file") moved function definitions from header to source file.
Makefile however was not updated to unconditionally (from
[..]_SOM_DETECTION) build the imx8 and phytec som detection units.
Also remove unused includes that cause build failures on arm 32bit
boards. SoM detection shall support 32bit boards as well, but arch
specific code should not be included in the generic module.
Fixes: aa7858fe5e2e ("board: phytec: som_detection: move definitions to source file")
Signed-off-by: Yannic Moog <[email protected]>
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AM642 SoC supports booting from GPMC NAND device.
Define boot device for it.
Signed-off-by: Roger Quadros <[email protected]>
Link: https://www.mail-archive.com/[email protected]/msg499180.html
Signed-off-by: Dario Binacchi <[email protected]>
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Set NAND chip ofnode and device so OF based partition parsing
can work.
Signed-off-by: Roger Quadros <[email protected]>
Link: https://www.mail-archive.com/[email protected]/msg499178.html
Signed-off-by: Dario Binacchi <[email protected]>
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For DM case we can get the NAND chip's IO address from DT
so we don't need to rely on CFG_SYS_NAND_BASE.
Signed-off-by: Roger Quadros <[email protected]>
Reviewed-by: Dario Binacchi <[email protected]>
Link: https://www.mail-archive.com/[email protected]/msg499177.html
Signed-off-by: Dario Binacchi <[email protected]>
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sys_proto.h no longer exists for K3 platform so drop it.
Include sizes.h to so SZ_16M is visible.
Signed-off-by: Roger Quadros <[email protected]>
Reviewed-by: Dario Binacchi <[email protected]>
Link: https://www.mail-archive.com/[email protected]/msg499176.html
Signed-off-by: Dario Binacchi <[email protected]>
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The macro ELM_BASE is defined in mach/hardware.h and is
not visible at the omap_elm.h header file. Avoid using it
in omap_elm.h.
Reported-by: Hong Guan <[email protected]>
Fixes: 7363cf0581a3 ("mtd: rawnand: omap_elm: u-boot driver model support")
Signed-off-by: Roger Quadros <[email protected]>
Link: https://lore.kernel.org/all/[email protected]
Signed-off-by: Dario Binacchi <[email protected]>
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AM335x uses a special driver "am335x_spl_bch.c" as SPL
NAND loader. This driver expects 1 sector at a time ECC
and doesn't work well with multi-sector ECC that was implemented in
commit 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction")
Additionally, the omap_elm driver does not support multi sector ECC and will
need more work and tests to get multi sector working correctly on all
platforms.
Switch back to 1 sector at a time read/ECC.
Fixes: 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction")
Signed-off-by: Roger Quadros <[email protected]>
Tested-by: Enrico Leto <[email protected]>
Tested-by: Heiko Schocher <[email protected]>
Link: https://lore.kernel.org/all/[email protected]/
Signed-off-by: Dario Binacchi <[email protected]>
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If the "mtd" parameter is NULL, the search will definitely yield a
negative result. In that case, it's better to exit immediately.
Signed-off-by: Dario Binacchi <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
Link: https://lore.kernel.org/all/[email protected]
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The patch checks that the "mtd" parameter is accessible before
proceeding.
Signed-off-by: Dario Binacchi <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
Link: https://lore.kernel.org/all/[email protected]
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mtd dump beyond 4 GiB will show incorrect results.
Multiplying two u32 will yield a u32. Add a missing cast.
Fixes: 5db66b3aee6f ("cmd: mtd: add 'mtd' command")
Addresses-Coverity-ID: 477205 ("Unintentional integer overflow")
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Miquel Raynal <[email protected]>
Link: https://lore.kernel.org/all/[email protected]
Signed-off-by: Dario Binacchi <[email protected]>
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