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- None of the callers perform error checking and based on the non-empty
versions of this function, there's no checking to be done, so make
this a void.
- Add a default weak version of the function.
- Remove the empty versions of exynos_init now that we have a weak
version.
Signed-off-by: Tom Rini <[email protected]>
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As part of reviewing a new platform, Daniel Schwierzeck noted that we
can have an empty Makefile in the board directory and don't need an
empty board.c file as well. Further with further cleanup in the
Makefile we can now omit the Makefile entirely. Remove a number of now
unnecessary board.c and Makefiles.
Signed-off-by: Tom Rini <[email protected]>
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It is entirely possible at this point to have platforms in U-Boot that
do not have board-specific C code (just Kconfig or environment) and so
make it optional to have to descend in to and then build in the board
directory.
Signed-off-by: Tom Rini <[email protected]>
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Allow for a proper configuration of CFI flash banks avaialble on the vexpress_ca9x4
board. Without this option, the CFI flash incorrectly detects that the board has two
banks of 32MB flash devices, while in reality, the board provides
two flash banks, each with 64MB size. As a result, it becomes impossible to e.g. to
save u-boot env in flash. According to device tree for this board and
its implementation in QEMU, the CFI width should be set to 32 bits.
After applying this fix, CFI flash will correctly detect both flash
banks each with a size of 64MB. As as result the functionality of e.g. saving u-boot
env will work correctly.
Tested on QEMU 6.2.0.
Cc: Kristian Amlie <[email protected]>
Signed-off-by: Patryk Biel <[email protected]>
Reviewed-by: Kristian Amlie <[email protected]>
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Use ARCH_DMA_MINALIGN in memalign() when allocating memory to read the script from the media.
Ref: https://lore.kernel.org/u-boot/CAJaLiFy05F3Cr4X4G2mVkppXnBEFZrHQ+5CngYN8eJPg8ENWkg@mail.gmail.com/T/#m26daadc2463fe653b814a94e6309e5e6bb6be1d1
Note: this patch depends on the previous patch
https://patchwork.ozlabs.org/project/uboot/patch/[email protected]/
Signed-off-by: Tony Dinh <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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If the source .env file changes to one that is also older than the
generated env.txt file then the .env file is not regenerated. This
means when switching board configs we do not regenerate the env.
This can be tested with:
$ make j721e_evm_a72_defconfig
$ make # this may fail to complete but that is okay for this test
$ make am64x_evm_a53_defconfig
$ make
$ vim include/generated/env.txt
Note this is still the J721e env not the AM64 config as expected.
As ENV_FILE is set based on configuration, regenerate anytime
autoconf.h changes.
Signed-off-by: Andrew Davis <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The SelectMAP configuration interface provides an 8-bit,
16-bit or 32-bit bidirectional data bus interface to the Versal FPGA
configuration logic that can be used for both configuration and readback.
A connected microcontoller to the SelectMAP interface can load boot
image with bitstream, TF-A (ARM Trusted Firmware) and U-Boot.
This commit adds the missing identification of the SelectMAP mode.
Signed-off-by: Polak, Leszek <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: Stefan Roese <[email protected]>
Link: https://lore.kernel.org/r/DU0PR07MB8419F7765892CDBCE7D559C5C8CFA@DU0PR07MB8419.eurprd07.prod.outlook.com
Signed-off-by: Michal Simek <[email protected]>
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Character '_' not recommended in node name. Use '-' instead.
Pretty much run sed below for node names.
s/si5335_/si5335-/
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/ac752b1e27f02efb32608188992bb7ae50e4b1b0.1695809130.git.michal.simek@amd.com
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This partially reverts commit ff33227819f579ffb963e0dac6bc6a6566b89563.
Versal NET clock node should use "xlnx,versal-net-clk", "xlnx,versal-clk"
compatible string that's why it is not necessary to define Versal NET
specific compatible string if there is no any other change needed. It can
be get back if there is a need to differentiate clock support between
Versal and Versal NET.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/c09276022db5f1b150679cc7a9f9583363ace2fb.1695808971.git.michal.simek@amd.com
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Using '_' is not recommended for node names. Use '-' instead.
Pretty much run seds below for node names.
s/heartbeat_led/heartbeat-led/
s/gtr_sel/gtr-sel/
s/zynqmp_ipi/zynqmp-ipi/
s/nvmem_firmware/nvmem-firmware/
s/soc_revision/soc-revision/
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/dd33d6cb0595ffedab117d477f4a3c9d9eb11715.1695808665.git.michal.simek@amd.com
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Xilinx was using in past is-dual property for QSPIs to reflect their
configurations. But handling for them never reached upstream code that's
why better to remove them.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/15980560b98672959a889ff9970cbe9540b4ed69.1695808563.git.michal.simek@amd.com
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RevB has different SD level shifter compare to revA. There are couple of
changes between revisions but none of them requires SW alignment.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/0f2bb29f88615ce75f887c006060543b4aeafd48.1695808407.git.michal.simek@amd.com
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The board is sharing a lot of components with zcu208 but it contains
differet silicon and also several components are done differently.
The board has 4GB memory connected to PS and additional 4GB connected to
PL. Compare to zcu208 sata support has been dropped and only USB3.0 is
using GTR (lane2). Others GTRs are routed to connectors.
MIO configuration is also shared with zcu111.
The board is using si5381 chip compare to si5341 which is normally used.
And as of now there is no Linux driver for this chip. PS reference clock is
generated out of si570 chip which is also new approach compare to zcu208.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/3b296ef0f52bd94e32bdeb6d1beee29ac85f00a2.1695808407.git.michal.simek@amd.com
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VPXA2785(vp-x-a2785-00) is evaluation board which contains two PCIe-Edge
fingers, one for PCIe-B(gen5x8) and one for CPM(dual gen5x8, gen5x16).
Each of the ports can operate in endpoint or root port mode. This allows
the single card to be used for both root port, endpoint, and switch modes.
The board is designed in the similar manner as others Versal boards. It
means board also have ZynqMP Zu4 System Controller which is described in a
separate file.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/59d3b1f7e785bc65518b465e5122fd2787616a93.1695808407.git.michal.simek@amd.com
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Generic system controller (SC) covers connection defined by specification
but different boards have different i2c devices. That's why describe i2c
devices available on multiple boards.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/ca1826b8b58981111229a94527818cc5a191ca9a.1695808407.git.michal.simek@amd.com
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System controller revC is using ADI ethernet phy instead of TI because of
supply chain issues.
Describe reset assert and de-assert times to 10us and 5ms respectively
according to the datasheet. Also setup RGMII RX and TX delay values to
2400ps as per board bring up observations.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/2790f6cede7485556d581ab8270dda477fa21522.1695808407.git.michal.simek@amd.com
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System controllers are pretty much the same on the all boards that's why
use autodetection based on i2c eeprom. This should end up with having only
one BSP for all SCs with only DT overlays to cover different i2c
structures.
All MIOs are fixed by the spec that's why not a problem to description
pinctrl setting.
Apart from eth phy reset, it also set proper phy delays.
The TI DP83867 PHY datasheet says:
T1: Post RESET stabilization time == 195us
T3: Hardware configuration pins transition to output drivers == 64us
T4: RESET pulse width == 1us
So with a little overhead set 'reset-assert-us' to 100us (T4) and
'reset-deassert-us' to 280us (T1+T3).
NOTE: The tuning of TI DP83867 phy reset delay is derived from linux
upstream commit: 5dbadc848259(arm64: dts: fsl: add support for Kontron
pitx-imx8m board).
i2c structure on Xilinx Versal evaluation platforms contain a lot of
devices but also connection to connectors like SFP. Because of this
complicated structure with also all level shifters, i2c muxes, etc. not all
devices are able to reliably work on 400kHz even if they are compatible
with this speed. That's why set i2c frequency to 100KHz to increase
reliability of the i2c bus.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/c8092340f92144f0cc9096194198f227015bc013.1695808407.git.michal.simek@amd.com
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Board contains two systems. The primary is Versal VP1202 ACAP device and
the secondary is ZynqMP zu4 which acts as system controller. The patch is
describing only ZynqMP system controller part.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/bd8b79d7c6693e90e12bce422f8ed00f2f43c9ae.1695808407.git.michal.simek@amd.com
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Add i2c accessible devices with description.
There is versal specific eeprom and i2c-gpio controller.
SE3 has also clock chip present.
Also remove x-prc description from SC dts.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/4f71ec6a63240fd4aaa3453824138281c50d71c3.1695808407.git.michal.simek@amd.com
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There are some changes between revA and revB boards. u39 8T49N240 was
removed and also three ina226 at 42/43/44 addresses (u178/u180/u182).
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/461cfe5b2b882365413f90d19efd8abcd6be56ed.1695808407.git.michal.simek@amd.com
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xlnx,fclk nodes are not described in dtschema that's why remove them.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/b25dedd066f587321751d7d20c1f65bb96c53b89.1695808407.git.michal.simek@amd.com
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Add support for KD240 Kria SOM CC. It is pretty much subset of KR260 board
from PS perspective.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/835f1d1b8982d46b902db69daad64e8445c051e9.1695808407.git.michal.simek@amd.com
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Official DT binding description for dual stacked/paralllel configurations
have been merged that's why switch to it.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/2912091c231f5e945ee44601c285fe16263448da.1695378830.git.michal.simek@amd.com
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Linux requires to describe nand structure under nand controller.
If it is not described nand device is not detected by Linux.
Error shown by Linux kernel:
pl35x-nand-controller e1000000.nand-controller: Incorrect number of NAND chips (0)
pl35x-nand-controller: probe of e1000000.nand-controller failed with error -22
When wired:
nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xda
nand: Micron MT29F2G08ABAEAWP
nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/3fcd68ccdfed5e6c079681e3b29e06583ec8a375.1695378830.git.michal.simek@amd.com
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There is difference between licenses in the Linux kernel and there
shouldn't be any diff because all changes are coming from the same source
at the same time. The difference is really in a time when they were
upstreamed. That's why sync it up.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/813b29378083153b67c60772f28cd2613519f338.1695378830.git.michal.simek@amd.com
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File was in UTF-8 format but there is no reason for it. Convert it to
ASCII/plain text.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/e4d52b898b461b86bb82009f37635f351279c753.1695378830.git.michal.simek@amd.com
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The DPSUB DT bindings now specify ports to model the connections with
the programmable logic and the DisplayPort output. Add them to the
device tree.
Signed-off-by: Laurent Pinchart <[email protected]>
Acked-by: Michal Simek <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/1c91420e90bc823d7529834c33438216857c7161.1695378830.git.michal.simek@amd.com
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Add a device tree node to describe the DisplayPort connector, and
connect it to the DPSUB output.
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/fe037c93ed41bc5ca97887964037520d449ca98c.1695378830.git.michal.simek@amd.com
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Some boards are using one mdio bus which holds multiple phys and also
boards are using mdio node for bus description. That's why there are cases
where address/size-cells are unnecessary which is also reported by make W=1
dtbs. That's why remove them from zynqmp.dtsi and let board DTSes to handle
it based on used description.
Error log:
/axi/ethernet@ff0e0000: unnecessary #address-cells/#size-cells without
"ranges" or child "reg" property
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/02f308c774d4f2a798a9a8c066824114a19841a7.1695378830.git.michal.simek@amd.com
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All zynqmp boards have been already described via mdio node that's why also
convert the rest of the boards. With using mdio node there is an option to
add reset property for the whole mdio bus which is reflected by
's/phy-reset-gpios/reset-gpios/g' for some boards.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/ff165281a70a38e2b76fee91e6255ce95ce8021b.1695378830.git.michal.simek@amd.com
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Some patches didn't have his full name and also there was one more ">" at
the end of email address. That's why correct both of these issues.
Fixes: 174d728471d5 ("arm64: zynqmp: Switch to amd.com emails")
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/e970cc0dfabe293c2baf6b231d34f3af0386f1eb.1695378830.git.michal.simek@amd.com
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SD card is connected with 4 data lines which should be described properly.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/065cb9f1c6706eb4d70066e25cfc30d17b9f875d.1695378830.git.michal.simek@amd.com
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Lower case should be used for register address.
Issue is reported as:
flash@0: partitions: Unevaluated properties are not allowed
('partition@22A0000' was unexpected)
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/66b3361df883ecab4f36ce3b4196fb606c802598.1695378830.git.michal.simek@amd.com
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Partitions are described via fixed-partitions that's why there is no need
to have address/size-cells in flash node.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/c704be9d9f3d09c1cc55b092efeb9c73fcda6451.1695378830.git.michal.simek@amd.com
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RPU subsystem can be configured in cluster-mode or split mode.
Also each r5 core has separate power domains.
Signed-off-by: Tanmay Shah <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/dde364939b4fbe3f7be7b6f5dff42e7d8b2f5c46.1695378830.git.michal.simek@amd.com
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Use arm-gic.h and irq.h for interrupt description. It helps to improve
readability of device tree file.
Suggested-by: Laurent Pinchart <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/e0db567e1eb4e4e90e59270f41708919682dacf4.1695378830.git.michal.simek@amd.com
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The code is not called that's why remove it.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/7b207e90f68028ab36fcc22df4127492f174793d.1695046281.git.michal.simek@amd.com
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Use dtso suffix instead of dts. Build option was introduced by
commit a0f9a77912b2 ("kbuild: Allow DTB overlays to built from .dtso named
source files").
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/1dce37e72428c14a3ccbb5dc674b90dfe56b75ac.1695046155.git.michal.simek@amd.com
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Describe assigned-clocks for both uarts. SOM is using this functionality.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/bddbb81209a4567b0939c5d2d0ecb42fdfcd71ea.1695036114.git.michal.simek@amd.com
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Read the tristate config for all the pins and display it.
ZynqMP> pinmux status MIO1
MIO1: slew:fast bias:enabled pull:up input:cmos drive:12mA
volt:1.8 tri_state:enabled
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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For Xilinx ZynqMP SOC new parameter was added and now it can
set 7 parameters for its pins. Pinmux status command will
print the status of these parameters for each pin. But
current print buffer length is only 80 characters long, increase it
to 90 to print all the parameters without truncation.
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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MDC clock change needs to be done when the driver probe function
is called as mdio is enabled at probe and not when the ethernet starts.
Setup the MDC clock at the probe itself.
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Add Board: rk3568 Bananapi R2Pro;
- Update pcie bifurcation support;
- dwc_eth_qos controller support for rk3568 and rk3588;
- Compressed binary support for U-Boot on rockchip platform;
- dts and config updates for different board and soc;
[ trini: Fix conflict on include/spl.h ]
Signed-off-by: Tom Rini <[email protected]>
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A RK8XX PMIC is typically using i2c0 on RK356x devices. Add bootph-all
to required pinctrl nodes to simplify use of the prevent booting on
power plug-in option in SPL.
With the following Kconfig options and nodes in u-boot.dtsi the prevent
booting on power plug-in option can work in SPL.
CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_PINCTRL=y
CONFIG_SPL_PMIC_RK8XX=y
&i2c0 {
bootph-pre-ram;
};
&rk817 {
bootph-pre-ram;
regulators {
bootph-pre-ram;
};
};
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The commit 30975fb73d51 ("rockchip: Add option to prevent booting on
power plug-in") introduce an option to prevent booting a device when the
device was powered on due to power plug-in instead of pressing a power
button.
This feature works by checking the power-on source during PMIC probe
and powers off the device if power-on source was power plug-in.
This check currently runs very late at PMIC probe in U-Boot proper.
Fix so that the power-on source check can work at probe time in SPL.
Also enable probe after bind and remove the PMIC banner in SPL.
With this we can use ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON and
SPL_PMIC_RK8XX to power off the device very quickly after TPL instead
of after TF-A and U-Boot proper has been loaded and run.
DDR V1.18 f366f69a7d typ 23/07/17-15:48:58
ln
LP4/4x derate en, other dram:1x trefi
ddrconfig:7
LPDDR4X, 324MHz
BW=32 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=16 Size=8192MB
change to: 324MHz
clk skew:0x64
change to: 528MHz
clk skew:0x58
change to: 780MHz
clk skew:0x58
change to: 1056MHz(final freq)
clk skew:0x40
out
Power Off due to plug-in event
Fixes: 30975fb73d51 ("rockchip: Add option to prevent booting on power plug-in")
Signed-off-by: Jonas Karlman <[email protected]>
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With PMIC_RK8XX, SYSRESET and CMD_POWEROFF options enabled it is
possible to power down a board using the poweroff command and turn the
board back on using a power button.
Enable the poweroff command on RK356x boards that have a button wired
to PMIC pwron.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Select SYSRESET_CMD_POWEROFF to use the sysreset implementation of the
poweroff command when PMIC_RK8XX is enabled.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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enable CONFIG_OF_LIBFDT_OVERLAY and use it on Radxa ROCK Pi S.
Signed-off-by: FUKAUMI Naoki <[email protected]>
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all rk3308 boards should use their own dtb file.
also, change fdt_addr_r to avoid following error:
"ERROR: Did not find a cmdline Flattened Device Tree"
it happens on Radxa ROCK Pi S (256MB/512MB) with kernel built from
Radxa BSP.
Signed-off-by: FUKAUMI Naoki <[email protected]>
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this patch adds support for PCIe3 (M.2 M key) and enables NVMe.
=> pci
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
00.00.00 0x1d87 0x3588 Bridge device 0x04
01.00.00 0x10ec 0x8125 Network controller 0x00
02.00.00 0x1d87 0x3588 Bridge device 0x04
03.00.00 0x1179 0x011a Mass storage controller 0x08
=> nvme scan
=> nvme info
Device 0: Vendor: 0x1179 Rev: AGHA4101 Prod: 79CA20WPKRYN
Type: Hard Disk
Capacity: 488386.3 MB = 476.9 GB (1000215216 x 512)
Signed-off-by: FUKAUMI Naoki <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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