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Add support of USB key boot in distro boot command.
Signed-off-by: Patrick Delaunay <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Activate the command stm32prog with CONFIG_CMD_STM32MPROG.
The CONFIG_SET_DFU_ALT_INFO is also activated to support
the required weak functions for the DFU virtual backen defined in
board/st/common/stm32mp_dfu.c.
Signed-off-by: Patrick Delaunay <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Enable USB related flags.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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stm32mp135f-dk board has a type-c connector to retrieve the connection
state. For now, simply force an active peripheral mode in u-boot for
flashing.
Signed-off-by: Fabrice Gasnier <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Device tree alignment with Linux kernel v6.6.rc1.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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Add script which installs U-Boot binaries from SD card to eMMC
and makes the eMMC bootable.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Align the script name with DH i.MX8MP DHCOM script name. Add
backward compatibility script to avoid breaking user scripts.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Add USART1 clock parents and mux configuration. This allows
support for configuring the USART1 as the serial console in
SPL and U-Boot via device tree. Without this patch the SPL
with usart1 serial console enabled crashes because it can
not find the clock specified in the device tree for usart1.
Signed-off-by: Anatolij Gustschin <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Ensure that the SoM and board code information is only printed when
CONFIG_SPL_DISPLAY_PRINT is set.
Signed-off-by: Harald Seiler <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
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Ensure that the RAM configuration line is only printed when
CONFIG_SPL_DISPLAY_PRINT is set.
Signed-off-by: Harald Seiler <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Add RNG node for STM32MP13x platforms.
Signed-off-by: Gatien Chevallier <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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STM32 RNG configuration should best fit the requirements of the
platform. Therefore, put a platform-specific RNG configuration
field in the platform data. Default RNG configuration for STM32MP13
is the NIST certified configuration [1].
While there, fix and the RNG init sequence to support all RNG
versions.
[1] https://csrc.nist.gov/projects/cryptographic-module-validation-program/entropy-validations/certificate/53
Signed-off-by: Gatien Chevallier <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Seed errors can occur when using the hardware RNG. Implement the
sequences to handle them. This avoids irrecoverable RNG state.
Try to conceal seed errors when possible. If, despite the error
concealing tries, a seed error is still present, then return an error.
A clock error does not compromise the hardware block and data can
still be read from RNG_DR. Just warn that the RNG clock is too slow
and clear RNG_SR.
Signed-off-by: Gatien Chevallier <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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In order to ensure a good RNG quality and compatibility with
certified RNG configuration, add RNG clock frequency restraint.
Signed-off-by: Gatien Chevallier <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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RNG clock error detection is now enabled if the "clock-error-detect"
property is set in the device tree.
Signed-off-by: Gatien Chevallier <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Default embed this configuration. If OP-TEE PTA RNG is exposed, it means
that the RNG is managed by the secure world. Therefore, the RNG node
should be disabled in the device tree as an access would be denied
by the hardware firewall.
Signed-off-by: Gatien Chevallier <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Rename the RNG driver as it is usable by other STM32 platforms
than the STM32MP1x ones. Rename CONFIG_RNG_STM32MP1 to
CONFIG_RNG_STM32
Signed-off-by: Gatien Chevallier <[email protected]>
Reviewed-by: Grzegorz Szymaszek <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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commit 6b443faa313c519db755ff90be32758fd9c66453 Linux upstream.
This is a preparation patch for the upcoming support to manage CAN
peripherals in single configuration.
The addition ensures backwards compatibility.
Signed-off-by: Dario Binacchi <[email protected]>
Link: https://lore.kernel.org/all/[email protected]
Signed-off-by: Marc Kleine-Budde <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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commit 559a6e75b4bcf0fc9e41d34865e72cf742f67d8e Linux upstream.
Add pin configurations for using CAN controller on stm32f469-disco
board. They are located on the Arduino compatible connector CN5 (CAN1)
and on the extension connector CN12 (CAN2).
Signed-off-by: Dario Binacchi <[email protected]>
Link: https://lore.kernel.org/all/[email protected]
Signed-off-by: Marc Kleine-Budde <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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commit 7355ad1950f41e755e6dc451834be3b94f82acd4 Linux upstream.
Add support for bxcan (Basic eXtended CAN controller) to STM32F429. The
chip contains two CAN peripherals, CAN1 the primary and CAN2 the secondary,
that share some of the required logic like clock and filters. This means
that the secondary CAN can't be used without the primary CAN.
Signed-off-by: Dario Binacchi <[email protected]>
Link: https://lore.kernel.org/all/[email protected]
Signed-off-by: Marc Kleine-Budde <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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The patch removes the legacy mode of displaying the ST logo and adopts
the approach introduced by the commit 284b08fb51b6 ("board: stm32mp1: add
splash screen with stmicroelectronics logo").
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
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The patch removes the hardcoded ST logo from the code, as it is no
longer used.
Signed-off-by: Dario Binacchi <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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The patch removes the legacy mode of displaying the ST logo and adopts
the approach introduced by the commit 284b08fb51b6 ("board: stm32mp1: add
splash screen with stmicroelectronics logo"). It was necessary to use a
specific logo for the stm32f746-disco board.
Furthermore, the previous version didn't properly center the logo, hiding
its upper part.
Signed-off-by: Dario Binacchi <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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The patch fixes the y-resolution, which was causing the creation of a
framebuffer larger than actually needed, resulting in memory waste.
Fixes: cc1b0e7b8e55b ("board: Add display to STM32F746 SoC discovery board")
Signed-off-by: Dario Binacchi <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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The patch applies the changes from Linux commit 10a970bc3ebfa ("ARM: dts:
stm32: support display on stm32f746-disco board") and removes the same
settings from stm32f746-disco-u-boot.dtsi.
Signed-off-by: Dario Binacchi <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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commit e4e724099f04072053cf411456e3e9aae48c4af1 Linux upstream.
In the schematics of document UM1907, the power supply for the micro SD
card is the same 3v3 voltage that is used to power other devices on the
board. By generalizing the name of the voltage regulator, it can be
referenced by other nodes in the device tree without creating
misunderstandings.
This patch is preparatory for future developments.
Signed-off-by: Dario Binacchi <[email protected]>
Signed-off-by: Alexandre Torgue <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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commit ba287d1a0137702a224b1f48673d529257b3c4bf Linux upstream.
Add pin configurations for using LTDC (LCD-tft Display Controller) on
stm32f746-disco board.
Signed-off-by: Dario Binacchi <[email protected]>
Reviewed-by: Raphaël Gallais-Pou <[email protected]>
Signed-off-by: Alexandre Torgue <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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The patch applies the changes from Linux commit 008ef8b3a1a00 ("Add LTDC
(Lcd-tft Display Controller) support") and removes the same settings
from stm32f746-disco-u-boot.dtsi.
Signed-off-by: Dario Binacchi <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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commit f0215440069c4fb12958d2d321e05faa2708a11d Linux upstream.
The patch adds support for touchscreen on the stm32f746-disco board.
Signed-off-by: Dario Binacchi <[email protected]>
Signed-off-by: Alexandre Torgue <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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commit 0637e66f8250c61f75042131fcb7f88ead2ad436 Linux upstream.
Add pin configurations for using i2c3 controller on stm32f7.
Signed-off-by: Dario Binacchi <[email protected]>
Signed-off-by: Alexandre Torgue <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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commit 7a5f349e592c254f3c1ac34665b6c3905576efc2 Linux upstream.
The patch replaces the number 12 with the appropriate numerical constant
already defined in the file stm32f7-rcc.h.
Signed-off-by: Dario Binacchi <[email protected]>
Signed-off-by: Alexandre Torgue <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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commit 0920ccdf41e3078a4dd2567eb905ea154bc826e6 Linux upstream.
Add support for bxcan (Basic eXtended CAN controller) to STM32F746. The
chip contains three CAN peripherals, CAN1 and CAN2 in dual peripheral
configuration and CAN3 in single peripheral configuration:
- Dual CAN peripheral configuration:
* CAN1: Primary bxCAN for managing the communication between a secondary
bxCAN and the 512-byte SRAM memory.
* CAN2: Secondary bxCAN with no direct access to the SRAM memory.
This means that the two bxCAN cells share the 512-byte SRAM memory and
CAN2 can't be used without enabling CAN1.
- Single CAN peripheral configuration:
* CAN3: Primary bxCAN with dedicated Memory Access Controller unit and
512-byte SRAM memory.
-------------------------------------------------------------------------
| features | CAN1 | CAN2 | CAN 3 |
-------------------------------------------------------------------------
| SRAM | 512-byte shared between CAN1 & CAN2 | 512-byte |
-------------------------------------------------------------------------
| Filters | 26 filters shared between CAN1 & CAN2 | 14 filters |
-------------------------------------------------------------------------
Signed-off-by: Dario Binacchi <[email protected]>
Link: https://lore.kernel.org/all/[email protected]
Signed-off-by: Marc Kleine-Budde <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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commit 011644249686f2675e142519cd59e81e04cfc231 Linux upstream.
Add pin configurations for using CAN controller on stm32f7.
Signed-off-by: Dario Binacchi <[email protected]>
Link: https://lore.kernel.org/all/[email protected]
Signed-off-by: Marc Kleine-Budde <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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commit 8f3ef556f8e1a670895f59ef3f01e4e26edd63e3 Linux upstream.
Add binding definition for CAN3 peripheral.
Signed-off-by: Dario Binacchi <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Lee Jones <[email protected]>
Reviewed-by: Patrice Chotard <[email protected]>
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Powering off the SiFive HiFive Unmatched board is supported both via the
SBI and GPIO sysreset drivers. See device-tree entry
compatible = "gpio-poweroff".
Enable the poweroff command.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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The Andes PLMT driver directly accesses the mtime MMIO region,
indicating its intended use in the M-mode boot stage. However,
since U-Boot proper (S-mode) also uses the PLMT driver, we need
to specifically mark the region as readable through PMPCFGx (or
S/U-mode read-only shared data region for Smepmp) in OpenSBI.
Granting permission for this case doesn't make sense. Instead,
we should use the generic RISC-V timer driver to read the mtime
through the TIME CSR. Therefore, we add the SPL_ANDES_PLMT_TIMER
config, which ensures that the PLMT driver is linked exclusively
against M-mode U-Boot or U-Boot SPL binaries.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Samuel Holland <[email protected]>
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Unify the memory layout for u-boot SPL mode
Add "CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS"
Signed-off-by: Randolph <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Modify "CONFIG_TARGET_AE350" to "CONFIG_TARGET_ANDES_AE350"
Signed-off-by: Randolph <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
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Most boards don't enable the pre-console buffer. So we will not see any
early messages. OpenSBI 1.3 provides us with the debug console extension
that can fill this gap.
For S-Mode U-Boot enable CONFIG_DEBUG_UART by default.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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A 16 bit aligned instruction should generated an exception if the C
extension is not available.
Provide an 'extension ialign16' command for testing exception handling.
For testing build qemu-riscv64_defconfig with CONFIG_RISCV_ISA_C=n
and run with
qemu-system-riscv64 -M virt -bios u-boot -nographic -cpu rv64,c=false
=> exception ialign16
Unhandled exception: Instruction address misaligned
EPC: 0000000087719138 RA: 0000000087719218 TVAL: 000000008771913e
EPC: 0000000080020138 RA: 0000000080020218 reloc adjusted
Code: 0113 0101 8067 0000 0113 ff01 3423 0011 (006f 0060)
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Eliminating the C extension on application processors is under
discussion.
Support emitting a compressed instruction. This will lead to an
illegal instruction exception if the C extension is not implemented.
For testing build qemu-riscv64_defconfig with CONFIG_RISCV_ISA_C=n
and run with
qemu-system-riscv64 -M virt -bios u-boot -nographic -cpu rv64,c=false
=> exception compressed
Unhandled exception: Illegal instruction
EPC: 0000000087731708 RA: 000000008773fe44 TVAL: 0000000000004501
EPC: 000000008001b708 RA: 0000000080029e44 reloc adjusted
Code: 0b93 0000 0493 0000 0993 0000 f06f ccdf (4501)
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Add timer driver in Starfive SoC. It is an timer that outside
of CPU core and inside Starfive SoC.
Signed-off-by: Kuan Lim Lee <[email protected]>
Reviewed-by: Wei Liang Lim <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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timer_get_boot_us function is required to record the boot stages as
us-based timestamp.
To get a micro-second time from a timer tick, this converts the
formula like below to avoid zero result of (tick / rate) part.
From: time(us) = (tick / rate) * 1000000
To : time(us) = (tick * 1000) / (rate / 1000)
Signed-off-by: Chanho Park <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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timer_get_boot_us function is required to record the boot stages as
us-based timestamp.
To get a micro-second time from a timer tick, this converts the
formula like below to avoid zero result of (tick / rate) part.
From: time(us) = (tick / rate) * 1000000
To : time(us) = (tick * 1000) / (rate / 1000)
Signed-off-by: Chanho Park <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Below warning can be occurred when CONFIG_BOOTSTAGE and
!CONFIG_SPL_BOOTSTAGE. It should be guarded by using CONFIG_IS_ENABLED
for SPL build.
arch/riscv/lib/bootm.c:46:9: warning: implicit declaration of
function 'bootstage_report'
46 | bootstage_report();
| ^~~~~~~~~~~~~~~~
| bootstage_error
Signed-off-by: Chanho Park <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-sh
- pinctrl re-sync for Renesas chips
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Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <[email protected]>
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Signed-off-by: Tom Rini <[email protected]>
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Signed-off-by: Tom Rini <[email protected]>
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Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <[email protected]>
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