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2023-07-21arm64: zynqmp: add pmu interrupt-affinityRadhey Shyam Pandey
Explicitly specify interrupt affinity to avoid HW perfevents need to guess. This avoids the following error upon linux boot: armv8-pmu pmu: hw perfevents: no interrupt-affinity property, guessing. Reported-by: John Toomey <[email protected]> Signed-off-by: Radhey Shyam Pandey <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/c2f55a10cf54c6004f5dfe2ea18bcb4cf04f5723.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Sync node name address with reg (mailbox)Michal Simek
Address in node name should match with the first reg property in DT. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/47bea10bbc3c88727c1fe839ff20e15a0c79c339.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Add L2 cache nodesRadhey Shyam Pandey
Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache node and let each CPU point to it. Reported-by: John Toomey <[email protected]> Signed-off-by: Radhey Shyam Pandey <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/c8dfabab12c97922aaad7fa91be0cbc7e4021528.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Fix usb reset over bootmode pins on zcu100Michal Simek
The commit a4180c369607 ("arm64: zynqmp: Add mode-pin GPIO controller DT node") added usb phy reset over bootmode pins by default on usb0 only. zcu100 is using usb0 as peripheral and usb1 as host. Unfortunately reset line is shared for both usb ulpi phys but usb_rst_b is connected to usb5744 hub which is used only in host mode. Especially this chip requires reset to operate properly that's why better assign gpio reset to usb1 instead of usb0. Without this change usb start crashed when runs. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/1ca80ec5bf7a595c03822f3e4e3683298205067a.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Cover K24 revB/1 SOMMichal Simek
Extend compatible versions for K24 SOM. Changes are not affecting SW behavior that's why all versions are compatible to each other. Describing all revisions is done by purpose because user space SW is reading compatible string for logic around DT overlays and bitstreams. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/92eba01ac316e58bd2d3508b0e63bbfafbedbb73.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Record compatible string for kv260 rev2Michal Simek
PCB rev2 compare to rev1 has some changes in PL side (IAS sensor AR1335 autofocus feature). PS side is completely unchanged. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/42f78dee8429eeac016d73de5c73af46fdaf4a98.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Assign TSU clock frequency for KV and KD boardsHarini Katakam
Set TSU clock frequency as 250MHz (minimum when running at 1G) on KV and KD carrier cards to allow PTP functionality. Signed-off-by: Harini Katakam <[email protected]> Reviewed-by: Radhey Shyam Pandey <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/4b758d503ef545e4d25d3930b0eb0793f1c415d2.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Increase reset assert time for TI SGMII PHYHarini Katakam
Increase reset assert time for TI SGMII PHY on KR260 CC starting 6.1 kernel. This PHY does not come out of reset with the existing 100us pulse width as per testing on multiple carrier cards. The reset is driven via a PCA9570 I2C expander. The expander driver was updated to an upstream version in 6.1 where gpio_chip _set was optimized. Delays in earlier kernels may have masked this issue. This is a safe workaround value for assert pulse width before the discussions are resolved with TI. Signed-off-by: Harini Katakam <[email protected]> Reviewed-by: Radhey Shyam Pandey <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/8fb9f17d43a43ef504c9f29006cd686cce8ac98b.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Fix gpio comment about No of gpiosMichal Simek
There are total 174 gpios but from 0 - 173 that's why fix comment to reflect it. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/c7e94b334e7dd6297e0d3a36a6a3d04bd7e9e967.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Assign TSU clock frequency for KR260Harini Katakam
Set TSU clock frequency as 250MHz (minimum when running at 1G) on KR260 CC to allow PTP functionality. Signed-off-by: Harini Katakam <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/d065b5c2c6450910bf57d104d65946111493caaa.1688992653.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Update MALI 400 interrupt and clock namesParth Gajjar
Motivation for the commit is to utilize the upstream community device tree so that the either modified ARM Mali 400 driver or upstream lima driver can be used. Signed-off-by: Parth Gajjar <[email protected]> Signed-off-by: Vishal Sagar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/89d046a9da5638e8b4918f80f3245d73ea46f99f.1688992653.git.michal.simek@amd.com
2023-07-21xilinx: dts: Fix open drain warning on Zynq, ZynqMP and VersalManikanta Guntupalli
Fix for below open drain warning on Zynq, ZynqMP and Versal reported by Linux. "enforced open drain please flag it properly in DT/ACPI DSDT/board file." Signed-off-by: Manikanta Guntupalli <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/056b6f60f89fa2addb762669b80640cd5b31b001.1688992653.git.michal.simek@amd.com
2023-07-21arm: xilinx: Setting default i2c clock frequency to 400kHzVaralaxmi Bingi
Setting default i2c clock frequency for Zynq and ZynqMP to maximum rate of 400kHz. Current default value is 100kHz. Signed-off-by: Varalaxmi Bingi <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/fb46fe911a68b79c8e4d150ca90c4e94eb5fb9e1.1688992653.git.michal.simek@amd.com
2023-07-21mtd: Add missing MTD dependency for cfi_mtdMichal Simek
cfi_mtd requires add_mtd_device() which is available only when MTD is enabled that's why record this dependency. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/76ae01ce2b2c988758b69e0f0cdcc21bf301c01e.1688472227.git.michal.simek@amd.com
2023-07-21mmc: zynq_sdhci: Dll reset only for ZynqMP platformAshok Reddy Soma
Dll reset is needed only for ZynqMP platforms, add condition in tuning to call arasan_zynqmp_dll_reset() just for ZynqMP platforms. On other platforms like Versal NET, If this condition is not added, we see PLM error messages when dll reset smc is called. Signed-off-by: Ashok Reddy Soma <[email protected]> Reviewed-by: Jaehoon Chung <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/d673ff3bdc5c236a7f0403c920e719684abd6059.1688991117.git.michal.simek@amd.com
2023-07-21arm64: zynqmp: Switch to amd.com emailsMichal Simek
Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
2023-07-21xilinx: zynq: Enable fdt apply utility for zynqRaju Kumar Pothuraju
Enables the FDT library (libfdt) overlay support for zynq platforms to be able to use fdt apply command. Signed-off-by: Raju Kumar Pothuraju <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/ab26dd186fb752b3d607e6160ae5baf6661d5de7.1688990179.git.michal.simek@amd.com
2023-07-21xilinx: Consolidate zynqmp_mmio_read/write in zynqmp_firmware.hMichal Simek
zynqmp_mmio_read/write() are firmware provided hooks that's why use only zynqmp_firmware.h for function declaration. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/e7489556f9e447c737a578c169d7e1e43586a273.1687524706.git.michal.simek@amd.com
2023-07-21xilinx: versal-net: Add mini eMMC 5.1 configurationAshok Reddy Soma
Add support for Versal NET mini eMMC 5.1 configuration. Add device tree and defconfig. Signed-off-by: Ashok Reddy Soma <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-07-21xilinx: versal-net: Add mini ospi configurationAshok Reddy Soma
Add support for Versal NET mini Octal SPI flash configuration. This runs from onchip memory, so it has to be compact. Hence only Octal SPI related settings are enabled. Signed-off-by: Ashok Reddy Soma <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-07-21xilinx: versal-net: Add mini qspi configurationAshok Reddy Soma
Add support for Versal NET mini Quad SPI flash configuration. This runs from onchip memory, so it has to be compact. Hence only Quad SPI related settings are enabled. Signed-off-by: Ashok Reddy Soma <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-07-21cadence_qspi: Enable flash reset for Versal NET platformAshok Reddy Soma
Enable flash reset functionality for Versal NET platform. In cadence_qspi.c there is weak function defined for reset, hence remove the check for config, so that it will work for Versal and Versal NET platforms. Add register defines in Versal NET hardware.h for mini U-Boot flash reset. Add read_delay initialization for Versal NET also. Signed-off-by: Ashok Reddy Soma <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-07-21net: zynq_gem: Don't hardcode the MDC clock divisorVenkatesh Yadav Abbarapu
As per spec MDC must not exceed 2.5MHz, read the pclk clock from the device tree and update the MDC clock divisor. GEM devices support larger clock divisors and have a different range of divisors. Program the MDIO clock divisors based on the clock rate of the pclk clock. Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-07-21arm64: versal-net: spi: Update boot sequence dynamicallyAshok Reddy Soma
Currently xspi0 is used for all spi boot modes, it means it will use "sf probe 0 0 0" for all spi's irrespective of which node it is wired. Get boot sequence from dev_seq() and update boot command for xspi dynamically. As a result bootcmd for spi is updated as below when two instances of spi are present in DT node. bootcmd_xspi0=devnum_xspi=0; run xspi_boot bootcmd_xspi1=devnum_xspi=1; run xspi_boot xspi_boot=sf probe $devnum_xspi:0 0 0 && sf read $scriptaddr $script_offset_f $script_size_f && echo XSPI: Trying to boot script at ${scriptaddr} && source ${scriptaddr}; echo XSPI: SCRIPT FAILED: continuing...; Signed-off-by: Ashok Reddy Soma <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-07-21xilinx: zynq: Add the missing function prototypesAlgapally Santosh Sagar
Add the missing prototypes for the functions pointed by the below sparse warnings warning: no previous prototype for 'set_dfu_alt_info' [-Wmissing-prototypes] warning: no previous prototype for 'board_debug_uart_init' [-Wmissing-prototypes] Signed-off-by: Algapally Santosh Sagar <[email protected]> Signed-off-by: Ashok Reddy Soma <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-07-21arm: zynq: Pass the missing argument type in function definitionAlgapally Santosh Sagar
Pass missing argument type in the function definition to fix the sparse warning, warning: old-style function definition [-Wold-style-definition] Signed-off-by: Algapally Santosh Sagar <[email protected]> Signed-off-by: Ashok Reddy Soma <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-07-21mtd: nand: zynq_nand: Change datatype of status and ecc_status to intAlgapally Santosh Sagar
status and ecc_status are of unsigned type where they are compared for negative value. This is pointed by below sparse warning. Change datatype to int to fix this. warning: comparison of unsigned expression in '< 0' is always false [-Wtype-limits] Signed-off-by: Algapally Santosh Sagar <[email protected]> Reviewed-by: Michael Trimarchi <[email protected]> Signed-off-by: Ashok Reddy Soma <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-07-21spi: zynq_qspi: Add missing prototype for zynq_qspi_mem_exec_opAlgapally Santosh Sagar
Add missing prototype to fix the sparse warning, warning: no previous prototype for 'zynq_qspi_mem_exec_op' [-Wmissing-prototypes]. Signed-off-by: Algapally Santosh Sagar <[email protected]> Signed-off-by: Ashok Reddy Soma <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-07-21xilinx: zynq: Add missing prototype for zynqmp_mmio_writeAlgapally Santosh Sagar
Add missing prototype to fix the sparse warning, warning: no previous prototype for 'zynqmp_mmio_write' [-Wmissing-prototypes]. Signed-off-by: Algapally Santosh Sagar <[email protected]> Signed-off-by: Ashok Reddy Soma <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-07-21spi: xilinx_spi: Add missing prototype for xilinx_qspi_mem_exec_opAlgapally Santosh Sagar
Add missing prototype to fix the below sparse warning warning: no previous prototype for 'xilinx_qspi_mem_exec_op' [-Wmissing-prototypes] Signed-off-by: Algapally Santosh Sagar <[email protected]> Signed-off-by: Ashok Reddy Soma <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-07-21arm64: zynqmp: Fix the memory node for k26/k24 kria som boardsSharath Kumar Dasari
PMUFW requires top 1MB of the lower DDR memory reserved for its operation, this is missing in k26/k24 sm static dts files because of which U-Boot throws warning messages "efi_free_pool: illegal free" as EFI puts some code to that space which shouldn't happen. Signed-off-by: Sharath Kumar Dasari <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/57452d16df2d48593de206bebf877d2c2cfe7bf1.1685966389.git.michal.simek@amd.com
2023-07-21watchdog: versal: Use new compatible xlnx,versal-wwdtMichal Simek
DT binding has been approved that's why use new compatible string. The old one is mark as deprecated and should be removed after some releases. Link: https://lore.kernel.org/r/[email protected]/ Reviewed-by: Stefan Roese <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/6e78d0d2e21f2f9e7f8f448bb8e0d27ced4de7d3.1686655339.git.michal.simek@amd.com
2023-07-20Merge tag 'dm-pull-20jul23' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-dm binman mkimage and template enhancements misc fixes
2023-07-20Merge branch '2023-07-20-assorted-CI-updates'Tom Rini
- Move to gcc-13.1 and QEMU 8.0.3 in CI. This also lets us move to a kernel.org toolchain for arc as well.
2023-07-21usb: cdns3: gadget: Configure speed in udc_startRavi Gunasekaran
When one of the functions does not support super speed, the composite driver forces the gadget to high speed. But the speed is never configured in the cdns3 gadget driver. So configure the speed in cdns3_gadget_udc_start just like in the kernel. Signed-off-by: Ravi Gunasekaran <[email protected]> Reviewed-by: Marek Vasut <[email protected]>
2023-07-21usb: ehci-mx6: remove unnecessary regulator enable from probeTim Harvey
Remove the regulator_set_enable() call from device probe which resolves a regulator imbalance. This is unnecessary as regulator_set_enable() will be called when ehci_register calls the init_after_reset hook. Suggested-by: Marek Vasut <[email protected]> Signed-off-by: Tim Harvey <[email protected]>
2023-07-21sunxi: H616: add LPDDR3 DRAM supportMikhail Kalashnikov
The H616 SoC has support for several types of DRAM: DDR3, LPDDR3, DDR4 and LPDDR4. At the moment, the driver only supports DDR3 memory. Let's extend the driver to support the LPDDR3 memory. All "magic" values obtained from the boot0. Signed-off-by: Mikhail Kalashnikov <[email protected]> Acked-by: Andre Przywara <[email protected]> Signed-off-by: Andre Przywara <[email protected]>
2023-07-21sunxi: H616: add DRAM type selectionMikhail Kalashnikov
Allwinner H616 SoC supports several types of DRAM memory. To further integrate other types of memory, we need to add this delimitation. Signed-off-by: Mikhail Kalashnikov <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Signed-off-by: Andre Przywara <[email protected]>
2023-07-21sunxi: H616: dram: split struct dram_paraAndre Przywara
Currently there is one DRAM parameter struct for the Allwinner H616 DRAM "driver". It contains many fields that are compile time constants (set by Kconfig variables), though there are also some fields that are probed and changed over the runtime of the DRAM initialisation. Because of this mixture, the compiler cannot properly optimise the code for size, as it does not consider constant propagation in its full potential. Help the compiler out by splitting that structure into two: one that only contains values known at compile time, and another one where the values will actually change. The former can then be declared "const", which will let the compiler fold its values directly into the code using it. We also add "const" tags for some new "struct dram_config" pointers, to further increase code optimisation. To help the compiler optimise the code further, the definition of the now "const struct dram_para" has to happen at a file-global level, so move that part out of sunxi_dram_init(). That results in quite some code savings (almost 2KB), and helps to keep the code small with the LPDDR3 support added later. Signed-off-by: Andre Przywara <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]>
2023-07-21sunxi: H616: dram: const-ify DRAM function parametersAndre Przywara
There are quite some functions in the Allwinner H616 DRAM "driver", some of them actually change the parameters in the structure passed to them, but many are actually not. To increase the optimisation potential for the code, mark those functions that just read members of the passed dram_para struct as "const". This in itself does not decrease the code size, but lays the groundwork for future changes doing so. Signed-off-by: Andre Przywara <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]>
2023-07-21sunxi: dram: make MBUS configuration functions staticAndre Przywara
The usage of the C keyword "inline" seems to be a common misunderstanding: it's a *hint* only, and modern compilers will inline (or not) functions based on their own judgement and provided compiler options. So while marking functions as "inline" does not do much, missing the "static" keyword will force to compiler to spell out a version of the function for potential external callers, which actually increases the code size (though hopefully the linker will drop the function). Change the "inline" attribute for the mbus_configure_port() functions in some Allwinner DRAM drivers to "static", so that the explicit version can actually be dropped from the object file, reducing the code size. "static inline" has a use case in header files, where it avoids a warning if a .c file including this header does not use the particular function. In a .c file itself "static inline" is not useful otherwise, so just use static here as well. Signed-off-by: Andre Przywara <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]>
2023-07-21sunxi: H616: enable USB support for H616 boardsAndre Przywara
Now that the PHY driver supports the H616 USB PHY, we can enable USB support for the two H616 boards. As the OrangePi Zero2 has a USB-C port hard-wired to peripheral mode, let's enable USB gadget mode for port 0, so people can use fastboot, ethernet or mass storage functionality. Signed-off-by: Andre Przywara <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]>
2023-07-21phy: sun4i: Add H616 USB PHY supportAndre Przywara
Now that the Allwinner USB PHY driver supports the H616 quirk, let's enable support for USB ports on that SoC. We connect the compatible string to a new struct describing the SoCs USB PHY properties, and unblock the PHY driver selection in Kconfig. A later patch will enable USB support in the H616 boards' defconfigs. Signed-off-by: Andre Przywara <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]>
2023-07-21phy: sun4i-usb: Add H616 USB PHY quirk supportAndre Przywara
The H616 USB PHY is some kind of special snowflake: Only port2 works out of the box, but all other ports need some help from this port2 to work correctly: The CLK_BUS_PHY2 and RST_USB_PHY2 clock and reset need to be enabled, and the SIDDQ bit in the PMU PHY control register needs to be cleared. For this register to be accessible, CLK_BUS_ECHI2 needs to be ungated. Don't ask .... Follow the respective Linux patch (b45c6d80325b) and add a quirk bit, triggering the special sequence as outlined above, for PHYs other than PHY2: ungate this one special clock, and clear the SIDDQ bit. We also pick the clock and reset from PHY2 and enable them as well. Signed-off-by: Andre Przywara <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]>
2023-07-21phy: sun4i-usb: Replace types with explicit quirk flagsAndre Przywara
So far we were assigning some crude "type" (SoC name, really) to each Allwinner USB PHY model, then guarding certain quirks based on this. This does not only look weird, but gets more or more cumbersome to maintain. Remove the bogus type names altogether, instead introduce flags for each quirk, and explicitly check for them. This improves readability, and simplifies future extensions. Port of Linux patch 8dd256bae653. Signed-off-by: Andre Przywara <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]>
2023-07-21sunxi: Kconfig: rework PHY_USB_SUN4I selectionAndre Przywara
At the moment we use "select" in each Allwinner SoC's Kconfig section to include the USB PHY driver in the build. This means it cannot be disabled via Kconfig, although USB is not really a strictly required core functionality, and a particular board might not even include USB ports. Rework the Kconfig part by removing the "select" lines for each SoC's section, and instead letting it default to "y" in the PHY driver section itself. We use "depends on !" to exclude the few SoCs we don't support (yet). The Allwinner V3s does not enable USB (PHY) support at the moment, even though it should work: let the PHY default to "n" to keep the current behaviour. Also the MUSB USB driver directly calls some functions from the PHY driver, so let the former depend on the PHY driver. Signed-off-by: Andre Przywara <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Tested-by: Sam Edwards <[email protected]>
2023-07-21phy: sun4i-usb: add Allwinner F1C100s supportAndre Przywara
The Allwinner F1C100s implements a single USB PHY, connected to its MUSB OTG controller. The USB PHY is of the simpler, older type (like the A10), the only real difference is that it's indeed only one PHY. Add a struct describing those F1C100s USB PHY properties, and connect it to the new compatible string. Signed-off-by: Andre Przywara <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]>
2023-07-21phy: sun4i-usb: Fix of_xlate() argument checkAndre Przywara
In its of_xlate() function, the Allwinner USB PHY driver compares the args_count variable against the number of implemented USB PHYs, although this is the *number of arguments* to the DT phandle property. Per the DT binding for this PHY device, this number is always one, so this check will always fail if the particular SoC implements exactly one USB PHY. So far this affected only the V3s (which has USB support disabled), but the F1C100s also sports one PHY only. Fix that check to compare args_count against exactly 1, and the args[0] content (requested PHY number) against the number of implemented PHYs. This fixes USB operation on the Allwinner V3s and allows to enable USB on the Allwinner F1C100s SoC. Signed-off-by: Andre Przywara <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]>
2023-07-20binman: Reduce state.SetInt and bintool cmd to debug levelSimon Glass
These are not very important message. Change them to use the 'debug' level instead of 'detail'. Signed-off-by: Simon Glass <[email protected]>
2023-07-20binman: Support writing symbols inside a mkimage imageSimon Glass
Add support for writing symbols and determining the assumed position of binaries inside a mkimage image. This is useful as an example for other entry types which might want to do the same thing. Signed-off-by: Simon Glass <[email protected]>
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