| Age | Commit message (Collapse) | Author |
|---|
|
Mips essentially duplicates the content of asm-generic/unaligned.h, so use
that file directly instead.
Signed-off-by: Jens Wiklander <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
|
|
Sh essentially duplicates the content of asm-generic/unaligned.h, so use
that file directly instead.
Signed-off-by: Jens Wiklander <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
|
|
Arm duplicates the content of asm-generic/unaligned.h, so use that file
directly instead.
Signed-off-by: Jens Wiklander <[email protected]>
Reviewed-by: Ilias Apalodimas <[email protected]>
|
|
- Correct some header double-inclusion guards and remove some dead (or
in the case of ti816x, unmaintained) code.
|
|
As part of various code clean-ups we have on occasion missed removing
unused header files. None of these files are referenced anywhere else
at this point.
Signed-off-by: Tom Rini <[email protected]>
|
|
Commit 11232139e399 ("nds32: Remove the architecture") removed the nds32
architecture, and with it the last user of the Faraday AHB controller
header file.
Consequently remove that header file as well.
This was found because the inclusion guard was misspelled.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
|
|
It seems like the header inclusion guard for the Exynos pinctrl header
was misspelled.
Make the preprocessor symbol for the #ifndef and #define lines the
same, so that the double inclusion protection works as expected.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
|
|
It seems like the header inclusion guard for some Freescale crosspoint
switch header was misspelled.
Make the preprocessor symbol for the #ifndef and #define lines the
same, so that the double inclusion protection works as expected.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
|
|
It seems like the header inclusion guard for some Uniphier DDR PHY
header was misspelled.
Make the preprocessor symbol for the #ifndef and #define lines the
same, so that the double inclusion protection works as expected.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
|
|
It seems like the header inclusion guards for some IMX related headers
were misspelled or got out of sync.
Make the preprocessor symbols for the #ifndef and #define lines the
same, so that the double inclusion protection works as expected.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
|
|
This platform is currently unmaintained and untested, so remove it.
Further, as it is the only TI816X SoC example, remove related files as
well.
Signed-off-by: Tom Rini <[email protected]>
|
|
- Fixes for some TI K3 platforms and merge the Apple M2 support I had
intended to pick up earlier.
|
|
The PCIe controller on the M2 Pro/Max is different from the one
found on earlier Apple SoCs. Some registers moved and te meaning
of the bits in some other registers changed. But they are still
similar enough to handle both controllers in the same driver.
Signed-off-by: Mark Kettenis <[email protected]>
|
|
Apple's M2 Pro/Max SoC are somewhat similar to the M1 Pro/Max but
need a tweaked memory map. USB, NVMe, UART and WDT are working
with the existing drivers.
Signed-off-by: Mark Kettenis <[email protected]>
|
|
K3 GP devices allows booting the secure binaries on them by bypassing
the x509 header on them.
ATF and OPTEE firewalling required the rproc_load to be called before
authentication. This change caused the failure for GP devices that
strips off the headers. The boot vector had been set before the headers
were stripped off causing the runtime stripping to fail and stripping
becoming in-effective.
Separate out the secure binary check on GP/HS devices so that the
boot_vector could be stripped before calling rproc_load. This allows
keeping the authentication later when the cluster is on along with
allowing the stripping of the binaries in case of gp devices.
Fixes: 1e00e9be62e5 ("arm: mach-k3: common: re-locate authentication for atf/optee")
Signed-off-by: Manorit Chawdhry <[email protected]>
|
|
When booting with HS silicon, the system firmware image is 278270, which
is slightly larger than currently allocated amount.
This can cause unexpected behavior if this overlap interferes with other
things in memory, so increase this with a slightly margin added as well
to avoid any boot issues that can appear after system firmware gets
loaded.
Signed-off-by: Dave Gerlach <[email protected]>
Signed-off-by: Tero Kristo <[email protected]>
Signed-off-by: Manorit Chawdhry <[email protected]>
Reviewed-by: Dhruva Gole <[email protected]>
|
|
In non-combined boot flow for K3, all the firewalls are locked by default
until sysfw comes up. Rom configures some of the firewall for its usage
along with the SRAM for R5 but the PSRAM region is still locked.
The K3 MCU Scratchpad for j721e was set to a PSRAM region triggering the
firewall exception before sysfw came up. The exception started happening
after adding multi dtb support that accesses the scratchpad for reading
EEPROM contents.
The commit changes R5 MCU scratchpad for j721e to an SRAM region.
Old Map:
┌─────────────────────────────────────┐ 0x41c00000
│ SPL │
├─────────────────────────────────────┤ 0x41c40000 (approx)
│ STACK │
├─────────────────────────────────────┤ 0x41c85b20
│ Global data │
│ sizeof(struct global_data) = 0xd8 │
├─────────────────────────────────────┤ gd->malloc_base = 0x41c85bfc
│ HEAP │
│ CONFIG_SYS_MALLOC_F_LEN = 0x70000 │
├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR
│ SPL BSS │ (0x41cf5bfc)
│ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │
└─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
(0x41cffbfc)
New Map:
┌─────────────────────────────────────┐ 0x41c00000
│ SPL │
├─────────────────────────────────────┤ 0x41c40000 (approx)
│ EMPTY │
├─────────────────────────────────────┤ 0x41c81920
│ STACK │
│ SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 │
├─────────────────────────────────────┤ 0x41c85920
│ Global data │
│ sizeof(struct global_data) = 0xd8 │
├─────────────────────────────────────┤ gd->malloc_base = 0x41c859f0
│ HEAP │
│ CONFIG_SYS_MALLOC_F_LEN = 0x70000 │
├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR
│ SPL BSS │ (0x41cf59f0)
│ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │
├─────────────────────────────────────┤ 0x41cff9fc
│ NEW MCU SCRATCHPAD │
│ SYS_K3_MCU_SCRATCHPAD_SIZE = 0x200 │
└─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX
(0x41cffbfc)
Fixes: ab977c8b91b4 ("configs: j721s2_evm_r5: Enable support for building multiple dtbs into FIT")
Signed-off-by: Manorit Chawdhry <[email protected]>
[[email protected]: SRAM allocation addressing diagram]
Signed-off-by: Neha Francis <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
Reviewed-by: Kamlesh Gurudasani <[email protected]>
|
|
K3 devices have runtime type board detection. Make the default defconfig
include the secure configuration. Then remove the HS specific config.
Non-HS devices will continue to boot due to runtime device type detection.
If TI_SECURE_DEV_PKG is not set the build will emit warnings, for non-HS
devices these can be ignored.
Reviewed-by: Bryan Brattlof <[email protected]>
Reviewed-by: Neha Malcom Francis <[email protected]>
Acked-by: Andrew Davis <[email protected]>
Signed-off-by: Manorit Chawdhry <[email protected]>
|
|
When building for secure devices using non-buildman based image generation
the signed tispl.bin file is called tispl.bin_HS. Also build the unsigned
tispl.bin file as expected.
Signed-off-by: Andrew Davis <[email protected]>
Signed-off-by: Manorit Chawdhry <[email protected]>
|
|
Signed-off-by: Tom Rini <[email protected]>
|
|
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <[email protected]>
|
|
https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20230525
-------------------
- i.MX93 series
- Fixes
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16412
|
|
Add trivial driver for the MXS AUART IP. This is the other UART IP
present in i.MX23 and i.MX28, used to drive the non-DUART ports.
Signed-off-by: Marek Vasut <[email protected]>
|
|
Enable sysreset for i.MX93 EVK.
Signed-off-by: Peng Fan <[email protected]>
|
|
Update DDR timing file generated by DDR Config Tool
1. Dynamic refresh rate is set by default
2. The 3rd freq will be 625MTS based on power and performance better than 100MTS.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
To avoid using static setting for ECC enabled DDR size, switch
to calculate DDR size from DDRC setting
Signed-off-by: Ye Li <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Jacky Bai <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
The rank setting flow should be updated to support multi
fsp config.
Signed-off-by: Jacky Bai <[email protected]>
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Update the DDR init flow for multi-setpoint support on i.MX93. A new
fsp_cfg struct need to be added in the timing file to store the diff
part of the DDRC and DRAM MR register for each setpoint.
Signed-off-by: Jacky Bai <[email protected]>
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Add 625M bypass clock that may be used DRAM 625M
bypass mode support.
Signed-off-by: Jacky Bai <[email protected]>
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
change the ddr saved info to the last 16KB of the OCRAM.
Signed-off-by: Jacky Bai <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
As the ddr timing info will be saved at the last 16KB of
the OCRAM, spl stack & bss base should be updated to avoid
conflict.
Signed-off-by: Peng Fan <[email protected]>
|
|
According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap
specification does not include the Critical Delay Difference (CDD) to
properly define the required rank-to-rank read command spacing after
executing PHY training firmware.
Following the errata workaround, at the end of data training, we get
all CDD values through the MessageBlock, then re-configure the DDRC
timing of WWT/WRT/RRT/RWT with comparing MAX CDD values.
Signed-off-by: Ye Li <[email protected]>
Acked-by: Peng Fan <[email protected]>
|
|
Add tmu nodes and thermal zone
Signed-off-by: Peng Fan <[email protected]>
|
|
Sync device tree with next-20230426
Signed-off-by: Peng Fan <[email protected]>
|
|
Currently bootaux only supports to boot M33 core from TCM. Since ATF
has changed to use x2 parameter for M33 image address, update the
bootaux command to use input address, so we can support boot from
any possilbe address like TCM, DDR, Flexspi NOR.
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Add a static u-boot config for i.MX93 low drive mode support. When
low drive mode is enabled, VDD_SOC is set to 0.75V. Bus clocks,
A55 core clock (900Mhz), DDR clock (1866MTS), and some peripherals
clocks (USDHC/FLEXSPI/PDM/DISP_PIX/CAM_PIX) must decrease to meet
max frequencies in low drive mode.
Also set standby voltage for buck1
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
There is no need to save gd with using the generic rom api function, so
simplify code.
Signed-off-by: Peng Fan <[email protected]>
|
|
The end brace should be in a new line
Signed-off-by: Peng Fan <[email protected]>
|
|
According to datasheet, iMX93 has fused parts with CORE1 or NPU or
both disabled. So update code to support it, the kernel device tree
runtime update will be added in future patches.
Signed-off-by: Peng Fan <[email protected]>
|
|
Config the A55 alt root clock to 500MHz(LD mode frequency)
by default. Normally, this clock root is only used as an
intermediate clock soure for A55 core/dsu when change the
ARM PLL frequency.
Signed-off-by: Peng Fan <[email protected]>
|
|
Add CONFIG_IMX9_LOW_DRIVE_MODE in imx9 clk, later we will
add board support
Signed-off-by: Peng Fan <[email protected]>
|
|
The HW_CTRL_SEL should be cleared when configuring PLL to avoid
potential glitch
Reviewed-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
|
Get the chip's market segment and speed grading from fuse and print
them in boot log as other i.MX series.
Signed-off-by: Peng Fan <[email protected]>
|
|
Support print reset cause. Since SRSR is not accessible from non-secure
world, so first save it to grp0, then read it in non-secure world.
Signed-off-by: Peng Fan <[email protected]>
|
|
There will be build error if CONFIG_SYSRESET is enabled, so guard
the reset_cpu with condition check here
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
|
|
Without this config, there is boot error: Error binding ulp_wdt driver
Signed-off-by: Peng Fan <[email protected]>
|
|
Select thermal config to print current temperature
Signed-off-by: Peng Fan <[email protected]>
|
|
Drop unused macro
Signed-off-by: Peng Fan <[email protected]>
|
|
select CONFIG_CPU_IMX to display cpu info
Signed-off-by: Peng Fan <[email protected]>
|
|
The MAC addresses are hard coded for bring up. Change it to support
reading from fuse.
Reviewed-by: Jacky Bai <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
|
