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The CN9130 SoC (an ARMADA 8K type) has both a NAND Flash Controller and
a generic local bus controller (Device Bus Controller) that share common
pins.
With a board design that incorporates both a NAND flash and uses
the Device Bus (in our case for an SRAM) accessing the Device Bus device
fails unless the NfArbiterEn bit is set. Setting the bit enables
arbitration between the Device Bus and the NAND flash.
Since there is no obvious downside in enabling this for designs that
don't require arbitration, we always enable it.
Signed-off-by: Chris Packham <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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The NAND flash controller (NFC) on the AC5/AC5X SoC is the same as
the NFC used on other Marvell SoCs. It does have the additional
restriction of only supporting SDR timing modes up to 3.
Signed-off-by: Chris Packham <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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The NF_CLK for the AC5 SoC runs at 400MHz. There's no strapping
or gating require so just add a mvebu_get_nand_clock() that
returns this value.
Signed-off-by: Chris Packham <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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The AC5/AC5X SoC has a NAND flash controller. Add this to the
SoC device tree.
Signed-off-by: Chris Packham <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Add gpio-fan in the DTS and enable the GPIO in board file to start the fan
during boot.
Note that this patch depends on
https://patchwork.ozlabs.org/project/uboot/patch/[email protected]/
Signed-off-by: Tony Dinh <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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- Update the Thecus N2350 DTS to conform with latest device-tree binding
and styles.
- Correct typo in mdio node.
Signed-off-by: Tony Dinh <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Reviewed-by: Pali Rohár <[email protected]>
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- Add ethernet driver for StarFive JH7110 SoC
- Add ACLINT mtimer and mswi devices support
- Add Lichee PI 4A board
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Reviewed-by: Wei Fu <[email protected]>
Signed-off-by: Yixun Lan <[email protected]>
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Add basic config for Sipeed Lichee PI 4A board which make it capable of
booting into serial console.
Reviewed-by: Wei Fu <[email protected]>
Signed-off-by: Yixun Lan <[email protected]>
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Only add basic support for CPU, PLIC UART and Timer.
Reviewed-by: Wei Fu <[email protected]>
Signed-off-by: Yixun Lan <[email protected]>
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Add support for Sipeed's Lichee Pi 4A board which based on T-HEAD's
TH1520 SoC, only minimal device tree and serial console are enabled,
so it's capable of chain booting from T-HEAD's vendor u-boot.
Reviewed-by: Wei Fu <[email protected]>
Signed-off-by: Yixun Lan <[email protected]>
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As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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This RISC-V ACLINT specification [1] defines a set of memory mapped
devices which provide inter-processor interrupts (IPI) and timer
functionalities for each HART on a multi-HART RISC-V platform.
The RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, however the device tree binding
is a new one. This change updates the sifive clint ipi driver to
support ACLINT mswi device, by checking the per-driver data field of
the ACLINT mtimer driver to determine whether a syscon based approach
needs to be taken to get the base address of the ACLINT mswi device.
[1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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This RISC-V ACLINT specification [1] defines a set of memory mapped
devices which provide inter-processor interrupts (IPI) and timer
functionalities for each HART on a multi-HART RISC-V platform.
The RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, however the device tree binding
is a new one. This change updates the sifive clint timer driver to
support ACLINT mtimer device, using a per-driver data field to hold
the mtimer offset to the base address encoded in the mtimer node.
[1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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The main difference between StarFive VisionFive 2 1.2A and 1.3B is gmac.
You can read the PCB version of the current board by
get_pcb_revision_from_eeprom(), and then dynamically configure the
difference of gmac in spl_perform_fixups() according to different PCB
versions, so that one DT and one defconfig can support both 1.2A and
1.3B versions, which is more user-friendly.
Signed-off-by: Yanhong Wang <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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StarFive VisionFive 2 has two versions, 1.2A and 1.3B, each version of
DDR capacity includes 2G/4G/8G, a DT can not support multiple
capacities, so the capacity size information is recorded to EEPROM, when
DDR initialization required capacity size information is read from
EEPROM.
If there is no information in EEPROM, it is initialized with the default
size defined in DT.
Signed-off-by: Yanhong Wang <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Enabled ID_EEPROM and I2C configuration for StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang <[email protected]>
Reviewed-By: Leo Yu-Chi Linag <[email protected]>
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Add support "atmel,24c04" eeprom for StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Enabled ID_EEPROM configuration for StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Enable DWC_ETH_QOS and PHY_MOTORCOMM configuration to support ethernet
function for StarFive VisionFive 2 board,including versions 1.2A and
1.3B.
Signed-off-by: Yanhong Wang <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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The defconfig file name for StarFive VisionFive2 has been changed, and
the documentation description has also changed.
Signed-off-by: Yanhong Wang <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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The difference between 1.2A and 1.3B is dynamically configured according
to the PCB version, and there is no difference on the board device tree,
so the same DT file can be used.
Signed-off-by: Yanhong Wang <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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Add ethernet device tree node to support StarFive ethernet driver for
the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
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The StarFive ETHQOS hardware has its own clock and reset,so add a
corresponding glue driver to configure them.
Signed-off-by: Yanhong Wang <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have
verified the driver on StarFive VisionFive2 board.
Signed-off-by: Yanhong Wang <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request efi-2023-07-rc7
Documentation:
* Fix links to Linux kernel documentation
UEFI:
* Fix memory leak in efidebug dh subcommand
* Fix underflow when calculating remaining variable store size
* Increase default variable store size to 64 KiB
* mkeficapsule: fix efi_firmware_management_capsule_header data type
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When tagging and releasing v2023.07 I forgot to drop the -rc6 tag. For
regular use, I've made a v2023.07.01 tag, but for here we can just drop
the -rc6 tag.
Signed-off-by: Tom Rini <[email protected]>
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The Gateworks imx8mp-venice-gw7905-2x consists of a SOM + baseboard.
The GW702x SOM contains the following:
- i.MX8M Plus SoC
- LPDDR4 memory
- eMMC Boot device
- Gateworks System Controller (GSC) with integrated EEPROM, button
controller, and ADC's
- PMIC
- SOM connector providing:
- eQoS GbE MII
- 1x SPI
- 2x I2C
- 4x UART
- 2x USB 3.0
- 1x PCI
- 1x SDIO (4-bit 3.3V)
- 1x SDIO (4-bit 3.3V/1.8V)
- GPIO
The GW7905 Baseboard contains the following:
- GPS
- microSD
- off-board I/O connector with I2C, SPI, GPIO
- EERPOM
- PCIe clock generator
- 1x full-length miniPCIe socket with PCI/USB3 (via mux) and USB2.0
- 1x half-length miniPCIe socket with USB2.0 and USB3.0
- USB 3.0 HUB
- USB Type-C with USB PD Sink capability and peripheral support
- USB Type-C with USB 3.0 host support
Signed-off-by: Tim Harvey <[email protected]>
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Display dram speed during configuration.
Signed-off-by: Tim Harvey <[email protected]>
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When booting from USB (SDP) setup firmware-update environment
for emmc device.
Signed-off-by: Tim Harvey <[email protected]>
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With variou README files migrated to rst, add them to the
MAINTAINER file for Beacon.
Signed-off-by: Adam Ford <[email protected]>
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Since U-Boot builds HTML documentation, migrate the contents
of the README file to an rst file which can generate the
proper outputs.
Signed-off-by: Adam Ford <[email protected]>
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Instead of cluttering up a header file with a bunch of defines,
move the default environmental variables to a file called
imx8mn_beacon.env and reference it from the defconfigs.
Signed-off-by: Adam Ford <[email protected]>
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Since U-Boot builds HTML documentation, migrate the contents
of the README file to an rst file which can generate the
proper outputs.
Signed-off-by: Adam Ford <[email protected]>
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Instead of cluttering up a header file with a bunch of defines,
move the default environmental variables to a file called
imx8mm_beacon.env and reference it from the defconfig.
Signed-off-by: Adam Ford <[email protected]>
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Read ethernet MAC address from EEPROM located on the SOM.
Signed-off-by: Hugo Villeneuve <[email protected]>
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While testing the ethernet interface on a Variscite symphony carrier
board using an imx8mn SOM with an onboard ADIN1300 PHY (EC hardware
configuration), the ethernet PHY is not detected.
The ADIN1300 datasheet indicate that the "Management interface
active (t4)" state is reached at most 5ms after the reset signal is
deasserted.
The device tree in Variscite custom git repository uses the following
property:
phy-reset-post-delay = <20>;
Add a new MDIO property 'reset-deassert-us' of 20ms to have the same
delay inside the ethphy node. Adding this property fixes the problem
with the PHY detection.
Note that this SOM can also have an Atheros AR8033 PHY. In this case,
a 1ms deassert delay is sufficient. Add a comment to that effect.
Fixes: c4c1ed68c1e8 ("imx8mn_var_som: Add support for Variscite
VAR-SOM-MX8M-NANO board")
Signed-off-by: Hugo Villeneuve <[email protected]>
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Select DM_ETH_PHY so that the reset-gpios property of the ethphy node
can be used.
Also select DM_PCA953X, which is needed for resetting the
ethernet PHY on the carrier board via the PCA9534 I/O expander.
Commit 4e5114daf9eb ("imx8mn: synchronise device tree with linux") did
synchronise device tree with linux, which in effect removed obsolete
PHY reset properties and replaced them with new mdio DM
properties. But the commit didn't activate DM_ETH_PHY or DM_PCA953X.
Fixes: 4e5114daf9eb ("imx8mn: synchronise device tree with linux")
Signed-off-by: Hugo Villeneuve <[email protected]>
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Enable support to read and display configuration/manufacturing infos
from 4Kbit EEPROM located on SOM board.
Note: CONFIG_DISPLAY_BOARDINFO is automatically selected for ARM arch.
Signed-off-by: Hugo Villeneuve <[email protected]>
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Getting
Found /vpu_g1@38300000 node
Modify /vpu_g1@38300000:status disabled
Found /vpu_g2@38310000 node
Modify /vpu_g2@38310000:status disabled
etc. on the console on every boot is needlessly verbose. Demote the
"Found ..." lines to debug(), which is consistent with other instances
in soc.c.
Signed-off-by: Rasmus Villemoes <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
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The single binary version of u-boot for XEA board is used to debrick and
factory programming.
The produced u-boot.sb is a single file, which allows having fully
operational u-boot prompt loaded with imx287 ROM.
Signed-off-by: Lukasz Majewski <[email protected]>
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The XEA board now supports the DM_SERIAL feature in u-boot.
The SPL is using the SPL_OF_PLATDATA - i.e. NOT SPL_DM_SERIAL to
reduce the overall size of the SPL binary.
Signed-off-by: Lukasz Majewski <[email protected]>
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The CONFIG_PL011 used by all other ARCH_MX28 based boards is not
supporting DM_SERIAL. Instead, other define - namely CONFIG_PL01X_SERIAL
shall be used by boards supporting DM_SERIAL.
Signed-off-by: Lukasz Majewski <[email protected]>
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The in-spl enabled DM serial console requires the board setup to be
able to parse SPL_OF_PLATDATA based serial driver (pl01x) for the
imx28 based XEA board.
Signed-off-by: Lukasz Majewski <[email protected]>
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When DM_SERIAL is enabled on mxs (i.e. imx28) platform, the console
early initialization must be postponed until the driver model is
correctly setup.
Signed-off-by: Lukasz Majewski <[email protected]>
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Before this change the FR_TXFF (Transmit FIFO full) bit (5 in
HW_UARTDBG_FR) has been used to assess if there is still data pending
to be sent via UART.
This approach is problematic, as it may happen that serial is in the
middle of transmission (so the TX FIFO is NOT full anymore) and this
test returns true infinitely. As a result, for example in _serial_flush()
DM serial function we are locked in endless while().
The fix here is to test explicitly if the TX FIFO is empty.
Signed-off-by: Lukasz Majewski <[email protected]>
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This commit prepares the pl01x serial driver to be used with
SPL_OF_PLATDATA enabled.
Signed-off-by: Lukasz Majewski <[email protected]>
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Before this change, building this driver for SPL with enabled SPL_DM_SERIAL
was problematic, as '-Wunused-const-variable=' warning was visible.
Now, the code is only considered when u-boot proper is build.
Signed-off-by: Lukasz Majewski <[email protected]>
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As imx28 family of SoCs is NOT supporting the Common Clock Framework (CCF)
the 'clks' property shall NOT be enabled by default.
Without this change u-boot proper before relocation tries to bind driver
(which doesn't exists) for this device. As a result, pre-relocation DTB
parsing is finished with error and the board hangs in a very early stage
of u-boot proper boot process.
Signed-off-by: Lukasz Majewski <[email protected]>
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The imx287 SoC doesn't support common clock framework (CCF), so the
'clocks' property is removed to avoid early (i.e. in SPL) errors when
SPL_OF_PLATDATA is used.
Signed-off-by: Lukasz Majewski <[email protected]>
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