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Commit 290ffe5788 (imx8m: fix reading of DDR4 MR registers) lifted a
private definition of lpddr4_mr_read() from imx8mm-cl-iot-gate board
code to drivers/ddr/imx/imx8m/ddrphy_utils.c, because that version
actually seems to work in practice.
However, commit 99c7cc58e1 (ddr: imx: Add i.MX9 DDR controller driver)
reintroduced the broken version in drivers/ddr/imx/imx8m/ddr_init.c,
copied most of the rest of ddrphy_utils.c to
drivers/ddr/imx/phy/ddrphy_utils.c, and stopped building
drivers/ddr/imx/imx8m/ddrphy_utils.c [and that file was then finally
completely removed with 7e9bd84883 (imx8m: ddrphy_utils: Remove unused
file)].
I assume this must have broken the imx8mm-cl-iot-gate board, at least
those that have not had their eeprom programmed with the proper
information. It certainly did break our out-of-tree board which always
reads back the ID register and uses that for a sanity check.
So apply the fix from 290ffe5788 once again.
Fixes: 99c7cc58e1 (ddr: imx: Add i.MX9 DDR controller driver)
Signed-off-by: Rasmus Villemoes <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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This change initializes Cryptographic Accelerator and Assurance Module.
Signed-off-by: Andrejs Cainikovs <[email protected]>
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CAAM is initialized in SPL, so relevant device tree nodes needs to be
updated.
Signed-off-by: Andrejs Cainikovs <[email protected]>
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- enable bootcount command
- enable CRC32 and MD5
- enable time commands
- enable GPIO LED support
- enable further eMMC HS400 functionality
- enable fixed PHY and MDIO driver model
- enable USB host functionality
- enable thermal management unit driver
- enable hexdump
Signed-off-by: Marcel Ziswiler <[email protected]>
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- enable bootcount command
- integrate bootcount using SNVS_LP general purpose register LPGPR0
- enable link-time optimisation
- explicitly set a boot delay of one second
- enable CRC32 and MD5
- enable command for low-level access to data in a partition
- enable time commands
- enable PMIC commands
- improve ETHPRIME configuration
- enable eMMC HS400 functionality
- enable fixed PHY and MDIO driver model
- remove stale PFUZE100 PMIC driver
- enable thermal management unit driver
- enable more USB host functionality
- enable hexdump
Signed-off-by: Marcel Ziswiler <[email protected]>
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Update the distro config env memory layout for the Verdin iMX8M Mini and
Verdin iMX8M Plus again:
- loadaddr=0x48200000 allows for 128MB area for uncompressing (ie FIT
images, kernel_comp_addr_r, kernel_comp_size)
- fdt_addr_r = loadaddr + 128MB - allows for 128MB kernel
- scriptaddr = fdt_addr_r + 512KB - allows for 512KB fdt
- ramdisk_addr_r = scriptaddr + 512KB - allows for 512KB script
Memory layout taken from commit fd5c7173ade4
("imx8m{m,n}_venice: update env memory layout").
Note that for our regular BSP Layers and Reference Images for Yocto
Project an updated distro boot script is required (see
meta-toradex-bsp-common/recipes-bsp/u-boot/u-boot-distro-boot).
Note that this corrects a pre-maturely applied version 2 of the same
patch set.
Fixes: bbe0089d29e ("verdin-imx8mm: verdin-imx8mp: update env memory layout")
Signed-off-by: Marcel Ziswiler <[email protected]>
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The GW7904 is based on the i.MX 8M Mini SoC featuring:
- LPDDR4 DRAM
- eMMC FLASH
- microSD connector with UHS support
- LIS2DE12 3-axis accelerometer
- Gateworks System Controller
- IMX8M FEC
- 2x RS232 off-board connectors
- PMIC
- 10x bi-color LED's
- 1x miniPCIe socket with PCIe and USB2.0
- 802.3at Class 4 PoE
- 10-30VDC input via barrel-jack
Signed-off-by: Tim Harvey <[email protected]>
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i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam.
i.Core MX8M Plus needs to mount on top of this Evaluation board for
creating complete i.Core MX8M Plus EDIMM2.2 Starter Kit.
Add support for it.
Signed-off-by: Jagan Teki <[email protected]>
Signed-off-by: Manoj Sai <[email protected]>
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Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Plus PCIe
- MIPI CSI
- 2x CAN
- Audio Out
i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam.
i.Core MX8M Plus needs to mount on top of this Evaluation board for
creating complete i.Core MX8M Plus EDIMM2.2 Starter Kit.
Add support for it.
Sync the i.Core MX8M Plus is an EDIMM SoM based on NXP
devicetree file from linux-next tree.
commit <aec8ad34f7f24> (arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit)
Signed-off-by: Manoj Sai <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus
from Engicam.
General features:
- NXP i.MX8M Plus
- Up to 4GB LDDR4
- 8 eMMC
- Gigabit Ethernet
- USB 3.0, 2.0 Host/OTG
- PCIe 3.0 interface
- I2S
- LVDS
- rest of i.MX8M Plus features
i.Core MX8M Plus needs to mount on top of Engicam baseboards
for creating complete platform solutions.
Add support for it.
Sync the i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus
from Engicam devicetree file from linux-next tree.
commit <eefe06b295087> (arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus SoM)
Signed-off-by: Manoj Sai <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
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The GW7903 has a BD71847 PMIC on I2C1. Adjust the model compare strings
to add it.
Signed-off-by: Tim Harvey <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Enable driver model for ulp watchdog timer. When CONFIG_WDT=y and the
status of device node is "okay", initr_watchdog will be called and
finally calls ulp_wdt_probe() and ulp_wdt_start().
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Ye Li <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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The reset source of the external PMIC on i.MX93 is WDOG_ANY PAD and the
source of WDOG_ANY PAD is interrupt. Therefore, using PMIC to reset
needs to enable the watchdog interrupt.
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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The WDOG clocks are sourced from the fixed 32KHz (lpo_clk).When the
timeout period exceeds 2 seconds, the value written to the TOVAL
register is larger than 16-bit can represent. Enabling watchdog
prescaler to solve this problem.
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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To use 32bits refresh and unlock command as default, check the CMD32EN
bit to select the corresponding commands.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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With the migration of the watchdog infrastructure to cyclic functions
it's been noticed, that at least one watchdog driver is broken now. As
the execution time of it's watchdog reset function is quite long.
In general it's not really necessary (right now) to disable the cyclic
function upon exceeding CPU time usage. So instead of disabling the
cylic function in this case, let's just print a warning once to show
this potential problem to the user.
Signed-off-by: Stefan Roese <[email protected]>
Suggested-by: Rasmus Villemoes <[email protected]>
Cc: Rasmus Villemoes <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Pali Rohár <[email protected]>
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In order to test that we properly handle watchdog(s) during the "wait
for the user to interrupt autoboot" phase, we need a watchdog device
to be watching us.
Signed-off-by: Rasmus Villemoes <[email protected]>
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In order to test that U-Boot actually maintains the watchdog device(s)
during long-running busy-loops, such as those where we wait for the
user to stop autoboot, we need a watchdog device that actually does
something during those loops; we cannot test that behaviour via the DM
test framework.
So introduce a relatively simple watchdog device which is simply based
on calling the host OS' alarm() function; that has the nice property
that a new call to alarm() simply sets a new deadline, and alarm(0)
cancels any existing alarm. These properties are precisely what we
need to implement start/reset/stop. We install our own handler so that
we get a known message printed if and when the watchdog fires, and by
just invoking that handler directly, we get expire_now for free.
The actual calls to the various OS functions (alarm, signal, raise)
need to be done in os.c, and since the driver code cannot get access
to the values of SIGALRM or SIG_DFL (that would require including a
host header, and that's only os.c which can do that), we cannot simply
do trivial wrappers for signal() and raise(), but instead create
specialized functions just for use by this driver.
Apart from enabling this driver for sandbox{,64}_defconfig, also
enable the wdt command which was useful for hand-testing this new
driver (especially with running u-boot under strace).
Signed-off-by: Rasmus Villemoes <[email protected]>
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This is a companion to u-boot,noautostart. If one has a single
watchdog device that one does want to have auto-started, but several
others that one doesn't, the only way currently is to set the
CONFIG_WATCHDOG_AUTOSTART and then use the opt-out for the majority.
The main motivation for this is to add an autostarted watchdog device
to the sandbox (to test a fix) without having to set AUTOSTART in
sandbox_defconfig and add the noautostart property to the existing
devices. But it's also nice for symmetry, and the logic in
init_watchdog_dev() becomes simpler to read because we avoid all the
negations.
Signed-off-by: Rasmus Villemoes <[email protected]>
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Add expire_now function for generic sysreset request
Signed-off-by: Jim Liu <[email protected]>
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Correct pointer dereferencing check to be more consistent.
Eliminate the below smatch warning:
drivers/mmc/mmc.c:3118 mmc_init_device()
warn: variable dereferenced before check 'm' (see line 3116)
Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]>
Reviewed-by: Michal Simek <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Unconditionally clearing DTO when RXDR is set leads to spurious timeouts
in FIFO mode transfers if events occur in the following order:
mask = dwmci_readl(host, DWMCI_RINTSTS);
// Hardware asserts DWMCI_INTMSK_DTO here
dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_DTO);
if (mask & DWMCI_INTMSK_DTO) {
// Unreachable as DTO is cleared without being handled!
return 0;
}
Only clear interrupts that we have seen and are handling so that DTO is
not missed.
Signed-off-by: John Keeping <[email protected]>
Tested-by: Jerome Forissier <[email protected]> (Rock PI 4B)
Tested-by: Quentin Schulz <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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The SDMMC IOs can be in an IO domain, that has to be enabled.
This is done by enabling vqmmc in the driver.
This has no impact on configurations not using an IO domain, the check
can then be executed on all platforms managing regulator, and the vqmmc
regulator enabled on all platforms having it in their DT.
Signed-off-by: Yann Gautier <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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The UHS modes for SD, HS200 and HS400 modes for eMMC are not supported
by the stm32_sdmmc2 driver.
Make it clear by removing the corresponding caps after parsing the DT.
Signed-off-by: Yann Gautier <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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To support dual data rate with STM32 sdmmc2 driver, the dedicated bit
(DDR - BIT(18)) needs to be set in the CLKRC register. Clock bypass
(no divider) is not allowed in this case. This is required for the
eMMC DDR modes.
Signed-off-by: Yann Gautier <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Add Socionext F_SDH30_E51 IP support. The features of this IP includes
CMD/DAT line delay and force card insertion mode for non-removable cards.
And the IP needs to add some quirks.
Signed-off-by: Kunihiko Hayashi <[email protected]>
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This patch defines a quirk to disable the block count
for single block transactions.
This is similar to Linux kernel commit d3fc5d71ac4d
("mmc: sdhci: add a quirk for single block transactions").
Signed-off-by: Kunihiko Hayashi <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Get rid of discrepancy beween comment /* 250 ms */ and code
which shifts by 4 thus dividing by 16.
So change code to shift by 2 and make the timeout value 250 ms.
Signed-off-by: Sergei Antonov <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
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Array index for SCCR 22th DWORD should be 21.
Fixes: bebdc237507c ("mtd: spi-nor: Parse SFDP SCCR Map")
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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address mode
The flash's internal address mode is tracked by nor->add_mode_nbytes and
it is set to 3 in BFPT parse. SEMPER multi-die package parts (>1Gb) are
3- or 4-byte address mode by default, depending on model number. We need
to make sure that 4-byte address mode is used for multi-die package parts.
For single-die package parts (<=1Gb), registers can be accessed by 3-byte
address. Read, program, and erase use the 4B opcodes that always take
4-byte address regardless of flash's internal address mode.
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Read/Write Any Register commands take 3- or 4- byte address depending on
flash's internal address mode. The nor->addr_width tracks number of
address bytes used in read/program/erase ops that can be 4
(with 4B opcodes) regardless of flash's internal address mode. The
nor->addr_mode_nbytes tracks flash's internal address mode so replace
nor->addr_width by that.
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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The nor->addr_width tracks number of address bytes used in
read/program/erase ops and eventually set to 4 for >16MB chips, regardless
of flash's internal address mode. For Infineon SEMPER flash's, we use
Read/Write Any Register commands for configuration and status check.
These commands take 3- or 4-byte address depending on flash's internal
address mode.
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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JESD216D-01 mentions that "defaults to 3-Byte mode; enters 4-Byte mode on
command."
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Add flash info table entries for s28hl512gt, s28hl01gt, and s28hs01gt.
These devices have the same functionality as s28hs512t.
In spi-nor-core, use device ID byte to detect S28 family instead of
device name.
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Change configuration macro name to support all other devices in SEMPER S28
family.
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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Change prefix to support all other devices in SEMPER S28 family.
Signed-off-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
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- NC-SI handling support and enable on evb-ast2[56]00, gpio driver for
ADP5585, improve qfw support, print more sysresets info, gw_ventana
and gcc-12 bugfix, improve BCB support, fix a few typos and remove an
unused keymile CONFIG symbol.
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This unused nowadays and can be dropped.
Signed-off-by: Holger Brunck <[email protected]>
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In some cases, the param variable is wrong, and in other cases we have
undocumented arguments.
Fix the docs.
Signed-off-by: Mattijs Korpershoek <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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For other sandbox tests the printed test name corresponds to the
configuration except for this one.
Signed-off-by: Michal Suchanek <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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For some blk operations, it's possible that a different hw partition
gets selected via blk_dselect_hwpart().
In that case, only the region of the device covered by that partition
is accessible.
This breaks "bcb load" which attempts to read the gpt and assumes it's
on the user(0) hw partition:
=> bcb load 2 misc
GUID Partition Table Header signature is wrong: 0xDE7B17AD07D9E5D6 != 0x5452415020494645
find_valid_gpt: *** ERROR: Invalid GPT ***
GUID Partition Table Header signature is wrong: 0x0 != 0x5452415020494645
find_valid_gpt: *** ERROR: Invalid Backup GPT ***
Error: mmc 2:misc read failed (-2)
Add a fail-safe in __bcb_load() to ensure we will always read from the
user(0) hwpartition.
This fixes the following fastboot sequence:
$ fastboot erase mmc2boot1 # switch to hwpart1
$ fastboot reboot bootloader # switch to hwpart0, then reads GPT
Signed-off-by: Mattijs Korpershoek <[email protected]>
Reviewed-by: Sean Anderson <[email protected]>
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Building with GCC 12.2 results in an error
board/gateworks/gw_ventana/gw_ventana.c:636:68: error: the comparison
will always evaluate as 'true' for the address of 'pwm_padmux' will
never be NULL [-Werror=address]
636 | } else if (hwconfig_subarg_cmp(arg, "mode", "pwm") &&
| ^~
Remove the superfluous check.
Signed-off-by: Heinrich Schuchardt <[email protected]>
Reviewed-By: Tim Harvey <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
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Boards can have multiple sysresets, iterate all when printing sysreset
info.
Fixes: 23471aed5c ("board_f: Add reset status printing")
Signed-off-by: Michal Suchanek <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Without this the early sysreset code cannot be tested.
Signed-off-by: Michal Suchanek <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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At the moment the QEMU boot sequence tries various (storage) devices
when trying to find a payload to boot.
To simplify starting a specific kernel and initrd, there is also the qfw
command, which can use the files specified on the QEMU command line, via
the -kernel and -initrd options.
Add this command to the list of boot options to try. Since users
specifying those options on the command line probably explicitly want
to run them, let's place the new command first. Without those options,
the qfw command will just gracefully fail, and we continue with the
existing order.
This allows auto-booting of specific kernels in QEMU, for instance in CI
systems.
Signed-off-by: Andre Przywara <[email protected]>
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When we try to load a kernel via the QEMU firmware device, we currently
"return -1;" if no kernel was specified on the QEMU command line. This
leads to the usage output, which is confusing (since nothing on the
command line was really wrong), but also somewhat hides the actual error
message.
Return CMD_RET_FAILURE (1), as it's a proper error, and make the message
more clear that this is not only a "warning".
This helps to call this command in boot scripts, and to gracefully
continue if this doesn't work.
Signed-off-by: Andre Przywara <[email protected]>
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At the moment the QEMU firmware command just prints the size of the
loaded binaries on the console.
To go with all the other load methods, and many boot scripts'
expectations, also store the size of the file loaded last in the
environment variable "filesize".
We first put the kernel size in there, but overwrite this with the
initrd size, should we have one, because this is probably the more
prominent user of $filesize (in the booti or bootz command).
Signed-off-by: Andre Przywara <[email protected]>
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Add gpio driver for ADP5585 I/O Expander Controller. The ADP5585 is a 10
input/output port expander and can be used to increase the number of
I/Os available to a processor.
Signed-off-by: Alice Guo <[email protected]>
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Aspeed BMCs are commonly used with NC-SI. A system indicates the driver
should configure the link over NC-SI using the device tree.
Add it to the defconfig so we get compile coverage of the driver, even
if the EVBs do not normally use it.
Signed-off-by: Joel Stanley <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
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Update the ftgmac100 driver to support NC-SI instead of an mdio phy
where available. This is a common setup for Aspeed AST2x00 platforms.
NC-SI mode is determined from the device-tree if either phy-mode sets it
or the use-ncsi property exists. If set then normal mdio setup is
skipped in favour of the NC-SI phy.
Signed-off-by: Samuel Mendoza-Jonas <[email protected]>
Signed-off-by: Joel Stanley <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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