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Makes it possible to use 16-bit DDR memory.
Signed-off-by: Dominic Rath <[email protected]>
Signed-off-by: Christian Gmeiner <[email protected]>
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Add CONFIG_NR_DRAM_BANKS from am64x_evm_a53_defconfig as this is needed
to calculate the size of DDR that is available.
Signed-off-by: Dave Gerlach <[email protected]>
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Add 'ss_cfg' memory region for memorycontroller node which is required
to enable ECC.
Signed-off-by: Dave Gerlach <[email protected]>
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Call into k3-ddrss driver to fixup device tree and resize the available
amount of DDR if ECC is enabled.
A second fixup is required from A53 SPL to take the fixup as done from
R5 SPL and apply it to DT passed to A53 U-boot, which in turn passes
this to the OS.
Signed-off-by: Dave Gerlach <[email protected]>
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Introduce ECC Functionality for full memory space as implemented in the
DDRSS. The following is done to accomplish this:
* Introduce a memory region "ss" to allow dt to provide DDRSS region,
which is not the same as "ctl" which is the controller region.
* Introduce a "ti,ecc-enable" flag which allows a memorycontroller
instance to enable ecc.
* Introduce functionality to properly program the DDRSS registers to
enable ECC for the full DDR memory space if enabled with above flag.
* Expose a k3_ddrss_ddr_fdt_fixup call to allow fixup of fdt blob to
account from DDR memory that must be reserved for ECC operation.
Signed-off-by: Dave Gerlach <[email protected]>
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The current address being read from dt actually represents the ddrss_ctl
memory region, while ddrss_ss region is something else. Introduce
ddrss_ctl_regs and use it to free up ddrss_ss_regs for its proper
purpose later so that we can avoid confusion.
Signed-off-by: Dave Gerlach <[email protected]>
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Add DT binding documentation for enabling ECC in the DDR sub system present
on AM64 device.
Signed-off-by: Dave Gerlach <[email protected]>
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Use the appropriate fdtdec_setup_mem_size_base and
fdtdec_setup_bank_size calls in dram_init and dram_bank_init to pull
these values from DT, where they are already available, instead of
hardcoding them.
Signed-off-by: Dave Gerlach <[email protected]>
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Mark the memory node with u-boot,dm-spl so we can use it from early SPL.
Signed-off-by: Dave Gerlach <[email protected]>
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Timer0 runs at 200MHz,and the clock-frequency defined in DT is
incorrect. Fix it.
Signed-off-by: Vignesh Raghavendra <[email protected]>
Reviewed-By: Nishanth Menon <[email protected]>
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On arm64 systems, recommendation is to use per-cpu timer for time
keeping. Currently AM64 ends up using DM timer as tick timer as driver
is enabled in the config. Drop OMAP DM Timer related configs, this will
switch to using armv8 per-cpu timer as tick timer for A53 SPL/U-Boot.
Signed-off-by: Vignesh Raghavendra <[email protected]>
Reviewed-By: Nishanth Menon <[email protected]>
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Enable ESM driver for AM64x R5 SPL/u-boot builds.
Signed-off-by: Hari Nagalla <[email protected]>
Reviewed-by: Christian Gmeiner <[email protected]>
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On AM64x devices, it is possible to route Main ESM0 error events to MCU
ESM. MCU ESM high error output can trigger the reset logic to reset the
device. So, for these devices we expect two ESM device nodes in the
device tree, one for Main ESM and the another MCU ESM in the device tree.
When these ESM device nodes are properly configired it is possible to
route the Main RTI0 WWDT output to the MCU ESM high output through Main
ESM and trigger a device reset when
CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is set to '0'.
On K3 AM64x devices, the R5 SPL u-boot handles the ESM device node
configurations.
Signed-off-by: Hari Nagalla <[email protected]>
Reviewed-by: Christian Gmeiner <[email protected]>
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Enable access to ESM0 configuration space and add Main ESM0 and MCU ESM
nodes to the AM64 device tree.
Signed-off-by: Hari Nagalla <[email protected]>
Reviewed-by: Christian Gmeiner <[email protected]>
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Add functionality to enable, set priority to the input events and to
route to MCU ESM. On AM64x/AM62x devices, it is possible to route Main
ESM0 error events to MCU ESM. When these error events are routed to MCU
ESM high output, it can trigger the reset logic to reset the device,
when CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is set to '0'.
K3 based J7 devices (ex: J721e) also have ESM modules, and the changes
to the driver does not impact those devices.
Signed-off-by: Hari Nagalla <[email protected]>
Reviewed-by: Christian Gmeiner <[email protected]>
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U-boot is intended to replace linux kernel in android boot image(ABL), and
it's FIT payload to replace initramfs file. The boot process is similar to
boot image with linux:
- android bootloader (ABL) unpacks android boot image
- ABL sets `linux,initrd-start property` in chosen node in unpacked FDT
- ABL sets x0 register to FDT address, and passes control to u-boot
- u-boot reads x0 register, and stores it in `prevbl_fdt_addr` env variable
- u-boot reads `linux,initrd-start` property,
and stores it in `prevbl_initrd_start_addr`
In this way, u-boot bootcmd relies on `prevbl_initrd_start_addr` env
variable, and boils down to `bootm $prevbl_initrd_start_addr`.
If more control on boot process is desired, pack a boot script in
FIT image, and put it to default configuration
What done:
- Rearrange defconfig option order
- Add CONFIG_SAVE_PREV_BL_* options
- Doc updates:
- remove wrong SBOOT memory corruption note, because
memory is changed during u-boot bringup process,
not by SBOOT
- put payload on ramdisk place in abl boot image
creation step
Signed-off-by: Dzmitry Sankouski <[email protected]>
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Platforms can overwrite the weak definition of spl_mmc_boot_mode() to
determine where to load U-Boot proper from.
For most of them this is a trivial decision based on Kconfig variables,
but it might be desirable the probe the actual device to answer this
question.
Pass the pointer to the mmc struct to that function, so implementations
can make use of that.
Compile-tested for all users changed.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Stefano Babic <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]> (for SoCFPGA)
Acked-by: Lokesh Vutla <[email protected]> (for OMAP and K3)
Reviewed-by: Simon Glass <[email protected]>
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BSP boot0 adjust PLL LDO regulator before clocks are initialized.
Let's do that.
Signed-off-by: Jernej Skrabec <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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BSP boot0 executes resistor calibration before clocks are initialized.
Let's do that.
Signed-off-by: Jernej Skrabec <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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H6 and H616 SPL code has a few writes to unknown PRCM registers. Now
that we know what they are, let's replace magic offsets with proper
register names.
Signed-off-by: Jernej Skrabec <[email protected]>
Reviewed-by: Samuel Holland <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Fix non working console on uart2, that seems releated to both
Allwinner H2+ and H3.
Signed-off-by: Angelo Dureghello <[email protected]>
[Andre: remove H2+, rearrange pin setup order]
Signed-off-by: Andre Przywara <[email protected]>
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This syncs the sun8i-h3-nanopi-neo.dts from the Linux tree, from tag
v5.18-rc1.
The alias is required to enable automatic MAC address generation.
Signed-off-by: Baltazár Radics <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Currently, clock/reset setup for this device is handled by a
platform-specific function and is intermixed with non-DM pinctrl
setup. Use the devicetree to get clocks/resets, which disentagles
it from the pinctrl setup in preparation for moving to DM_PINCTRL.
This also has the added benefit of picking the right clock/reset
bits for H6 and new SoCs that have a rearranged PRCM MMIO space.
Signed-off-by: Samuel Holland <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Chips attached to the RSB bus require an initialization command before
they can be used. (Specifically, this command programs the chip's
runtime address.) The driver does this in its .probe_chip hook, under
the assumption that .probe_chip is called during child probe. This is
not the case; .probe_chip is only called by dm_i2c_probe, which is
intended for use by board-level code, not for chips with OF nodes.
Since this initialization command must be run before a child chip can be
used, do it before probing each child.
Signed-off-by: Samuel Holland <[email protected]>
Acked-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Currently, clock/reset setup for this device is handled by a
platform-specific function and is intermixed with non-DM pinctrl
setup. Use the devicetree to get clocks/resets, which disentagles
it from the pinctrl setup in preparation for moving to DM_PINCTRL.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Chips attached to the P2WI bus require an initialization command before
they can be used. (Specifically, this switches the chip from I2C mode
to P2WI mode.) The driver does this in its .probe_chip hook, under the
assumption that .probe_chip is called during child probe. This is not
the case; .probe_chip is only called by dm_i2c_probe, which is intended
for use by board-level code, not for chips with OF nodes.
Since this initialization command must be run before a child chip can be
used, do it before probing each child.
Signed-off-by: Samuel Holland <[email protected]>
Acked-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Now that mkimage can generate TOC0 images, and the SPL can interpret
them, hook up the build infrastructure so the user can choose which
image type to build. Since the absolute load address is stored in the
TOC0 header, that information must be passed to mkimage.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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SPL uses the image header to detect the boot device and to find the
offset of the next U-Boot stage. Since this information is stored
differently in the eGON and TOC0 image headers, add code to find the
correct value based on the image type currently in use.
Signed-off-by: Samuel Holland <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Most Allwinner sunxi SoCs have separate boot ROMs in non-secure and
secure mode. The "non-secure" or "normal" boot ROM (NBROM) uses the
existing sunxi_egon image type. The secure boot ROM (SBROM) uses a
completely different image type, known as TOC0.
A TOC0 image is composed of a header and two or more items. One item
is the firmware binary. The others form a chain linking the firmware
signature to the root-of-trust public key (ROTPK), which has its hash
burned in the SoC's eFuses. Signatures are made using RSA-2048 + SHA256.
The pseudo-ASN.1 structure is manually assembled; this is done to work
around bugs/quirks in the boot ROM, which vary between SoCs. This TOC0
implementation has been verified to work with the A50, A64, H5, H6,
and H616 SBROMs, and it may work with other SoCs.
Signed-off-by: Samuel Holland <[email protected]>
Acked-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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As mkimage -T sunxi_egon now gains support for -A parameter, specify the
architecture when generating SPL boot image for sunxi.
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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There's now a sun20i family in sunxi, which uses RISC-V CPU.
Add support for making eGON.BT0 image for RISC-V.
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Refactor some functions in mkimage sunxi_egon type, in order to prepare
for adding support for more CPU architectures (e.g. RISC-V). In
addition, compatibility for operation w/o specified architecture is
kept, in this case the architecture is assumed as ARM.
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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The sunxi_egon type used to take no -A argument (because we assume sunxi
targets are all ARM). However, as Allwinner D1 appears as the first
RISC-V sunxi target, we need to support -A; in addition, as external
projects rely on U-Boot mkimage to generate sunxi eGON.BT0 header, we
need to keep compatibility with command line without -A.
As the default value of arch in mkimage is not proper (IH_ARCH_PPC
instead of IH_ARCH_INVALID), to keep more compatibility, add an Aflag
field to image parameters to describe whether an architecture is
explicitly specified.
Reviewed-by: Tom Rini <[email protected]>
Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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This is the only possible mux setting for the A64's PWM peripheral.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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When the DM_I2C driver is loaded, the pin setup is done automatically
from the device tree by the pinctrl driver.
Clean up the code in the process: remove #ifdefs and recognize that the
pin configuration is the same for all sun8i/sun50i SoCs, not just those
which select CONFIG_MACH_SUN8I.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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When the DM_I2C driver is loaded, the pin setup is done automatically
from the device tree by the pinctrl driver.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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These options are not currently enabled anywhere. Any new users should
use DM clocks and pinctrl.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Where multiple options were available, the one matching board.c and the
device trees was chosen.
Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland <[email protected]>
[Andre: fixup H5 I2C1 pinmux]
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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This includes UART0 and R_UART (s_uart) on all supported platforms, plus
the additional UART configurations from arch/arm/mach-sunxi/board.c.
Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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