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Commit 5534fb4f4833 ("arm64: a37xx: pinctrl: Correct PWM pins
definitions") introduced bogus definitions os PWM pins: all 4 pins have
index 11, instead of having indexes 11, 12, 13, 14.
Fix this.
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Pali Rohár <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Replace null pointer by pointer to device registers when calling
armada38x_rtc_write.
Signed-off-by: Francois Berder <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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The a3700_fdt_fix_pcie_regions() function still computes nonsense.
It computes the fixup offset from the PCI address taken from the first
row of the "ranges" array, which means that:
- PCI address must equal CPU address (otherwise the computed fix offset
will be wrong),
- the first row must contain the lowest address.
This is the case for the default device-tree, which is why we didn't
notice it.
It also adds the fixup offset to all PCI and CPU addresses, which is
wrong.
Instead:
1) The fixup offset must be computed from the CPU address, not PCI
address.
2) The fixup offset must be computed from the row containing the lowest
CPU address, which is not necessarily contained in the first row.
3) The PCI address - the address to which the PCIe controller remaps the
address space as seen from the point of view of the PCIe device -
must be fixed by the fix offset in the same way as the CPU address
only in the special case when the CPU adn PCI addresses are the same.
Same addresses means that remapping is disabled, and thus if we
change the CPU address, we need also to change the PCI address so
that the remapping is still disabled afterwards.
Consider an example:
The ranges entries contain:
PCI address CPU address
70000000 EA000000
E9000000 E9000000
EB000000 EB000000
By default CPU PCIe window is at: E8000000 - F0000000
Consider the case when TF-A moves it to: F2000000 - FA000000
Until now the function would take the PCI address of the first entry:
70000000, and the new base, F2000000, to compute the fix offset:
F2000000 - 70000000 = 82000000, and then add 8200000 to all addresses,
resulting in
PCI address CPU address
F2000000 6C000000
6B000000 6B000000
6D000000 6D000000
which is complete nonsense - none of the CPU addresses is in the
requested window.
Now it will take the lowest CPU address, which is in second row,
E9000000, and compute the fix offset F2000000 - E9000000 = 09000000,
and then add it to all CPU addresses and those PCI addresses which
equal to their corresponding CPU addresses, resulting in
PCI address CPU address
70000000 F3000000
F2000000 F2000000
F4000000 F4000000
where all of the CPU addresses are in the needed window.
Fixes: 4a82fca8e330 ("arm: a37xx: pci: Fix a3700_fdt_fix_pcie_regions() function")
Signed-off-by: Pali Rohár <[email protected]>
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Enable ext4 write support in Turris Omnia's defconfig. Some users find
it useful.
Signed-off-by: Marek Behún <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Use "MVPCIE_" prefix instead of generic "PCIE_" prefix for pci_mvebu.c
specific macros. Define offset macros for Root Port registers and use
standard register macros from pci.h when accessing Root Port registers.
Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Marek Behún <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Macro SELECT() is unused and struct mvebu_pcie field lane_mask is unused
too. Remove them.
Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Marek Behún <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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Sometimes kwboot after quitting terminal prints error message:
terminal: Bad address
This is caused by trying to call write() syscall with count of (size_t)-1
bytes.
When quit sequence is split into more read() calls then number of input
bytes (nin) at the end of cycle can underflow and be negative. Fix it.
Fixes: de7514046ea5 ("tools: kwboot: Fix detection of quit esc sequence")
Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
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- Assorted Kconfig migrations and related cleanups.
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This converts the following to Kconfig:
CONFIG_CHIP_SELECTS_PER_CTRL
Cc: Alison Wang <[email protected]>
Cc: Pramod Kumar <[email protected]>
Cc: Priyanka Jain <[email protected]>
Cc: Rajesh Bhagat <[email protected]>
Cc: Vladimir Oltean <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
Signed-off-by: Tom Rini <[email protected]>
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This option is not in use anywhere and the documentation implies it's
for some very old and unlikely to be seen currently issues. Rather than
update the code so the CONFIG symbol could be easily in Kconfig, remove
the code.
Cc: Ramon Fried <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Acked-by: Ramon Fried <[email protected]>
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This converts the following to Kconfig:
CONFIG_BOOTP_MAY_FAIL
CONFIG_BOOTP_VENDOREX
CONFIG_BOOTP_BOOTFILESIZE
CONFIG_BOOTP_NISDOMAIN
CONFIG_BOOTP_TIMEOFFSET
Cc: Ramon Fried <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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This slight environment modification shouldn't be in the CONFIG
namespace, change it.
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_BOOTFILE
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_BOARD_POSTCLK_INIT
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_BOARD_ECC_SUPPORT
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_BIOSEMU
Cc: Simon Glass <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
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This converts the following to Kconfig:
CONFIG_BOARD_COMMON
Signed-off-by: Tom Rini <[email protected]>
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These particular values are not configurable and today we always set
CONFIG_SECURE_BL1_ONLY. Move these to where they're used in the code,
and drop from the CONFIG namespace.
Cc: Minkyu Kang <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Reviewed-by: Minkyu Kang <[email protected]>
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This converts the following to Kconfig:
CONFIG_BTB
Signed-off-by: Tom Rini <[email protected]>
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Remove some code, primarily CPM2 related, that is now unused since the
removal of MPC8540/60ADS.
Fixes 3913191c8a6b ("powerpc: mpc8540ads: mpc8560ads: Drop support for MPC8540/60ADS")
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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- A small set of scmi updates
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https://source.denx.de/u-boot/custodians/u-boot-at91
First set of u-boot-atmel fixes for the 2022.04 cycle:
This fixes set includes only a single fix for the Ethernet on sama7g5ek
board which is broken at the moment.
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Update and fixes for sl28, lx2, pblimage generation for some powerpc
products
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The F1C100s DT contains the wrong compatible string for the watchdog,
which breaks reset functionality.
Updating the DT goes via the Linux tree, but to allow reset
functionality meanwhile (useful for development!), disable SYSRESET for
now, to let the old-fashioned watchdog driver kick in and provide the
reset_cpu() implementation.
Signed-off-by: Andre Przywara <[email protected]>
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Commit 88998f777531 ("arm: arm926ej-s: Add sunxi code") introduced
the ARM926 version of the code to save and restore some FEL state, to
be able to return to the BROM FEL code after the SPL has run.
However during review a change was made, that happened to mess up the
register restore part, so SCTLR and CPSR ended up with the wrong values,
breaking return to FEL.
Use the same offset that we actually save those registers to, to make
FEL booting actually work on the Lichee Pi Nano.
Signed-off-by: Andre Przywara <[email protected]>
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Enable SPI boot in SPL on SUNIV architecture and use
it in the licheepi nano that uses the F1C100s.
Signed-off-by: Jesse Taube <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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The SUNIV SoCs come with a sun6i-style SPI controller at the base address
of sun4i SPI controller. The module clock of the SPI controller is
missing which leaves us running directly from the AHB clock, which is
set to 200MHz.
Signed-off-by: Icenowy Zheng <[email protected]>
[Icenowy: Original implementation]
Signed-off-by: Jesse Taube <[email protected]>
[Jesse: adaptation to Upstream U-Boot]
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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In contrast to other Allwinner SoCs the F1C100s BROM does not store a
boot source indicator in the eGON header in SRAM. This leaves the SPL
guessing where we were exactly booted from, and for instance trying
the SD card first, even though we booted from SPI flash.
By inspecting the BROM code and by experimentation, Samuel found that the
top of the BROM stack contains unique pointers for each of the boot
sources, which we can use as a boot source indicator.
This patch removes the existing board_boot_order bodge and replace it
with a proper boot source indication function.
The only caveat is that this only works in the SPL, as the SPL header
gets overwritten with the exception vectors, once U-Boot proper takes
over. Always return MMC0 as the boot source, when called from U-Boot
proper, as a placeholder for now, until we find another way.
Signed-off-by: Jesse Taube <[email protected]>
Suggested-by: Samuel Holland <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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Implements SCMI APIs to retrieve the number exposed SCMI clocks using
SCMI_PROTOCOL_ATTRIBUTES messages and the names of the clocks using
SCMI_CLOCK_ATTRIBUTES messages.
This change updates sandbox SCMI clock test driver to manage these
2 new message IDs.
Cc: Lukasz Majewski <[email protected]>
Cc: Sean Anderson <[email protected]>
Cc: Clement Leger <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Signed-off-by: Gabriel Fernandez <[email protected]>
Signed-off-by: Etienne Carriere <[email protected]>
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Updates sandbox SCMI clock driver and tests since enabling CCF will
mandate clock discovery that is all exposed SCMI clocks shall be
discovered at initialization. For this reason, sandbox SCMI clock
driver must emulate all clocks exposed by SCMI server, not only those
effectively consumed by some other U-Boot devices.
Therefore the sandbox SCMI test driver exposes 3 clocks (IDs 0, 1 and 2)
and sandbox SCMI clock consumer driver gets 2 of them.
Cc: Simon Glass <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Signed-off-by: Etienne Carriere <[email protected]>
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Changes devm_scmi_process_msg() first argument from target parent device
to current SCMI device and lookup the SCMI agent device among SCMI device
parents for find the SCMI agent operator needed for communication with
the firmware.
This change is needed in order to support CCF in clk_scmi driver unless
what CCF will fail to find the right udevice related to exposed SCMI
clocks.
This patch allows to simplify the caller sequence, using SCMI device
reference as parameter instead of knowing SCMI uclass topology. This
change also adds some protection in case devm_scmi_process_msg() API
function is called for an invalid device type.
Cc: Lukasz Majewski <[email protected]>
Cc: Sean Anderson <[email protected]>
Cc: Jaehoon Chung <[email protected]>
Cc: Patrick Delaunay <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Signed-off-by: Etienne Carriere <[email protected]>
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As per DT bindings since Linux kernel v5.14, the device tree can define
only 1 SCMI agent node that is named scmi [1]. As a consequence, change
implementation of the SCMI driver test through sandbox architecture to
reflect that.
This change updates sandbox test DT and sandbox SCMI driver accordingly
since all these are impacted.
Cc: Simon Glass <[email protected]>
Reviewed-by: Patrick Delaunay <[email protected]>
Signed-off-by: Etienne Carriere <[email protected]>
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Changes SCMI bindings documentation to relate to Linux kernel
source tree that recently changed the bindings description to YAML
format.
Reviewed-by: Patrick Delaunay <[email protected]>
Signed-off-by: Etienne Carriere <[email protected]>
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To quote the author:
I was looking into the arm64 boot code lately and stumbled upon some
issues. Also Nishanth brought back memories of a lengthy debug session,
which was caused due to U-Boot keeping SErrors masked. As the resulting
patches are all somewhat related, I gathered this series here to address
those problems.
Patches 1 to 3 address exception handling issues, with the SError
enablement being the most prominent fix here.
Patch 4 cleans up asm/io.h. This was on the list before[1], but was
somehow lost when it was intercepted by a shorter version of itself.
Patches 5 and 6 clean up some unnecessarily complicated AArch64 assembly
code.
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The branch_if_master macro jumps to a label if the CPU is the "master"
core, which we define as having all affinity levels set to 0. To check
for this condition, we need to mask off some bits from the MPIDR
register, then compare the remaining register value against zero.
The implementation of this was slighly broken (it preserved the upper
RES0 bits), overly complicated and hard to understand, especially since
it lacked comments. The same was true for the very similar
branch_if_slave macro.
Use a much shorter assembly sequence for those checks, use the same
masking for both macros (just negate the final branch), and put some
comments on them, to make it clear what the code does.
This allows to drop the second temporary register for branch_if_master,
so we adjust all call sites as well.
Also use the opportunity to remove a misleading comment: the macro
works fine on SoCs with multiple clusters. Judging by the commit
message, the original problem with the Juno SoC stems from the fact that
the master CPU *can* be configured to be from cluster 1, so the
assumption that the master CPU has all affinity values set to 0 does not
hold there. But this is already mentioned above in a comment, so remove
the extra comment.
Signed-off-by: Andre Przywara <[email protected]>
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The switch_el macro is a neat contraption to handle cases where we need
different code depending on the current exception level, but its
implementation was longer than needed.
Simplify it by doing just one comparison, then using the different
condition codes to branch to the desired target. PState.CurrentEL just
holds two bits, and since we don't care about EL0, we can use >, =, < to
select EL3, EL2 and EL1, respectively.
Signed-off-by: Andre Przywara <[email protected]>
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asm/io.h is the header file containing the central MMIO accessor macros.
Judging by the header and the comments, it was apparently once copied
from the Linux kernel, but has deviated since then *heavily*. There is
absolutely no point in staying close to the original Linux code anymore,
so just remove the old cruft, by:
- removing pointless Linux history
- removing commented code
- removing outdated comments
- removing unused definitions (for mem_isa)
This massively improves the readability of the file.
Signed-off-by: Andre Przywara <[email protected]>
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In ARMv8 we have the choice between two stack pointers to use: SP_EL0 or
SP_ELx, which is banked per exception level. This choice is stored in
the SP field of PState, and can be read and set via the SPSel special
register. When the CPU takes an exception, it automatically switches to
the SP_ELx stack pointer.
Trusted Firmware enters U-Boot typically with SPSel set to 1, so we use
SP_ELx all along as our sole stack pointer, both for normal operation and
for exceptions.
But if we now for some reason enter U-Boot with SPSel cleared, we will
setup and use SP_EL0, which is fine, but leaves SP_ELx uninitialised.
When we now take an exception, we try to save the GPRs to some undefined
location, which will usually end badly.
To make sure we always have SP_ELx pointing to some memory, set SPSel
to 1 in the early boot code, to ensure safe operation at all times.
Signed-off-by: Andre Przywara <[email protected]>
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The ARMv8 architecture describes the "SError interrupt" as the fourth
kind of exception, next to synchronous exceptions, IRQs, and FIQs.
Those SErrors signal exceptional conditions from which the system might
not easily recover, and are normally generated by the interconnect as a
response to some bus error. A typical situation is access to a
non-existing memory address or device, but it might be deliberately
triggered by a device as well.
The SError interrupt replaces the Armv7 asynchronous abort.
Trusted Firmware enters U-Boot (BL33) typically with SErrors masked,
and we never enable them. However any SError condition still triggers
the SError interrupt, and this condition stays pending, it just won't be
handled. If now later on the Linux kernel unmasks the "A" bit in PState,
it will immediately take the exception, leading to a kernel crash.
This leaves many people scratching their head about the reason for
this, and leads to long debug sessions, possibly looking at the wrong
places (the kernel, but not U-Boot).
To avoid the situation, just unmask SErrors early in the ARMv8 boot
process, so that the U-Boot exception handlers reports them in a timely
manner. As SErrors are typically asynchronous, the register dump does
not need to point at the actual culprit, but it should happen very
shortly after the condition.
For those exceptions to be taken, we also need to route them to EL2,
if U-Boot is running in this exception level.
This removes the respective code snippet from the Freescale lowlevel
routine, as this is now handled in generic ARMv8 code.
Reported-by: Nishanth Menon <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
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The arm64 version of the exception command was just defining the
undefined exception, but actually copied the AArch32 instruction.
Replace that with an encoding that is guaranteed to be and stay
undefined. Also add instructions to trigger unaligned access faults and
a breakpoint.
This brings ARM64 on par with ARM(32) for the exception command.
Signed-off-by: Andre Przywara <[email protected]>
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To quote the author:
This series adds a new errors-only pylint check and adds it to the CI
systems.
It also fixes the current errors in the U-Boot Python code, disabling
errors where it seems necessary.
A small patch to buildman allows it to build sandbox without any changes
to the default config file
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Add a check that new Python code does not regress the pylint score for
any module.
Signed-off-by: Simon Glass <[email protected]>
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At present the default .buildman file written by buildman does not specify
a default toolchain. Add an 'other' line so this works correctly and
sandbox builds run as expected.
Signed-off-by: Simon Glass <[email protected]>
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Add a new 'pylint_err' target which only reports errors, not warnings.
Signed-off-by: Simon Glass <[email protected]>
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Fix pylint errors in all test.
This requires adding a get_spawn() method to the ConsoleBase base, so that
its subclass is happy.
Signed-off-by: Simon Glass <[email protected]>
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Fix two pylint errors in this file.
Note ACTION_SPL_NOT_EXIST is not defined so the dead code can be removed.
Signed-off-by: Simon Glass <[email protected]>
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Fix pylint errors that can be fixed and mask those that seem to be
incorrect.
A complication with binman is that it tries to avoid importing libfdt
(or anything that imports it) unless needed, so that things like help
still work if it is missing.
Note that two tests are duplicated in binman and two others have
duplicate names, so both of these issues are fixed also.
Signed-off-by: Simon Glass <[email protected]>
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Fix pylint errors in this directory.
Signed-off-by: Simon Glass <[email protected]>
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Fix pylint errors that can be fixed and mask those that seem to be
incorrect.
Signed-off-by: Simon Glass <[email protected]>
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