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Enhance the extension board scanning code in sandbox with better error
handling and code organization.
Signed-off-by: Kory Maincent (TI.com) <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Migrate sunxi board extension detection from legacy implementation to
the new UCLASS-based extension board framework.
Signed-off-by: Kory Maincent (TI.com) <[email protected]>
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Clean up and improve code structure in the sunxi CHIP board extension
detection implementation.
Signed-off-by: Kory Maincent (TI.com) <[email protected]>
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Migrate TI board cape detection from legacy extension support to the
new UCLASS-based extension board framework.
Signed-off-by: Kory Maincent (TI.com) <[email protected]>
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Clean up and reorganize cape detection code structure for improved
maintainability and readability.
Signed-off-by: Kory Maincent (TI.com) <[email protected]>
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Introduce UCLASS-based extension board support to enable more
standardized and automatic loading of extension board device tree
overlays in preparation for integration with bootstd and pxe_utils.
Several #if CONFIG_IS_ENABLED are used in cmd/extension_board.c to ease the
development but don't worry they are removed later in the series.
Signed-off-by: Kory Maincent (TI.com) <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Relocate extension board support from cmd/ to boot/ directory in
preparation for converting the extension framework to use UCLASS.
Also improve code style by applying reverse xmas tree ordering.
Signed-off-by: Kory Maincent (TI.com) <[email protected]>
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Add documentation to describe the extension structure.
Signed-off-by: Kory Maincent (TI.com) <[email protected]>
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Disable compulab extension board detection functionality in XPL (eXtended
Program Loader) images to reduce size and complexity in the early boot
stage.
Signed-off-by: Kory Maincent (TI.com) <[email protected]>
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Disable DIP detection functionality in XPL (eXtended Program Loader)
images to reduce size and complexity in the early boot stage.
Signed-off-by: Kory Maincent (TI.com) <[email protected]>
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The CAPE_EEPROM_BUS_NUM configuration option was incorrectly depending
on CMD_EXTENSION, which represents the extension board command. However,
the cape scan functionality can be built and used independently of the
command interface through the SUPPORT_EXTENSION_SCAN option.
Change the dependency from CMD_EXTENSION to SUPPORT_EXTENSION_SCAN to
properly reflect that the I2C bus configuration is needed for the cape
scan function itself, not specifically for the command.
Signed-off-by: Kory Maincent (TI.com) <[email protected]>
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Disable cape detection functionality in xPL images to reduce size and
complexity in the early boot stage.
Signed-off-by: Kory Maincent (TI.com) <[email protected]>
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Add myself as maintainer for the extension board support that was
originally added to track ongoing development and maintenance.
Signed-off-by: Kory Maincent (TI.com) <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Mattijs Korpershoek <[email protected]>
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Commit 65e2c14d5a5a ("binman: btool: mkimage: use Bintool.version")
removed the version argument from the run method but forgot to remove it
from the method docstring, so let's fix this oversight.
Fixes: 65e2c14d5a5a ("binman: btool: mkimage: use Bintool.version")
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-rockchip
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/28119
- New Boards support:
rk3588: MNT Reform2
rk3528: Radxa ROCK 2A/2F
rk3576: ArmSoM Sige1, Luckfox Omni3576, FriendlyElec NanoPi M5,
Radxa ROCK 4D
rk3568: Lunzn FastRhino R66S
- Other board level updates.
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The free running mode is 0 at bit offset 1. User mode is 1 at bit offset
1. Currently, free running mode is 1 at offset 0, which is already the
case thanks to TIME_EN.
So, this essentially does not change the actual value written to the
register as it is TIME_EN | TIMER_FMODE which currently is 0x1 | BIT(0)
= 0b1, and will become 0x1 | (0 << 1) = 0b1.
I checked PX30, RK3128, RK3188, RK3228, RK3288, RK3308, RK3328, RK3368
RK3506, RK3562 and RK3568 TRMs.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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eMMC erase and write support on RK3528 is somewhat unreliable, sometime
e.g. mmc erase and write commands will fail with an error.
Use the delay line lock value for half card clock cycle, DLL_LOCK_VALUE,
to set a manual xx_TAP_VALUE to fix the unreliable eMMC support.
This is only enabled for RK3528, remaining SoCs still use the automatic
tap value, (DLL_LOCK_VALUE * 2) % 256, same value we configure manually
for RK3528.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The free running mode is 0 at bit offset 1. User mode is 1 at bit offset
1. Currently, free running mode is 1 at offset 0, which is already the
case thanks to TIME_EN.
So, this essentially does not change the actual value written to the
register as it is TIME_EN | TIMER_FMODE which currently is 0x1 | BIT(0)
= 0b1, and will become 0x1 | (0 << 1) = 0b1.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Ensure that the spi/sfc node for SPI flash is aviliable during pre-reloc
phase so that env can successfully be loaded from SPI Flash.
No boards with these SoCs seem to be affected as there is no default use
of ENV_IS_IN_SPI_FLASH=y.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The only difference with the implementation in spl_common.c is that we
check whether the timer has already been enabled. Considering this is
running in SPL, the first stage on RK3036, I feel like it's guaranteed
to not be enabled by default. No public TRM though and I don't have
access to an RK3036 device so take this as a guess.
Size of SPL binary increases by 8B for evb-rk3036.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Boot devices are being probed when SPL boot order is determined. This
may delay boot slightly and can prevent booting from SPI Flash on boards
that use same pins for SPI Flash and eMMC due to pinctrl being applied
prior to booting.
Instead defer probe of the boot device until SPL try to load image from
the boot device by using uclass_find_device_by_of_offset() instead of
the get variant.
Signed-off-by: Jonas Karlman <[email protected]>
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Instead of redefining what is essentially the same code in
secure_timer_init, let's simply use rockchip_stimer_init from
spl_common.o instead.
This increases the size of the TPL by 16B, due to the added check of
STIMER already being enabled. Experimentally, STIMER is not already
enabled when in TPL.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Add support for MNT Reform2, it works as a carrier board
with a Firefly iCore-3588Q SoM.
Specification:
- Rockchip RK3588
- LPDDR5X 16/32 GB
- eMMC 128/256 GB
- HDMI Type A out x 1
- USB 3.0 Host x 1
- USB-C 3.0 with DisplayPort AltMode
- PCIE M.2 E Key for Wireless connection
- PCIE M.2 M Key for NVME connection
- DSI to eDP panel
- 1Gb Ethernet w/ Microchip KSZ9310 PHY
Tested using Fedora boot on USB stick and eMMC.
Signed-off-by: Peter Robinson <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The Sige1 is a single board computer developed by ArmSoM, based on the
Rockchip RK3528A SoC.
Add support for the ArmSoM Sige1 board.
Features tested on a ArmSoM Sige1 v1.1:
- SD-card boot
- eMMC boot
- Ethernet
- USB host (with pending DT changes)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Lunzn Fastrhino R66S is a high-performance mini router.
Specification:
- Rockchip RK3568
- 1/2GB LPDDR4 RAM
- SD card slot
- 2x USB 3.0 Port
- 2x 2500 Base-T (PCIe, r8125b)
- 12v DC Jack
Signed-off-by: Tianling Shen <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The Sige1 is a single board computer developed by ArmSoM, based on the
Rockchip RK3528A SoC.
Add initial device tree for the ArmSoM Sige1 board.
Signed-off-by: Jonas Karlman <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 1c6b12ef9575bc18dad2393e50ca1ebf96f0a0c8 ]
(cherry picked from commit 3ba04aa78ba71faab4a339f5ab15bc81a3e0a51b)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Anbernic RG353M is hardware compatible with RG353P. Only the form-factor
differs. So only one DTS is created for both machines with
"Anbernic RG353P" as default model. If a RG353M is detected, the model
should be overwritten with the correct name.
Actually, it's overwritten with "Anbernic" only making the process of
machine detection a little harder.
However, to determine the size of the string "Anbernic RG353M", it is
sizeof() which is used resulting in obtaining the size of the pointer
(which is 8 bytes on ARM64) not the size of the pointed string.
strlen() should be used instead.
Signed-off-by: David Barbion <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The ROCK 2 Family is a high-performance SBC (Single Board Computer)
developed by Radxa, based on the Rockchip RK3528A.
The Radxa E20C shares some board characteristics with the ROCK 2 family
boards.
Add support for the ROCK 2A and 2F boards. The radxa-e20c-rk3528 target
is also extended to support booting ROCK 2 boards.
Features tested on a ROCK 2A v1.202:
- SD-card boot
- Ethernet
- USB host (with pending DT changes)
Features tested on a ROCK 2F v1.016:
- SD-card boot
- eMMC boot
- USB host (with pending DT changes)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Forcing all those symbols on means we cannot make the binary smaller or
with unnecessary features or drivers disabled. This is especially useful
for security, auditing and certification where less code built means
less to look at (and less surface attack) and less to patch, but also
for making binary images smaller which typically means faster boot.
It is possible to have boards without MMC, NAND or SPI flashes, without
anything on SPI or I2C buses, nothing to control over PWM or GPIO or for
which we have no interest in regulator control or serial output so make
it possible to remove all that if desired.
No intended change in default selected symbols.
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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The ROCK 2A and ROCK 2F is a high-performance single board computer
developed by Radxa, based on the Rockchip RK3528A SoC.
Add initial device tree for the Radxa ROCK 2A and ROCK 2F boards.
Signed-off-by: Jonas Karlman <[email protected]>
Tested-by: Yao Zi <[email protected]>
Reviewed-by: Nicolas Frattaroli <[email protected]>
Tested-by: Nicolas Frattaroli <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
[ upstream commit: 5b71b3d9aa61626d6a93ed2f761a748aa2ecfa95 ]
(cherry picked from commit d272bc0c747a5af49cf98140ebd25a702f84ab52)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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FriendlyElec NanoPi M5 with Rockchip RK3576 SoC (4x Cortex-A72,
4x Cortex-A53, Mali-G52 MC3 GPU, 6 TOPS NPU).
Features tested on a NanoPi M5 2411:
- SD-card boot
- SPI flash boot
- Ethernet
- LEDs
- PCIe/NVMe
- USB HOST/OTG
- USER button
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Luckfox Omni3576 Carrier Board with Core3576 Module, powered by the
Rockchip RK3576 SoC with four Cortex-A72 cores, four Cortex-A53 cores,
and a Mali-G52 MC3 GPU.
Features tested with a Core3576 Rev1.1 on a Omni3576 carrier board:
- SD-card boot
- eMMC boot
- LED
- PCIe/NVMe
- USB2.0 HOST
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The Radxa ROCK 4D is a compact single-board computer (SBC) featuring
numerous top-tier functions, features, and expansion options.
Equipped with the Rockchip RK3576 or RK3576J SoC, the ROCK 4D boasts an
octa-core CPU (4x Cortex-A72 + 4x Cortex-A53), Mali-G52 GPU, and a
powerful 6 TOPS NPU, making it ideal for AI and multimedia tasks.
Features tested on a Radxa ROCK 4D v1.112:
- SPI Flash boot
- Ethernet
- PCIe/NVMe
- USB host
ROCK 4D boards with SPI Flash is configured to boot from FSPI0->UFS->USB,
or directly from USB when the MASKROM button is pressed, booting
directly from SD-card is not possible on these boards.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The bootsource ids reported by BootROM of RK3576 for SPI NOR and USB
differs slightly compared to prior SoCs:
- Booting from sfc0 (ROCK 4D) report the normal bootsource id 0x3.
- Booting from sfc1 M1 (NanoPi M5) report a new bootsource id 0x23.
- Booting from sfc1 M0 has not been tested (no board using this config).
- Booting from USB report a new bootsource id 0x81.
Add a RK3576 specific read_brom_bootsource_id() function to help decode
the new bootsource id values and the required boot_devices mapping of
sfc0 and sfc1 to help support booting from SPI flash on RK3576.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The bootsource ids reported by BootROM of RK3528 for e.g. USB differs
compared to prior SoCs:
- Booting from USB report a new bootsource id 0x81.
Add a RK3528 specific read_brom_bootsource_id() function to help decode
this new bootsource id value to help support booting from USB on RK3528.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The bootsource ids reported by BootROM of RK3528 and RK3576 for e.g.
SPI NOR and USB differs slightly compared to prior SoCs:
- Booting from sfc0 (ROCK 4D) report the normal bootsource id 0x3.
- Booting from sfc1 M1 (NanoPi M5) report a new bootsource id 0x23.
- Booting from sfc1 M0 has not been tested (no board using this config).
- Booting from USB report a new bootsource id 0x81 on RK3528 and RK3576.
Add a helper function to read the bootsource id. This helper function
will be used to translate the new values to the common BROM_BOOTSOURCE
enum values on RK3528 and RK3576.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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SFC after version 8 supports dtr mode, so the IO is the binary output of
the controller clock.
Signed-off-by: Jon Lin <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The commit f8cb3fde935e ("arm: dts: rockchip: Fix eMMC write on RK3528")
added a missing mmc-hs200-1_8v prop to boart u-boot.dtsi.
Remove this boart u-boot.dtsi mmc-hs200-1_8v prop now that the board dt
from dts/upstream after the v6.17-dts sync includes this prop.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Update rk3326-u-boot.dtsi to include OTP in U-Boot pre-reloc phase for
checkboard() to be able to read information about the running SoC model
and variant from OTP and print it during boot:
U-Boot 2025.07 (Jul 13 2025 - 10:07:16 +0000)
Model: ODROID-GO Super
SoC: RK3326
DRAM: 1 GiB (total 1022 MiB)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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I have the ORDOID-GO Super variant of this board. Add myself as a
reviewer to help review future patches targeting this device.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Enable the default commands and some more useful commands that can be
useful to determin the state of the board from U-Boot CLI.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Use default-state prop to ensure that the blue heartbeat LED turns on
at boot to inticate that U-Boot proper has been reached.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Enable Kconfig options to support RockUSB, buttons, LEDs and RNG
featured on the board or SoC.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Change to dynamically select what storage media to use for the U-Boot
environment depending on from what storage media the FIT images was
loaded from, fall back to use env from nowhere.
U-Boot SPL 2025.07 (Jul 13 2025 - 10:07:16 +0000)
Trying to boot from MMC1
...
Loading Environment from MMC... Reading from MMC(0)...
or
U-Boot SPL 2025.07 (Jul 13 2025 - 10:07:16 +0000)
Trying to boot from SPI
...
Loading Environment from SPIFlash...
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Include FDTs for all three board variants in the FIT image and adjust
the board selection code to use correct FDT in U-Boot proper.
E.g. use the odroid-go3 DT for a ODROID-GO Super device:
U-Boot 2025.07 (Jul 13 2025 - 10:07:16 +0000)
Model: ODROID-GO Super
DRAM: 1 GiB (total 1022 MiB)
PMIC: RK817 (on=0x80, off=0x08)
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The ODROID GO2 devices come with onboard SPI flash, add support for
using the SPI flash.
The BootROM seem to expect the IDBlock at 64 KiB offset compared to the
typical 32 KiB offset from start of SPI flash used by other SoCs.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Include the RK817 PMIC in SPL and enable Kconfig options to power off
the handheld gaming device when it was powered on due to a power cable
plug-in event:
DDR3, 333MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
out
Power Off due to plug-in event
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Include pinctrl nodes and props for sdmmc, sfc and uart in SPL to ensure
pins are configured according to the device tree.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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Drop SPL_DRIVERS_MISC, it is not needed/used on these devices.
Enable SPL_FIT_SIGNATURE to ensure the integrity of the FIT images
that are loaded into memory.
Change SPL_MAX_SIZE to 256 KiB, similar to other SoCs where TF-A is
loaded at 0x40000 offset from start of DRAM.
Enable SPL_DM_SEQ_ALIAS to ensure device aliases are applied in SPL.
Drop use of SPL_TINY_MEMSET, there is plenty room for the normal memset.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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The handheld gaming devices that this defconfig tagets does not contain
an Ethernet port, remove Ethernet related Kconfig options.
They also do not contain any pwm-regulator in their DTs, remove the
PWM regulator related Kconfig option.
Display/video is not supported in U-Boot, remove all display/video
related Kconfig options.
There is no real functional change expected with these options removed.
Signed-off-by: Jonas Karlman <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
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