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2021-08-09arm: imx8ulp: Allocate DCNANO and MIPI_DSI to AD domainYe Li
Configure DCNANO and MIPI_DSI to be controlled by AD for single boot Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2021-08-09arm: iMX8ULP: Add boot device relevant functionsYe Li
Read from ROM API to get current boot device. Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2021-08-09arm: imx8ulp: Probe the S400 MU device in arch initYe Li
Need probe the S400 MU device in arch_cpu_init_dm, so we can use S400 API in u-boot Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2021-08-09imx8ulp: unify rdc functionsPeng Fan
Unify rdc function to rdc.c Update soc.c to use new rdc function Signed-off-by: Peng Fan <[email protected]>
2021-08-09arm: imx8ulp: release trdc and assign lpav from RTD to APDPeng Fan
Rlease LPAV from RTD to APD Release gpu2D/3D to APD Set TRDC MBC2 MEM1 for iomuxc0 access Since upower depends AP/M33 SW to configure IOMUX for its PMIC i2c and MODE pins. we have to open iomuxc0 access for A35 core (domain 7) in single boot. Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Ye Li <[email protected]>
2021-08-09arm: imx8ulp: add trdc release requestPeng Fan
Add TRDC release request, then we could configure resources to be accessible by A35 Domain. Signed-off-by: Peng Fan <[email protected]>
2021-08-09arm: imx8ulp: add rdc supportPeng Fan
There is xrdc inside i.MX8ULP, we need to configure permission to make sure AP non-secure world could access the resources. Signed-off-by: Peng Fan <[email protected]>
2021-08-09arm: imx8ulp: release and configure XRDC at early phaseYe Li
Since S400 will set the memory of SPL image to R/X. We can't write to any data in SPL image. 1. Set the parameters save/restore only for u-boot, not for SPL. to avoid write data. 2. Not use MU DM driver but directly call MU API to send release XRDC to S400 at early phase. 3. Configure the SPL image memory of SRAM2 to writable (R/W/X) Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2021-08-09drivers: misc: s400_api: Update API for fuse read and writeYe Li
Add API to support fuse read and write Signed-off-by: Ye Li <[email protected]>
2021-08-09drivers: misc: imx8ulp: Update S400 API for release RDCYe Li
The RDC API is updated to add a field for XRDC or TRDC Signed-off-by: Ye Li <[email protected]>
2021-08-09drivers: misc: imx8ulp: Add S400 API for image authenticationYe Li
Add S400 API for image authentication Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2021-08-09drivers: misc: s400_api: Update S400_SUCCESS_IND to 0xd6Ye Li
According to latest S400 API doc, the the success indicate value is changed to 0xd6. So update the driver codes. Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2021-08-09arm: imx8ulp: Update the reset vector in u-bootYe Li
Because we have set reset vector to ATF in SPL, have to set it back to ROM for any reset in u-boot Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2021-08-09arm: imx8ulp: disable wdog3Peng Fan
Disable wdog3 which is configured by ROM Signed-off-by: Peng Fan <[email protected]>
2021-08-09arm: imx8ulp: Enable full L2 cache in SPLYe Li
SRAM2 is half L2 cache and default to SRAM after system boot. To enable the full l2 cache (512KB), it needs to reset A35 to make the change happen. So re-implement the jump entry function in SPL: 1. configure the core0 reset vector to entry (ATF) 2. enable the L2 full cache 3. reset A35 So when core0 up, it runs into ATF. And we have 512KB L2 cache working. Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2021-08-09arm: imx8ulp: soc: Change to use CMC1 to get bootcfgYe Li
CMC1 also has a MR register for bootcfg Signed-off-by: Ye Li <[email protected]>
2021-08-09drivers: mmc: fsl_esdhc_imx: support i.MX8ULPPeng Fan
i.MX8ULP reuse same SDHC IP as i.MX8M, so follow i.MX8M code logic. Signed-off-by: Peng Fan <[email protected]>
2021-08-09arm: imx8ulp: add clock supportPeng Fan
Add i.MX8ULP clock support Signed-off-by: Peng Fan <[email protected]>
2021-08-09driver: serial: fsl_lpuart: support i.MX8ULPPeng Fan
i.MX8ULP lpuart has same register layout as i.MX7ULP and i.MX8 Signed-off-by: Peng Fan <[email protected]>
2021-08-09pinctrl: Add pinctrl driver for imx8ulpYe Li
Add pinctrl driver for i.MX8ULP Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2021-08-09net: fec_mxc: support i.MX8ULPPeng Fan
Support i.MX8ULP in fec_mxc Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Ramon Fried <[email protected]>
2021-08-09driver: misc: Add MU and S400 API to communicate with SentinelYe Li
Add MU driver and S400 API. Need enable MISC driver to work Signed-off-by: Ye Li <[email protected]>
2021-08-09arm: imx: move container Kconfig under mach-imxPeng Fan
Since i.MX8 and i.MX8ULP reuse common container, so move the Kconfig public to both. Signed-off-by: Peng Fan <[email protected]>
2021-08-09arm: imx8ulp: add container supportYe Li
i.MX8ULP support using ROM API to load container image, it use same ROM API as i.MX8MN/MP, and use same container format as i.MX8QM/QXP. Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2021-08-09arm: imx: parse-container: guard included header filesPeng Fan
Guard included sci.h with CONFIG_AHAB_BOOT to avoid build failure for i.MX8ULP Signed-off-by: Peng Fan <[email protected]>
2021-08-09arm: imx8: Move container image header file to mach-imxYe Li
Since the container is shared among i.MX platforms, move its header file to mach-imx Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2021-08-09arm: imx8: Move container parser and image to mach-imx common folderYe Li
Since we will re-use the container parser on imx8ulp, move the codes to mach-imx Signed-off-by: Ye Li <[email protected]>
2021-08-09arm: imx: basic i.MX8ULP supportPeng Fan
Add basic i.MX8ULP support For the MMU part, Using a simple way the calculate the MMU size to avoid default heavy calcaulation. And align address and size in the table settings to 2MB or 4GB as much as possible. So we can reduce the 4K page allocations in MMU table which will spends much time in create the page table Signed-off-by: Ye Li <[email protected]> Signed-off-by: Peng Fan <[email protected]>
2021-08-09imx: imx8ulp: add get reset causePeng Fan
Add get reset cause function to show what triggerred reset. Signed-off-by: Peng Fan <[email protected]>
2021-08-09arm: imx8ulp: support print cpu infoPeng Fan
Support print cpu info. the clock function has not been added, it will be added in following patches. Signed-off-by: Peng Fan <[email protected]>
2021-08-09arm: imx: sys_proto: move boot mode define to common headerPeng Fan
These defines could be reused by i.MX8ULP, so move them to common header. Signed-off-by: Peng Fan <[email protected]>
2021-08-09arm: imx: add i.MX8ULP cpu type and helperPeng Fan
Add i.MX8ULP cpu type and helpers. Signed-off-by: Peng Fan <[email protected]>
2021-08-09arm: imx: add i.MX8ULP basic Kconfig optionPeng Fan
Add i.MX8ULP related basic Kconfig option, which will be used later. Signed-off-by: Peng Fan <[email protected]>
2021-08-09board: gateworks: venice: add board model to dtTim Harvey
Add the specific board model from EEPROM config to the device-tree to make it easier to access from Linux userspace. Signed-off-by: Tim Harvey <[email protected]>
2021-08-09configs: imx8mm_venice_defconfig: remove unused SPL featuresTim Harvey
remove unused SPL features to shink the size of the SPL which otherwise would no longer fit into IMX8M Mini OCRAM. Signed-off-by: Tim Harvey <[email protected]>
2021-08-09mx28evk: Convert to driver modelFabio Estevam
Make the conversion to driver model as it is mandatory. Successfully tested booting Linux from the SD card. Dropped support for networking and splash screen as these need to be properly converted to DM and tested. Signed-off-by: Fabio Estevam <[email protected]>
2021-08-09board: ge: bx50v3: Add PCIe reset to DTSebastian Reichel
Add PCIe reset gpio to the Bx50v3 devicetree and get get rid of CONFIG_PCIE_IMX_PERST_GPIO. Signed-off-by: Sebastian Reichel <[email protected]>
2021-08-09mx7dsabresd: Select CONFIG_IMX_HABFabio Estevam
Select CONFIG_IMX_HAB so that the "hab_status" command becomes available, which is useful for checking if the chip has been correctly setup to run in secure boot mode. Signed-off-by: Fabio Estevam <[email protected]>
2021-08-09board: gateworks: venice: add imx8mm-gw7902 supportTim Harvey
The GW7902 is based on the i.MX 8M Mini / Nano SoC featuring: - LPDDR4 DRAM - eMMC FLASH - Gateworks System Controller - LTE CAT M1 modem - USB 2.0 HUB - M.2 Socket with USB2.0, PCIe, and dual-SIM - IMX8M FEC - PCIe based GbE - RS232/RS485/RS422 serial transceiver - GPS - CAN bus - WiFi / Bluetooth - MIPI header (DSI/CSI/GPIO/PWM/I2S) - PMIC Do the following to add support for it: - add dts - add PMIC config Signed-off-by: Tim Harvey <[email protected]>
2021-08-09board: gateworks: venice: add board model/serial# to envTim Harvey
Add board model/serial# strings to env. Move the creation of the strings to gsc_read() and the display of the info into gsc_info() so they are available to U-Boot proper. Signed-off-by: Tim Harvey <[email protected]>
2021-08-09board: gateworks: venice: use bus numbers vs namesTim Harvey
replace looking up i2c bus name by bus number and define bus numbers and eeprom address with #defines. Signed-off-by: Tim Harvey <[email protected]>
2021-08-09board: gateworks: venice: get mem size from dtTim Harvey
Get mem size from dt which SPL updated per EEPROM config. Signed-off-by: Tim Harvey <[email protected]>
2021-08-09arm: dts: imx8mm-venice-gw7901: use common u-boot dtsiTim Harvey
Use the common imx8mm-u-boot.dtsi Signed-off-by: Tim Harvey <[email protected]>
2021-08-09arm: dts: imx8mm-venice-gw700x: fix fifo-depth phy propsTim Harvey
Replace the deprecated 'tx-fifo-depth' and 'rx-fifo-depth' properties not supported by U-Boot drivers/net/phy/dp83867.c with the proper 'ti,fifo-depth' property. Signed-off-by: Tim Harvey <[email protected]>
2021-08-09arm: dts: imx8mm-venice-gw71xx: fix USB OTG VBUSTim Harvey
The GW71xx has a USB Type-C connector with USB 2.0 signaling. GPIO1_12 is the power-enable to the TPS25821 Source controller and power switch responsible for monitoring the CC pins and enabling VBUS. Therefore GPIO1_12 must always be enabled and the vbus output enable from the IMX8MM can be ignored. To fix USB OTG VBUS enable a pull-up on GPIO1_12 to always power the TPS25821 and change the regulator output to GPIO1_10 which is unconnected. Signed-off-by: Tim Harvey <[email protected]>
2021-08-09warp: Use the correct symbol for CONFIG_IMX_HABFabio Estevam
The intention of commit d714a75fd4dc ("imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HAB") was to convert from CONFIG_SECURE_BOOT to CONFIG_IMX_HAB, but it replaced with an extra "_" character. Fix it by using the correct CONFIG_IMX_HAB symbol. Fixes: d714a75fd4dc ("imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HAB") Signed-off-by: Fabio Estevam <[email protected]>
2021-08-09imx: ventana: add support for GW54xx-G revisionTim Harvey
The GW54xx-G revision has the foolowing changes: - replaces the EOL GbE PHY with an updated part (requires an enable pin) - replaces the EOL analog video decoder with an updated part (requires dt prop) - add power control to miniPCIe socket Signed-off-by: Tim Harvey <[email protected]>
2021-08-09imx: ventana: add support for GW53xx-G revisionTim Harvey
The GW53xx-G revision has the foolowing changes: - replaces the EOL GbE PHY with an updated part (requires an enable pin) - replaces the EOL analog video decoder with an updated part (requires dt prop) - add power control to miniPCIe socket Signed-off-by: Tim Harvey <[email protected]>
2021-08-09imx: ventana: add GW5913 supportTim Harvey
The GW5913 is a Single Board Computer based on the NXP i.MX6Q/DL SoC with the following features: - DDR3 DRAM - NAND FLASH (256MiB or 2048MiB) - Gateworks System Periperhal Controller - front panel LED's - front panel pushbutton - Digital I/O connector (I2C/GPIO/UART) - u-blox Zoe-M8Q GPS - 1x RJ45 GbE - 1x MiniPCIe socket with PCIe USB 2.0 and nanoSIM socket - Passive PoE and wide-range DC power supply Signed-off-by: Tim Harvey <[email protected]>
2021-08-09imx: ventana: add GW5912 supportTim Harvey
The GW5912 is a Single Board Computer based on the NXP i.MX6Q/DL SoC with the following features: - DDR3 DRAM - NAND FLASH (256MiB or 2048MiB) - microSD socket - Gateworks System Periperhal Controller - front panel LED's - front panel pushbutton - RS232 connector (2x UARTs) - CAN/RS485 connector - Digital I/O connector (I2C/GPIO) - SPI connector - u-blox Zoe-M8Q GPS - LIS2DE12 Accellerometer - 1x FEC GbE RJ45 with 802.3at Active PoE - 1x PCI GbE RJ45 with Passive PoE - 5x MiniPCIe socket with PCIe/USB 2.0 - 1x MiniPCIe socket with PCIe/USB 2.0 and SIM socket - Aux power input with wide-range DC power supply Signed-off-by: Tim Harvey <[email protected]>
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