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2021-07-27arm: dts: k3-j7200-main: Add DT node for torrent serdesAswath Govindraju
Add DT node for torrent serdes. This is in sync with v5.13 Linux Kernel. Signed-off-by: Aswath Govindraju <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lokesh Vutla <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-07-27ARM: dts: k3-j721e: Add support for USB3 in USB0 instanceKishon Vijay Abraham I
Configure the parent clock of wiz3_pll0_refclk to the internal clock required for USB3 to be functional and also remove "ti,usb2-only" property as it now supports USB3 mode. This has properties specific to u-boot on top of DT present in v5.13 of Linux Kernel. Signed-off-by: Jean-Jacques Hiblot <[email protected]> Signed-off-by: Vignesh Raghavendra <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lokesh Vutla <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-07-27board: ti: j721e: Add support for probing and configuring Torrent serdes on ↵Aswath Govindraju
J7200 Add support for probing and configuring Torrent serdes on J7200. Signed-off-by: Aswath Govindraju <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lokesh Vutla <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-07-27phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoCJean-Jacques Hiblot
Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures three clock selects (pll0, pll1, dig) and supports resets for each of the lanes. This is an adaptation of the linux driver. Signed-off-by: Jean-Jacques Hiblot <[email protected]> Signed-off-by: Vignesh Raghavendra <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lokesh Vutla <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-07-27phy: cadence: Add driver for Torrent SERDESAswath Govindraju
Add driver for Torrent SERDES. Signed-off-by: Aswath Govindraju <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lokesh Vutla <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-07-27phy: cadence: Add driver for Sierra PHYAlan Douglas
Add a Sierra PHY driver with PCIe and USB support. This driver is a port from the mainline linux driver. The PHY has multiple lanes, which can be configured into groups, and a generic PHY device is created for each group. There are two resets controlling the overall PHY block, one to enable the APB interface for programming registers, and another to enable the PHY itself. Additionally there are resets for each PHY lane. The PHY can be configured in hardware to read register settings from ROM, or they can be written by the driver. The sequence of operation on startup is to enable the APB bus, write the PHY registers (if required) for each lane group, and then enable the PHY. Each group of lanes can then be individually controlled using the power_on()/ power_off() function for that generic PHY One difference with the linux driver is that the PHY is always reset after it is powered-on. This is because role switching is not supported in u-boot and the cable orientation is handled by the PHY reset. Signed-off-by: Jean-Jacques Hiblot <[email protected]> Signed-off-by: Alan Douglas <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Vignesh Raghavendra <[email protected]> Signed-off-by: Lokesh Vutla <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-07-27dt-bindings: ti-serdes-mux: Add defines for AM64 SoCKishon Vijay Abraham I
AM64 has a single lane SERDES which can be configured to be used with either PCIe or USB. Define the possilbe values for the SERDES function in AM64 SoC here. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lokesh Vutla <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-07-27dt-bindings: phy: cadence-torrent: Add defines for refclk driverKishon Vijay Abraham I
Add defines for refclk driver used to route the refclk out of torrent SERDES. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lokesh Vutla <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-07-27dt-bindings: phy: Add defines for AM64 SERDES WrapperKishon Vijay Abraham I
Add defines for AM64 SERDES Wrapper. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lokesh Vutla <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-07-27dt-bindings: phy: Add definitions for additional phy typesAswath Govindraju
Add definitions for additional phy types that's used specifically for Torrent SERDES. Signed-off-by: Aswath Govindraju <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lokesh Vutla <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-07-27dm: test: Add test case to check node name ignoring unit addressKishon Vijay Abraham I
Add test to check node name ignoring unit address. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lokesh Vutla <[email protected]> Reviewed-by: Simon Glass <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-07-27dm: core: Add helper to compare node namesKishon Vijay Abraham I
Add helper to compare node names. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lokesh Vutla <[email protected]> Reviewed-by: Simon Glass <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-07-27configs: am335x_evm: Support GbE PHYsPaul Barker
The SanCloud BeagleBone Enhanced (BBE) includes a Gigabit Ethernet PHY. Signed-off-by: Paul Barker <[email protected]>
2021-07-27arm: dts: Import am335x-sancloud-bbe devicetreePaul Barker
This device tree is imported from Linux 5.13.1 and enabled via the am335x board file and the am335x evm defconfig. Signed-off-by: Paul Barker <[email protected]>
2021-07-27arm: dts: Resync BeagleBone device treesPaul Barker
These device trees are updated to match the versions in Linux 5.13.1. The tick-timer entry in am335x-bone-common.dtsi is preserved. Signed-off-by: Paul Barker <[email protected]>
2021-07-27dt-bindings: Resync omap & am33xx pinctrl bindingsPaul Barker
These headers are updated to match the versions in Linux 5.13.1. Signed-off-by: Paul Barker <[email protected]>
2021-07-27configs: j7200_evm_*_defconfig: Enable configs for HS400 supportAswath Govindraju
Enable configs to add support for HS400 speed mode. Signed-off-by: Aswath Govindraju <[email protected]> Signed-off-by: Lokesh Vutla <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-07-27arm: dts: k3-j7200-main: Add support for HS400 and update delay select ↵Aswath Govindraju
values for MMCSD subsystems HS400 speed mode is now supported in J7200 SoC[1]. Therefore add mmc-hs400-1_8v tag in sdhci0 device tree node. Also update the delay values for various speed modes supported, based on the revised january 2021 J7200 datasheet[2]. [1] - section 12.3.6.1.1 MMCSD Features, in https://www.ti.com/lit/ug/spruiu1a/spruiu1a.pdf, (SPRUIU1A – JULY 2020 – REVISED JANUARY 2021) [2] - https://www.ti.com/lit/ds/symlink/dra821u.pdf, (SPRSP57B – APRIL 2020 – REVISED JANUARY 2021) Signed-off-by: Aswath Govindraju <[email protected]> Signed-off-by: Lokesh Vutla <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-07-27mmc: sdhci_am654: Read ti, strobe-sel property from device treeAswath Govindraju
Read the strobe select value from the device tree property ti,strobe-sel, required for HS400 speed mode Fixes: a20008eabd95 ("mmc: am654_sdhci: Add Support for configuring PHY in J721e") Signed-off-by: Aswath Govindraju <[email protected]> Signed-off-by: Lokesh Vutla <[email protected]> Reviewed-by: Jaehoon Chung <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-07-27mmc: sdhci: Write to HOST_CONTROL2 register for HS400 speed modeFaiz Abbas
Enable HS400 speed mode by writing to HOST_CONTROL2 register. Signed-off-by: Faiz Abbas <[email protected]> Signed-off-by: Aswath Govindraju <[email protected]> Signed-off-by: Lokesh Vutla <[email protected]> Acked-by: Jaehoon Chung <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-07-27snow: Enable unit testsSimon Glass
It is useful to have a board with unit tests enabled, to check that this does not break. Let's choose snow, since it is not under active development and it is glorious. Signed-off-by: Simon Glass <[email protected]> Reviewed-by: Jaehoon Chung <[email protected]> Signed-off-by: Minkyu Kang <[email protected]>
2021-07-27test: Fix size_t formats in strlcat testSimon Glass
Some of the printf() formats do not match their types. Fix this. Reported-by: Minkyu Kang <[email protected]> Signed-off-by: Simon Glass <[email protected]> Signed-off-by: Minkyu Kang <[email protected]>
2021-07-27samsung: exynos: Convert SROMC interface to a driverSimon Glass
Add a bus driver for this and use it to configure the bus parameters for the Ethernet interface. Drop the old pre-driver-model code. Switch over to use driver model for Ethernet. Signed-off-by: Simon Glass <[email protected]> Reviewed-by: Jaehoon Chung <[email protected]> Signed-off-by: Minkyu Kang <[email protected]>
2021-07-26configs: Resync with savedefconfigTom Rini
Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <[email protected]>
2021-07-26Prepare v2021.10-rc1v2021.10-rc1Tom Rini
Signed-off-by: Tom Rini <[email protected]>
2021-07-26Merge tag 'xilinx-for-v2021.10-rc1' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.10-rc1 xilinx: - Use default ENVL_NOWHERE configuration - Add support for handling compressed kernels zynqmp: - SPL malloc size extension - USB2.0 for zc1751 dc2 - Fix USB3.0 nodes - Handle lpd_lsbus clock - Cleanup macros around SYSRESET versal: - Remove PBSIZE macro zynq_sdhci: - Tap delay fixups net: - Add support for MRMAC
2021-07-26arm64: zynqmp: Move USB3 PHY properties from DWC3 node to USB nodeManish Narani
Move the PHY properties from DWC3 node to USB node in ZynqMP DTs as here the USB3 PHY used is PSGTR, which is connected to Xilinx USB core. This PHY initialization should be handled from Xilinx USB core as the prerequisite register configurations are done here only. Signed-off-by: Manish Narani <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2021-07-26xilinx: Define kernel_comp_addr_r,kernel_comp_size env variablesRaju Kumar Pothuraju
Add kernel_comp_addr_r, kernel_comp_size env variables for zynqmp and versal to be able to use the compressed kernel Image(.gz,.bz2,.lzma,.lzo) using booti command. Signed-off-by: Raju Kumar Pothuraju <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2021-07-26arm64: versal: Drop default definitions of CONFIG_SYS_PBSIZEMichal Simek
It is default value which had been converted by commit 432e39806805 ("include/configs: drop default definitions of CONFIG_SYS_PBSIZE"). That's why also remove it. Signed-off-by: Michal Simek <[email protected]>
2021-07-26arm64: zynqmp: Enable reset and poweroff via sysreset frameworkMichal Simek
reset and poweroff are called via hooks in psci driver which is going around sysreset framework that's why enable sysreset drivers and do reset and poweroff via this framework. Using this flow will allow us to call SYSTEM_WARM_RESET based on psci 1.1 spec which can be calles with reset -w command. Signed-off-by: Michal Simek <[email protected]>
2021-07-26arm64: zynqmp: Do not define do_reset() if sysreset is enabledMichal Simek
The SPL can also be compiled with sysreset drivers just fine, so update the condition to cater for that option. The same change was done by commit efa1a62ad2dd ("ARM: imx8m: Do not define do_reset() if sysreset is enabled"). Signed-off-by: Michal Simek <[email protected]>
2021-07-26psci: Do not define do_poweroff() if CONFIG_SYSRESET_CMD_POWEROFF is enabledMichal Simek
CONFIG_SYSRESET_CMD_POWEROFF defines do_poweroff() in sysreset-uclass.c that's why don't define it twice when both CONFIG_SYSRESET_CMD_POWEROFF and CONFIG_CMD_POWEROFF are enabled. CONFIG_SYSRESET_CMD_POWEROFF depends on CONFIG_CMD_POWEROFF. Signed-off-by: Michal Simek <[email protected]>
2021-07-26xilinx: versal: Enable Xilinx AXI MRMACAshok Reddy Soma
Enable Xilinx AXI MRMAC for Versal platforms. Signed-off-by: Ashok Reddy Soma <[email protected]> Reviewed-by: Simon Glass <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2021-07-26net: xilinx: axi_mrmac: Add MRMAC driverAshok Reddy Soma
Add support for xilinx multirate(MRMAC) ethernet driver. This driver uses multichannel DMA(MCDMA) for data transfers of MRMAC. Added support for 4 ports of MRMAC for speeds 10G and 25G. MCDMA supports upto 16 channels but in this driver we have setup only one channel which is enough. Tested 10G and 25G on all 4 ports. Signed-off-by: Ashok Reddy Soma <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2021-07-26net: ethtool: Add ethernet speed macros for higher speedsAshok Reddy Soma
Add speed macro's for higher ethernet speeds to be used in u-boot networking drivers. Added Macros for speeds 14G, 20G, 25G, 40G, 50G, 56G, 100G and 200G inline with linux. Signed-off-by: Ashok Reddy Soma <[email protected]> Reviewed-by: Simon Glass <[email protected]> Acked-by: Ramon Fried <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2021-07-26clk: zynqmp: Add support for enabling clock on lpd_lsbusMichal Simek
lpd_lsbus is clock which is used by many IPs like dmas, gems, gpio, sdhcis, spis, ttcs, uarts, watchdog that's why make sense to also enable access to change this clock. For this clock you already get the rate. Signed-off-by: Michal Simek <[email protected]>
2021-07-26arm64: dts: zynqmp: Enable USB2.0 for zc1751-xm016-dc2Piyush Mehta
The board zynqmp-zc1751-xm016-dc2 support only USB2.0. This patch removes USB3.0 DT configuration for DC2 board. Signed-off-by: Piyush Mehta <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2021-07-26xilinx: Return ENVL_NOWHERE instead of ENVL_UNKNOWNMike Looijmans
The system refuses to boot without any environment, so return ENVL_NOWHERE when there's nowhere to store the environment instead of ENVL_UNKNOWN. This fixes that the board won't boot from eMMC when CONFIG_ENV_IS_IN_FAT is not defined, for example. Similar for other combinations. Fixes: 1025bd098aa8 "xilinx: zynqmp: Add support for saving variables" Signed-off-by: Mike Looijmans <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2021-07-26mmc: zynq_sdhci: Make variables/structure staticMichal Simek
All these variables/structure are local and should be static. Issues are reported by sparse: drivers/mmc/zynq_sdhci.c:49:11: warning: symbol 'zynqmp_iclk_phases' was not declared. Should it be static? drivers/mmc/zynq_sdhci.c:50:11: warning: symbol 'zynqmp_oclk_phases' was not declared. Should it be static? drivers/mmc/zynq_sdhci.c:53:11: warning: symbol 'versal_iclk_phases' was not declared. Should it be static? drivers/mmc/zynq_sdhci.c:54:11: warning: symbol 'versal_oclk_phases' was not declared. Should it be static? drivers/mmc/zynq_sdhci.c:546:24: warning: symbol 'arasan_ops' was not declared. Should it be static? Signed-off-by: Michal Simek <[email protected]> Signed-off-by: Ashok Reddy Soma <[email protected]> Reviewed-by: Jaehoon Chung <[email protected]>
2021-07-26mmc: zynq_sdhci: Fix kernel doc warningsMichal Simek
Fix these kernel doc warnings: drivers/mmc/zynq_sdhci.c:181: warning: contents before sections drivers/mmc/zynq_sdhci.c:236: warning: contents before sections drivers/mmc/zynq_sdhci.c:291: warning: contents before sections drivers/mmc/zynq_sdhci.c:297: warning: Function parameter or member 'degrees' not described in 'sdhci_versal_sdcardclk_set_phase' drivers/mmc/zynq_sdhci.c:354: warning: contents before sections drivers/mmc/zynq_sdhci.c:360: warning: Function parameter or member 'degrees' not described in 'sdhci_versal_sampleclk_set_phase' drivers/mmc/zynq_sdhci.c:467: warning: contents before sections Signed-off-by: Michal Simek <[email protected]> Signed-off-by: Ashok Reddy Soma <[email protected]> Reviewed-by: Jaehoon Chung <[email protected]>
2021-07-26mmc: zynq_sdhci: Split set_tapdelay function to in and outAshok Reddy Soma
Split arasan_zynqmp_set_tapdelay() to handle input and output tapdelays separately. This is required to handle zero values for ITAP and OTAP values. If we dont split, we will have to remove the if() in the function, which makes ITAP values to be overwritten when OTAP values are called to set and vice-versa. Restrict tap_delay value calculated to max allowed 8 bits for ITAP and 6 bits for OTAP for ZynqMP. Signed-off-by: Ashok Reddy Soma <[email protected]> Reviewed-by: Jaehoon Chung <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2021-07-26mmc: zynq_sdhci: Use Mask writes for Tap delaysAshok Reddy Soma
Restrict tap_delay value to the allowed size(8bits for itap and 6 bits for otap) before writing to the tap delay register. Clear ITAP and OTAP delay bits before updating with the new tap value for Versal platform. Signed-off-by: Ashok Reddy Soma <[email protected]> Reviewed-by: Jaehoon Chung <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2021-07-26mmc: zynq_sdhci: Allow configuring zero Tap valuesAshok Reddy Soma
Allow configuring ITAP and OTAP values with zero to avoid failures in some cases (one of them is SD boot mode). Legacy, SDR12 modes require to program the ITAP and OTAP values as zero, whereas for SDR50 and SDR104 modes ITAP value is zero. In SD boot mode firmware configures the SD ITAP and OTAP values and in this case u-boot has to re-configure required tap values(including zero) based on the operating mode. Signed-off-by: Ashok Reddy Soma <[email protected]> Reviewed-by: Jaehoon Chung <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2021-07-26mmc: zynq_sdhci: Resolve uninitialized return valueAshok Reddy Soma
set_phase() functions are not modifying the ret value and returning the same uninitialized ret, return 0 instead. Keep the return type as int to return errors when the tapdelay's are set via xilinx_pm_request() in future. Signed-off-by: Ashok Reddy Soma <[email protected]> Reviewed-by: Jaehoon Chung <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2021-07-26xilinx: zynqmp: increase CONFIG_SYS_SPL_MALLOC_SIZE to 16MBRicardo Salveti
commit 03f1f78a9b44 ("spl: fit: Prefer a malloc()'d buffer for loading images")' changed the way buffer allocation worked for SPL to a more flexible method. For xilinx zynqmp the 1MB buffer is not necessarily enough when dealing with complex fit images (e.g. containing FPGA/TF-A/OP-TEE/U-Boot proper), which can easily reach up to 10MB, so increase the default CONFIG_SYS_SPL_MALLOC_SIZE size to 16MB to cover more advanced scenarios. Signed-off-by: Ricardo Salveti <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2021-07-24Merge tag 'efi-2021-10-rc1-3' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2021-10-rc1-3 Documentation: provide Makefile documentation SMBIOS: generate BIOS release date based on UEFI version improve error handling in SMBIOS table generation UEFI: correct handling of signed capsule if authentication if off
2021-07-24Merge branch '2021-07-24-arm-and-platform-updates'Tom Rini
- dragonboard410c, synquacer, aspeed fixes / updates - pl011 serial driver fixes - Two generic arm bugfixes
2021-07-24serial: pl011: Enable DEBUG_UART_PL011 in SPLChen Baozi
Commit b81406db51a6 ("arm: serial: Add debug UART capability to the pl01x driver") add supports to use pl01x as a debug UART. However, due to CONFIG_IS_ENABLED macro requires CONFIG_SPL_* prefix, the _debug_uart_init() would not choose TYPE_PL011 in SPL build. This patch fixes the bug by judging CONFIG_DEBUG_UART_PL011 explicitly. Signed-off-by: Chen Baozi <[email protected]> Reviewed-by: Simon Glass <[email protected]>
2021-07-24reset: ast2600: Fix missing reference operatorChia-Wei Wang
Fix missing reference operator '&' to correctly get HW register addresses for writel(). Signed-off-by: Chia-Wei Wang <[email protected]>
2021-07-24MAINTAINERS: correct the path of UEFI docsAKASHI Takahiro
Change the path from doc/uefi to doc/develop/uefi. Fixes: commit d1ceeeff6c2e ("doc: Move UEFI under develop/") Signed-off-by: AKASHI Takahiro <[email protected]> Reviewed-by: Heinrich Schuchardt <[email protected]>
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