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There is no good reason to use a sequence from rand() here. We may as well
invent our own sequence.
This should molify Coverity which does not use rand() being used.
Signed-off-by: Simon Glass <[email protected]>
Reported-by: Coverity (CID: 312949)
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Clang has -Wself-assign enabled by default under -Wall and so when
building with -Werror we would get an error here. Inspired by Linux
kernel git commit a21151b9d81a ("tools/build: tweak unused value
workaround") make use of the fact that both Clang and GCC support
casting to `void` as the method to note that something is intentionally
unused.
Signed-off-by: Tom Rini <[email protected]>
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- Various clk/pinctrl updates to re-sync with Linux and other fixes
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Increase the BOOTM_LEN to 32M . This would allow a bigger kernel image to be
booted, for example the multi_v7_defconfig.
Loading Kernel Image
Image too large: increase CONFIG_SYS_BOOTM_LEN
Must RESET board to recover
resetting ...
Signed-off-by: Eugen Hristev <[email protected]>
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The V3U SoC has several unlock registers, one per register group. They
reside at offset zero in each 0x200 bytes-sized block.
To avoid adding yet another table to the PFC implementation, this
patch adds the option to specify an address mask instead of the fixed
address in sh_pfc_soc_info::unlock_reg.
This is a direct port of Linux 5.12 commit e127ef2ed0a6
("pinctrl: renesas: Implement unlock register masks") by
Ulrich Hecht <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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The help text for Gen2 entries had a copy paste error, still containing
the Gen3 string, while the description was correctly listing Gen2. Fix
the help text.
Signed-off-by: Marek Vasut <[email protected]>
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The help text in the Kconfig file was always a copy of the same thing.
Move single copy into the common PFC driver entry instead. Also fix a
copy-paste error in the PFC help text, which identified PFC as clock.
Signed-off-by: Marek Vasut <[email protected]>
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Pass struct udevice to rcar_gpio_set_direction() in preparation of
quirk handling in rcar_gpio_set_direction(). No functional change.
Signed-off-by: Marek Vasut <[email protected]>
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Most of the PLLx, MAIN, FIXED clock handlers are calling very similar
code, which determines parent rate and then applies multiplication and
division. The only difference is whether multiplication is fixed factor
or coming from CRx register. Deduplicate the code into a single function.
Signed-off-by: Marek Vasut <[email protected]>
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Base on Linux v5.10-rc2, commit 8b652aa8a1fb by Yoshihiro Shimoda
To support other register layouts in the future, add register pointers
of {control,status,reset,reset_clear}_regs into struct cpg_mssr_info
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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From Linux v5.10-rc2, commit ffbf9cf3f946 by Yoshihiro Shimoda
Introduce enum clk_reg_layout to support multiple register layout variants
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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CPG IP in some specific Renesas SoCs (i.e. new R8A779A0 V3U SoC)
requires a different setting procedure. Make struct cpg_mssr_info
accessible to handle the clock setting in that case.
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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The MODEMR register offset changed on R8A779A0, make the MODEMR offset
configurable. Fill the offset in on all clock drivers. No functional
change.
Based off "clk: renesas: Make CPG Reset MODEMR offset accessible from
struct cpg_mssr_info" by Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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This supports RPCD2 clock handling. While at it, add the check point
for RPC-IF clock RPCD2 Frequency Division Ratio, since it must be odd
number
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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This patch fixes Realtime Module Stop Control Register (RMSTPCR) offsets
based on R-Car Gen3, H2/M2/M2N/E2/E2X hardware user's manual.
The r8a73a4 only has RMSTPCR0 - RMSTPCR5 so this calculation change
doesn't affect it.
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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RPC clk_get_rate will return error code instead of expected clock rate.
Fix this.
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
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Reinstate RPC clock on D3/E3 after Linux 5.12 synchronization.
The D3 and E3 clock drivers do not contain RPC clock entries
mainline Linux yet.
Signed-off-by: Marek Vasut <[email protected]>
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Synchronize R-Car Gen3 clock tables with Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut <[email protected]>
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Synchronize R-Car Gen2 clock tables with Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut <[email protected]>
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Synchronize RZ/G2 clock tables with Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut <[email protected]>
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- Sync Armada mvpp2 ethernet driver with Marvell version (misc Marvell
authors)
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With commit 8678776df6f5 (arm: mvebu: armada-3720-uDPU: fix PHY mode
definition to sgmii-2500) the PHY mode was switch to "sgmii-2500", even
when this is functionally incorrect since "2500base-x" was not supported
in U-Boot at that time. As this mode is now supported (at least present
in the headers), this patch moves back to the orinal version.
Signed-off-by: Stefan Roese <[email protected]>
Cc: Jakov Petrina <[email protected]>
Cc: Vladimir Vid <[email protected]>
Cc: Luka Perkov <[email protected]>
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Until now the mvpp2 driver used an extra 'phy-speed'
DT property in order to differentiate between the
SGMII and SGMII @2.5GHz. As there is a dedicated
PHY_INTERFACE_MODE_SGMII_2500 flag to mark the latter
start using it and drop the custom flag.
Signed-off-by: Marcin Wojtas <[email protected]>
Reviewed-by: Stefan Chulski <[email protected]>
Reviewed-by: Nadav Haklai <[email protected]>
Tested-by: Nadav Haklai <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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Currently, there are 2 valid cases for interface, PHY
and mdio relation:
- If an interface has PHY handler, it'll call
mdio_mii_bus_get_from_phy(), which will register
MDIO bus.
- If we want to use fixed-link for an interface,
PHY handle is not defined in the DTS, and no
MDIO is registered.
There is a third case, for some boards (with switch),
the MDIO is used for switch configuration, but the interface
itself uses fixed link. This patch allows this option by
checking if fixed-link subnode is defined, in this case,
MDIO bus is registers, but the PHY address is set to
PHY_MAX_ADDR for this interface, so this interface will
not try to access the PHY later on.
Signed-off-by: Stefan Chulski <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Ben Peled <[email protected]>
Reviewed-by: Stefan Chulski <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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Signed-off-by: Ben Peled <[email protected]>
Reviewed-by: Stefan Chulski <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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Signed-off-by: Ben Peled <[email protected]>
Reviewed-by: Stefan Chulski <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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GMII_SPEED should be enabled for 2.5G speed
Signed-off-by: Stefan Chulski <[email protected]>
Reviewed-by: Yan Markman <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Because the mvpp2 driver now relies on the PHYLIB and
the external MDIO driver, configuring low level
SMI bus settings is redundant.
Signed-off-by: Marcin Wojtas <[email protected]>
Reviewed-by: Kostya Porotchkin <[email protected]>
Reviewed-by: Stefan Chulski <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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Signed-off-by: Stefan Chulski <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
Reviewed-by: Ramon Fried <[email protected]>
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1. Differ between Port1 RGMII and SFI modes in Netcomplex config.
2. Remove XPCS config from SFI mode.
Port1 doesn't XPCS domain, XPCS config should be removed.
Access to Port1 XPCS can cause stall.
3. Add Port1 MPCS configurations.
Signed-off-by: Stefan Chulski <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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Signed-off-by: Stefan Chulski <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
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https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2021.07-rc3
ZynqMP:
- Syncup DT with Linux kernel
- Fix mmc mini configurations via DT
- Add pinctrl/psgtr description to DTs
- Add DTs for Kria boards
- Enable RTC and Time commands
Versal:
- Fix early BSS section location
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It will need larger heap size for u-boot-spl to load u-boot.itb which
be generated from binman than USE_SPL_FIT_GENERATOR.
Signed-off-by: Rick Chen <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
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Now that we have switched to binman to generate u-boot.itb for all
RISC-V boards, USE_SPL_FIT_GENERATOR is no longer needed and can
be dropped.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Use the new BINMAN_STANDALONE_FDT option for AE350 based SPL defconfigs,
so that binman is now used to generate u-boot.itb.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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By utilizing the newly introduced BINMAN_STANDALONE_FDT option, along
with a new dedicated device tree source file for the QEMU virt target
used for binman only, we can now use binman to generate u-boot.itb.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Sort the RISC-V DTS build targets by their Kconfig target names in
alphabetical order.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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For scenarios like OF_BOARD or OF_PRIOR_STAGE, no device tree blob is
provided in the U-Boot build phase hence the binman node information
is not available. In order to support such use case, a new Kconfig
option BINMAN_STANDALONE_FDT is introduced, to tell the build system
that a device tree blob containing binman node is explicitly required
when using binman to package U-Boot.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Generally speaking BINMAN_FDT makes sense for OF_SEPARATE or OF_EMBED.
For the other OF_CONTROL methods, it's quite possible binman node is
not available as binman is invoked during the build phase instead of
runtime. Let's only turn it on for OF_SEPARATE or OF_EMBED by default.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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At present SiFive Unleashed board uses the Makefile to create the FIT,
using USE_SPL_FIT_GENERATOR, which is deprecated as per the Makefile
warning. Update to use binman instead.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This updates the make rules to pass OpenSBI blob to binman.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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Add an entry for RISC-V OpenSBI's 'fw_dynamic' firmware payload.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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Currently there are 2 binman test cases using the same 172 number.
It seems that 172_fit_fdt.dts was originally named as 170_, but
commit c0f1ebe9c1b9 ("binman: Allow selecting default FIT configuration")
changed its name to 172_ for no reason. Let's change it back.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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This is wrongly referring to Intel ME, which should be ATF.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
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It needs a space around '-a'.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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It should be FDT, not FTD.
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
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Right now U-Boot is not aware about date/time that's why enable it by
default also with EFI runtime service for setting time.
Signed-off-by: Michal Simek <[email protected]>
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U-Boot expects to be linked to a specific hard-coded address and to
be loaded to and run from that address. CONFIG_POSITION_INDEPENDENT
config lifts that restriction & allowing the code to be loaded to
and executed from almost any address.
As we enabled CONFIG_POSITION_INDEPENDENT, CONFIG_INIT_SP_RELATIVE
is enabled by default, where it will set the early stack pointer at
runtime by adding an offset value to &_bss_start. The offset value
is taken from SYS_INIT_SP_BSS_OFFSET.
SYS_INIT_SP_BSS_OFFSET offset should be large enough so that the
early malloc region, global data (gd), and early stack should fit.
With commit d8fabcc424bd ("arm64: versal: Increase SYS_MALLOC_F_LEN")
SYS_MALLOC_F_LEN is increased from 32KB to 1MB, so we need to
accommodate this space with SYS_INIT_SP_BSS_OFFSET. Hence increasing
SYS_INIT_SP_BSS_OFFSET to 1.5MB.
Signed-off-by: T Karthik Reddy <[email protected]>
Acked-by: Ashok Reddy Soma <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
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